CN106711230A - Thin film transistor - Google Patents

Thin film transistor Download PDF

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Publication number
CN106711230A
CN106711230A CN201710007292.5A CN201710007292A CN106711230A CN 106711230 A CN106711230 A CN 106711230A CN 201710007292 A CN201710007292 A CN 201710007292A CN 106711230 A CN106711230 A CN 106711230A
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China
Prior art keywords
thin film
film transistor
silver
grid
zinc oxide
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CN201710007292.5A
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Chinese (zh)
Inventor
张志云
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Xian University of Science and Technology
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Xian University of Science and Technology
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Priority to CN201710007292.5A priority Critical patent/CN106711230A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66969Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

The present invention discloses a thin film transistor. The thin film transistor comprises a substrate, a gate arranged on the substrate, a grid insulation layer, a source and a drain which are arranged on the substrate and configured to cover the grid, and a silver doping zinc oxide tin-alloy layer. The opposite two sides of the surface of the grid insulation layer are provided with the source and the drain. The silver doping zinc oxide tin-alloy layer is arranged at the surface of the grid insulation layer, and is contacted with the two ends of the source and the drain. The silver doping zinc oxide tin-alloy layer comprises a channel area, and the channel area is located between the source and the drain. The rate of the silver and the zinc oxide tin is 1-2% by weight in silver doping zinc oxide tin-alloy layer. The thin film transistor is mixed with the silver element to facilitate improving the carrier mobility in the electrode of the zinc oxide tin thin film, a ZnSnO-TFT with high field effect mobility can be obtained through adoption of an indium tin oxide glass substrate and the low temperature annealing technology, the production process is simple and the usage life is long.

Description

A kind of thin film transistor (TFT)
Technical field
The present invention relates to technical field of electronic components, more particularly to a kind of thin film transistor (TFT).
Background technology
Thin film transistor (TFT) is one of species of field-effect transistor, rough production method be deposited on substrate it is various not Same film, such as semiconductor active layer, dielectric layer and metal electrode layer.Thin film transistor (TFT) has to the service behaviour of display device Highly important effect.Thin film transistor (TFT) generally comprises the parts such as grid, drain electrode, source electrode and channel layer, when grid is applied During with positive voltage, grid voltage produces electric field in gate insulation layer, and power line points to semiconductor surface by gate electrode, and is produced at surface Raw charge inducing increases with gate voltage, and semiconductor surface will be changed into electron accumulation layer by depletion layer, forms inversion layer and works as When reaching strong inversion (when reaching cut-in voltage), source just has carrier and works as source-drain voltage by raceway groove between leakage plus voltage During very little, conducting channel is approximately a constant resistance, and leakage current increases with source-drain voltage and linearly increases;When source-drain voltage is very big When, it can produce influence to gate voltage so that electric field is gradually weakened by source to drain terminal in gate insulation layer, semiconductor surface transoid Electronics is gradually reduced by source to drain terminal in layer, and channel resistance increases as source-drain voltage increases, and leakage current increase becomes slow Slowly, correspondence linear zone is to saturation region transition;When source-drain voltage increases to a certain extent, drain terminal inversion layer thickness is kept to zero, and voltage exists Increase, device enters saturation region in actual LCD productions, mainly using a-Si:The ON state (being more than cut-in voltage) of HTFT is to picture Plain capacitor fast charging, the voltage of pixel capacitance is kept using OFF state, so as to realize the unification of quick response and good storage.
Relatively low in traditional non-crystalline silicon mobility, light sensitivity is strong, polycrystalline SiTFT complex process, polycrystalline organic thin film Body pipe is difficult to overcome low life-span, the weakness of low mobility again.
The content of the invention
The invention aims to solve shortcoming present in prior art, and a kind of thin film transistor (TFT) for proposing.
To achieve these goals, present invention employs following technical scheme:
A kind of thin film transistor (TFT), including substrate, the grid being arranged on substrate, the grid that are arranged on substrate and cover grid Insulating barrier, source electrode, drain electrode, also including silver doped zinc oxide tin alloy layers, opposite sides is provided with the surface of the gate insulation layer Source electrode, drain electrode, the silver doped zinc oxide tin alloy layers be arranged on the surface of gate insulation layer and source electrode, drain electrode two ends respectively with Its contact, the silver doped zinc oxide tin alloy layers include channel region, and channel region is located between source electrode, drain electrode, Ag doping Silver accounts for the 1-2% of zinc-tin oxide weight in zinc-tin oxide alloy-layer.
Preferably, the grid is indium tin oxide grid.
Preferably, the gate insulation layer is silica membrane.
A kind of preparation method of above-mentioned thin film transistor (TFT), comprises the following steps:
Step 1:The photoetching indium tin oxide grid on substrate;
Step 2:The silicon dioxide gate insulation layer of photoetching cover grid pole on substrate;
Step 3:Silver doped zinc oxide tin alloy layers are formed on silicon dioxide gate insulation layer;
Step 4:Plating source electrode, drain electrode;
Step 5:Process annealing treatment.
Preferably, in the step 3, the silver element in silver doped zinc oxide tin alloy layers will by radio-frequency magnetron sputter method The mode that silver element is mixed in target mixes zinc-tin oxide film.
Preferably, the process conditions for preparing silver doped zinc oxide tin alloy layers are to be evacuated to 1.9 × 10-4Pa, leads to Start sputtering after entering to be passed through the argon gas and oxygen mixed gas that volume ratio is 1: 3.
Preferably, in the step 4 by small ion sputter deposit thickness for 100nm metal platinum be used as source electrode, Drain electrode.
Preferably, in the step 5, the specific method of process annealing treatment is:Sample is put into annealing dress at room temperature Intensification is postponed, is annealed 20 minutes for 80-100 DEG C in air atmosphere, taken out after natural cooling.
The operation principle of rf magnetron sputtering refer to electronics in the presence of electric field E, it is former with argon during substrate is flown to Son collides, and its ionization is produced Ar cations and new electronics;New electronics flies to substrate, and Ar ions are under electric field action Cathode target is flown in acceleration, and with high-energy bombardment target surface, sputters target.In sputtering particle, neutral target atom Or molecule deposition forms film on substrate, and the secondary electron for producing can be subject to electric field and magnetic fields, produce E (electric field) × B (magnetic field) signified direction drift, abbreviation E × B drifts, its movement locus is similar to a cycloid.It is if toroidal magnetic field, then electric Son just moves in a circle in approximate cycloid form on target surface, and their motion path is not only very long, and is bound in close In the heating region on target surface, and substantial amounts of Ar is ionized in this region bombard target, it is achieved thereby that high Sedimentation rate.With the increase of collision frequency, the energy ezpenditure of secondary electron totally, is gradually distance from target surface, and electric field E's It is eventually deposited on substrate under effect
In the present invention, zinc-tin oxide finds as semiconductor channel layer material through development test, mixes silver element favourable Carrier mobility in the electrode for improving zinc-tin oxide film, with the increase of incorporation, the electronics of zinc-tin oxide film Mobility can reach a peak value, then be gradually reduced, best results when silver element accounts for the 1-2% of zinc-tin oxide weight, can reach 10cm2/v/s;Process annealing treatment can reduce the internal flaw of film, to reach the purpose of the quality for improving film;It is another Aspect can also improve the surface of film so that the contact between film and another layer film or electrode is more preferable, using indium tin Oxide glass substrate and low temperature annealing process, can obtain the ZnSnO-TFT thin film transistor (TFT)s of high field-effect mobility, produce work Skill is simple, long service life.
Brief description of the drawings
Fig. 1 is a kind of structural representation of thin film transistor (TFT) proposed by the present invention.
In figure:1 substrate, 2 grids, 3 gate insulation layers, 4 silver doped zinc oxide tin alloy layers, 5 source electrodes, 6 drain electrodes.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.
The rf magnetron sputtering unit type used in the present embodiment is GP-560b type dual chamber magnetron sputtering deposition systems; The model Yue Loong epoch LJ-16 of small ion sputter;Annealing device model RTP-500 fast heat treatment devices.
First embodiment
Reference picture 1, a kind of thin film transistor (TFT), including substrate 1, be arranged on substrate grid 2, be arranged on substrate and cover The gate insulation layer 3 of lid grid, source electrode 5, drain electrode 6, also including silver doped zinc oxide tin alloy layers 4, the surface of the gate insulation layer 3 Upper opposite sides is provided with source electrode 5, drain electrode 6, and the silver doped zinc oxide tin alloy layers 4 are arranged on the surface and source of gate insulation layer 3 Pole 5, the two ends of drain electrode 6 are in contact with it respectively, and the silver doped zinc oxide tin alloy layers 4 include channel region, channel region position Between source electrode 5, drain electrode 6, silver accounts for the 1% of zinc-tin oxide weight in silver doped zinc oxide tin alloy layers 4, and the grid 2 is indium Tin-oxide grid, the gate insulation layer 3 is silica membrane.
A kind of preparation method of above-mentioned thin film transistor (TFT), comprises the following steps:
Step 1:The photoetching indium tin oxide grid on substrate;
Step 2:The silicon dioxide gate insulation layer of photoetching cover grid pole on substrate;
Step 3:Silver doped zinc oxide tin alloy layers, silver doped zinc oxide tin alloy are formed on silicon dioxide gate insulation layer Silver element in layer mixes zinc-tin oxide film, technique by way of radio-frequency magnetron sputter method mixes in target silver element Condition is to be evacuated to 1.9 × 10-4Pa, sputtering is started after being passed through the argon gas and oxygen mixed gas that volume ratio is 1: 3;
Step 4:Plating source electrode, drain electrode, by small ion sputter deposit thickness for 100nm metal platinum be used as source electrode, Drain electrode;
Step 5:Process annealing is processed, and specific method is:Heated up after sample to be put into annealing device at room temperature, in air Annealed 20 minutes for 80 DEG C in atmosphere, taken out after natural cooling.
Second embodiment
Reference picture 1, a kind of thin film transistor (TFT), including substrate 1, be arranged on substrate grid 2, be arranged on substrate and cover The gate insulation layer 3 of lid grid, source electrode 5, drain electrode 6, also including silver doped zinc oxide tin alloy layers 4, the surface of the gate insulation layer 3 Upper opposite sides is provided with source electrode 5, drain electrode 6, and the silver doped zinc oxide tin alloy layers 4 are arranged on the surface and source of gate insulation layer 3 Pole 5, the two ends of drain electrode 6 are in contact with it respectively, and the silver doped zinc oxide tin alloy layers 4 include channel region, channel region position Between source electrode 5, drain electrode 6, silver accounts for the 1.5% of zinc-tin oxide weight in silver doped zinc oxide tin alloy layers 4, and the grid 2 is Indium tin oxide grid, the gate insulation layer 3 is silica membrane.
A kind of preparation method of above-mentioned thin film transistor (TFT), comprises the following steps:
Step 1:The photoetching indium tin oxide grid on substrate;
Step 2:The silicon dioxide gate insulation layer of photoetching cover grid pole on substrate;
Step 3:Silver doped zinc oxide tin alloy layers, silver doped zinc oxide tin alloy are formed on silicon dioxide gate insulation layer Silver element in layer mixes zinc-tin oxide film, technique by way of radio-frequency magnetron sputter method mixes in target silver element Condition is to be evacuated to 1.9 × 10-4Pa, sputtering is started after being passed through the argon gas and oxygen mixed gas that volume ratio is 1: 3;
Step 4:Plating source electrode, drain electrode, by small ion sputter deposit thickness for 100nm metal platinum be used as source electrode, Drain electrode;
Step 5:Process annealing is processed, and specific method is:Heated up after sample to be put into annealing device at room temperature, in air Annealed 20 minutes for 90 DEG C in atmosphere, taken out after natural cooling.
3rd embodiment
Reference picture 1, a kind of thin film transistor (TFT), including substrate 1, be arranged on substrate grid 2, be arranged on substrate and cover The gate insulation layer 3 of lid grid, source electrode 5, drain electrode 6, also including silver doped zinc oxide tin alloy layers 4, the surface of the gate insulation layer 3 Upper opposite sides is provided with source electrode 5, drain electrode 6, and the silver doped zinc oxide tin alloy layers 4 are arranged on the surface and source of gate insulation layer 3 Pole 5, the two ends of drain electrode 6 are in contact with it respectively, and the silver doped zinc oxide tin alloy layers 4 include channel region, channel region position Between source electrode 5, drain electrode 6, silver accounts for the 2% of zinc-tin oxide weight in silver doped zinc oxide tin alloy layers 4, and the grid 2 is indium Tin-oxide grid, the gate insulation layer 3 is silica membrane.
A kind of preparation method of above-mentioned thin film transistor (TFT), comprises the following steps:
Step 1:The photoetching indium tin oxide grid on substrate;
Step 2:The silicon dioxide gate insulation layer of photoetching cover grid pole on substrate;
Step 3:Silver doped zinc oxide tin alloy layers, silver doped zinc oxide tin alloy are formed on silicon dioxide gate insulation layer Silver element in layer mixes zinc-tin oxide film, technique by way of radio-frequency magnetron sputter method mixes in target silver element Condition is to be evacuated to 1.9 × 10-4Pa, sputtering is started after being passed through the argon gas and oxygen mixed gas that volume ratio is 1: 3;
Step 4:Plating source electrode, drain electrode, by small ion sputter deposit thickness for 100nm metal platinum be used as source electrode, Drain electrode;
Step 5:Process annealing is processed, and specific method is:Heated up after sample to be put into annealing device at room temperature, in air Annealed 20 minutes for 100 DEG C in atmosphere, taken out after natural cooling.
The above, the only present invention preferably specific embodiment, but protection scope of the present invention is not limited thereto, Any one skilled in the art the invention discloses technical scope in, technology according to the present invention scheme and its Inventive concept is subject to equivalent or change, should all be included within the scope of the present invention.

Claims (8)

1. a kind of thin film transistor (TFT), including substrate, the grid being arranged on substrate, the grid for being arranged on substrate and covering grid are exhausted Edge layer, source electrode, drain electrode, it is characterised in that:Also include silver doped zinc oxide tin alloy layers, it is relative on the surface of the gate insulation layer Both sides are provided with source electrode, drain electrode, and the silver doped zinc oxide tin alloy layers are arranged on the surface of gate insulation layer and source electrode, the two of drain electrode End is in contact with it respectively, and the silver doped zinc oxide tin alloy layers include channel region, and channel region is located at source electrode, drains it Between, silver accounts for the 1-2% of zinc-tin oxide weight in silver doped zinc oxide tin alloy layers.
2. a kind of thin film transistor (TFT) according to claim 1, it is characterised in that:The grid is indium tin oxide grid.
3. a kind of thin film transistor (TFT) according to claim 1, it is characterised in that:The gate insulation layer is that silica is thin Film.
4. the preparation method of a kind of thin film transistor (TFT) according to claim any one of 1-3, it is characterised in that:Including as follows Step:
Step 1:The photoetching indium tin oxide grid on substrate;
Step 2:The silicon dioxide gate insulation layer of photoetching cover grid pole on substrate;
Step 3:Silver doped zinc oxide tin alloy layers are formed on silicon dioxide gate insulation layer;
Step 4:Plating source electrode, drain electrode;
Step 5:Process annealing treatment.
5. the preparation method of a kind of thin film transistor (TFT) according to claim 4, it is characterised in that:In the step 3, silver is mixed Silver element in miscellaneous zinc-tin oxide alloy-layer mixes oxygen by way of radio-frequency magnetron sputter method mixes in target silver element Change zinc-tin film.
6. the preparation method of a kind of thin film transistor (TFT) according to claim 5, it is characterised in that:It is described to prepare Ag doping oxygen Change the process conditions of Zinc-tin alloy layer to be evacuated to 1.9 × 10-4Pa, the argon gas and oxygen for being passed through volume ratio for 1: 3 is mixed Start sputtering after closing gas.
7. the preparation method of a kind of thin film transistor (TFT) according to claim 4, it is characterised in that:Pass through in the step 4 Small ion sputter deposit thickness is the metal platinum of 100nm as source electrode, drain electrode.
8. the preparation method of a kind of thin film transistor (TFT) according to claim 4, it is characterised in that:In the step 5, low temperature The specific method of annealing is:Heated up after sample to be put into annealing device at room temperature, 80-100 DEG C is moved back in air atmosphere Fire 20 minutes, takes out after natural cooling.
CN201710007292.5A 2017-01-06 2017-01-06 Thin film transistor Pending CN106711230A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101582453A (en) * 2008-05-15 2009-11-18 三星电子株式会社 Transistor, semiconductor device and method of manufacturing the same
CN101621075A (en) * 2008-06-30 2010-01-06 三星移动显示器株式会社 Thin film transistor, method of manufacturing the same and flat panel display device having the same
US20110303918A1 (en) * 2010-06-11 2011-12-15 Samsung Mobile Display Co., Ltd. Organic light-emitting display and method of manufacturing the same
CN104241391A (en) * 2013-06-21 2014-12-24 三星显示有限公司 Thin film transistor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101582453A (en) * 2008-05-15 2009-11-18 三星电子株式会社 Transistor, semiconductor device and method of manufacturing the same
CN101621075A (en) * 2008-06-30 2010-01-06 三星移动显示器株式会社 Thin film transistor, method of manufacturing the same and flat panel display device having the same
US20110303918A1 (en) * 2010-06-11 2011-12-15 Samsung Mobile Display Co., Ltd. Organic light-emitting display and method of manufacturing the same
CN104241391A (en) * 2013-06-21 2014-12-24 三星显示有限公司 Thin film transistor

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