CN106711034A - Method for forming semiconductor structure - Google Patents
Method for forming semiconductor structure Download PDFInfo
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- CN106711034A CN106711034A CN201510548258.XA CN201510548258A CN106711034A CN 106711034 A CN106711034 A CN 106711034A CN 201510548258 A CN201510548258 A CN 201510548258A CN 106711034 A CN106711034 A CN 106711034A
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Abstract
The invention provides a method for forming a semiconductor structure. The method comprises a step of providing a substrate, a step of forming an interface layer at the surface of the substrate, a step of forming a high k dielectric layer at the surface of the interface layer, and a step of carrying out first annealing process which is used for doping optimization ions in the high k dielectric layer, wherein the optimization ions are used for filling the defects in the high k dielectric layer. The performance of the formed semiconductor structure is improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of forming method of semiconductor structure.
Background technology
With the fast development of ic manufacturing technology, promote the semiconductor devices in integrated circuit, especially
It is the size of MOS (Metal Oxide Semiconductor, Metal-oxide-semicondutor) device not
Reduce disconnectedly, being miniaturized and integrated requirement, and transistor device for integrated circuit development is met with this
It is one of important component in MOS device.
For semiconductor devices, as the size of semiconductor devices persistently reduces, prior art is with oxygen
During the gate dielectric layer that SiClx or silicon oxy-nitride material are formed, semiconductor devices cannot have been met for performance
It is required that.The transistor for especially being formed as gate dielectric layer using silica or silicon oxynitride easily produces electric leakage
A series of problems, such as stream and impurity spread, so as to influence the threshold voltage of transistor, causes transistor
Reliability and stability decline.
To solve problem above, a kind of transistor constituted with high-K gate dielectric layer and metal gate is suggested, i.e.,
High-k/metal gate (HKMG, High K Metal Gate) transistor.The high-k/metal gate transistor is used
K (dielectric constant) dielectric material high replaces conventional silica or silicon oxynitride as gate dielectric material, with
Metal material or metal compound material substitute traditional polysilicon gate material, form metal gate.It is described
High-k/metal gate transistor can reduce leakage current in the case of minification, reduce operating voltage
And power consumption, the performance of transistor is improved with this.
In addition, the high K medium material can also be used as memory device (such as DRAM device)
Gate dielectric layer between grid structure and substrate, or as the dielectric layer between capacitor the two poles of the earth.
However, being widely used with high K medium material, the shortcoming of high K medium material is to semiconductor devices
The harmful effect for causing is also serious all the more.
The content of the invention
The problem that the present invention is solved is to provide a kind of forming method of semiconductor structure, the semiconductor for being formed
Structural behaviour improves.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：There is provided
Substrate；Boundary layer is formed in the substrate surface；High-k dielectric layer is formed in the interface layer surfaces；Enter
The annealing process of row first, first annealing process is used for the optimization ion that adulterated in the high-k dielectric layer,
The optimization ion is used for the defect filled up in the high-k dielectric layer.
Optionally, the optimization ion includes one or more in Nitrogen ion, hydrogen ion and fluorine ion.
Optionally, the material of the high-k dielectric layer is Hf based dielectric materials.
Optionally, the Hf based dielectric materials are HfO2。
Optionally, the material of the boundary layer is silica；The formation process of the boundary layer is thermal oxide
Technique.
Optionally, after the boundary layer is formed, before forming the high-k dielectric layer, carry out described
First annealing process.
Optionally, after the high-k dielectric layer is formed, first annealing process is carried out.
Optionally, the gas of first annealing process includes NH2F。
Optionally, the parameter of first annealing process includes：Annealing temperature be 850 DEG C~1050 DEG C, gas
It is 1Torr~1ATM to press.
Optionally, the gas of first annealing process also includes H2。
Optionally, NH described in first annealing process2F and H2Volume ratio be 1:100~100:1.
Optionally, also include：After high-k dielectric layer is formed, the second annealing process is carried out；Described
The gas of two annealing process includes N2。
Optionally, also include：Before the boundary layer is formed, dummy grid is formed in the substrate surface
Structure, the dummy gate structure includes dummy gate layer and the side wall positioned at dummy gate layer sidewall surfaces；
Source region and drain region are formed in the substrate of the dummy gate structure both sides；Formed the source region and drain region it
Afterwards, dielectric layer is formed in the substrate surface, the dielectric layer exposes the top of the dummy gate structure
Surface；The dummy gate layer is removed, the opening for exposing substrate surface is formed in the dielectric layer；
The substrate surface for exposing that is open forms boundary layer；Sidewall surfaces and the boundary of bottom in the opening
Facing surface forms high-k dielectric layer.
Optionally, also include：Dummy grid film is formed on the high-k dielectric layer surface；Etch the pseudo- grid
Pole film, high-k dielectric layer and boundary layer, and section substrate surface is exposed, in high-k dielectric layer surface shape
Into dummy gate layer；Side wall is formed in the sidewall surfaces of the dummy gate layer, high-k dielectric layer and boundary layer；
Source region and drain region are formed in the substrate of the dummy gate layer, high-k dielectric layer, boundary layer and side wall both sides；
After the source region and drain region is formed, dielectric layer, the dielectric layer exposure are formed in the substrate surface
Go out the top surface of the dummy gate structure；The dummy gate layer is removed, forms sudden and violent in the dielectric layer
Expose the opening of high-k dielectric layer.
Optionally, the high-k dielectric layer surface in the opening forms the grid layer of filling full gate mouthful.
Optionally, the material of the grid layer is one or more in metal and metallic compound；It is described
Metal includes copper, tungsten, aluminium, silver, titanium and tantalum；The metallic compound includes titanium nitride and tantalum nitride.
Optionally, the substrate includes：Substrate, the fin positioned at substrate surface and positioned at substrate table
The table of the separation layer in face, the partial sidewall surface of the separation layer covering fin, and the separation layer
Top surface of the face less than fin.
Optionally, the boundary layer is located at the side wall and top surface of the fin.
Compared with prior art, technical scheme has advantages below：
In forming method of the invention, the defect that the optimization ion can be filled up in the high-k dielectric layer,
And the defect easily produces bigger relaxation electric current in relaxation process.On the one hand, the high K medium
The electron trap that is constituted of defect in layer can optimised ion filled up such that it is able to make high K medium
Layer in defect can pole removed from forbidden band so that electronics be difficult when being migrated in the high-k dielectric layer by
Electron trap is captured such that it is able to make the relaxation electric current that the high-k dielectric layer is produced in relaxation process
Reduce.On the other hand, the Lacking oxygen in the high-k dielectric layer can be filled up by the optimization ion,
Migrated in the high-k dielectric layer because of the attraction by Lacking oxygen so as to avoid the oxonium ion in boundary layer；
Polarized atom in the high-k dielectric layer is not easily susceptible to the interference of oxonium ion, Neng Gouyou in relaxation process
Effect ground reduces the relaxation electric current in high-k dielectric layer.And, the optimization ion will not reduce high K medium
The dielectric constant of layer.Therefore, the semiconductor structure performance improvement for being formed, by the semiconductor structure
Into transistor positive bias temperature it is unstable and negative temperature bias are unstable is inhibited.
Further, the optimization ion includes one or more in Nitrogen ion, hydrogen ion and fluorine ion.
Adulterate the Nitrogen ion, hydrogen ion and fluorine ion in the high-k dielectric layer, can not only fill up described
Defect in high-k dielectric layer, to reduce the relaxation electric current in high-k dielectric layer, additionally it is possible to improve the k high
The dielectric constant of dielectric layer, is conducive to the performance of the formed semiconductor structure of raising.
Further, the material of the high-k dielectric layer is Hf based dielectric materials.With the Hf bases medium material
Expect that leakage current produced in the semiconductor structure of composition is smaller, then the performance of the semiconductor structure for being formed
Preferably.And, can be reduced in high-k dielectric layer by the doping optimization ion in the high-k dielectric layer
Relaxation electric current.Therefore, the performance improvement of the semiconductor structure for being formed.
Brief description of the drawings
Fig. 1 to Fig. 7 is that the cross-section structure of the forming process of the semiconductor structure of one embodiment of the invention is illustrated
Figure；
Fig. 8 to Figure 10 is that the cross-section structure of the forming process of the semiconductor structure of another embodiment of the present invention shows
It is intended to；
Figure 11 to Figure 12 is the cross-section structure of the forming process of the semiconductor structure of further embodiment of this invention
Schematic diagram.
Specific embodiment
As stated in the Background Art, being widely used with high K medium material, the shortcoming of high K medium material
The harmful effect caused to semiconductor devices is also serious all the more.
Found by research, the atom in high K medium material can polarize under action of alternative electric field,
And electric equilibrium state, i.e. relaxation (Dielectric Relaxation, abbreviation DR) are reverted to by relaxation process
Phenomenon.In relaxation process, the atom being polarized in high K medium material needs certain relaxation time
To revert to electric equilibrium state, and in relaxation process, relaxation can be produced in the high K medium material
Electric current, so as to cause energy loss.Specifically, the polarization intensity in high K medium material has one to fall behind
In the phase angle of alternating electric field, and the energy loss that relaxation phenomena is caused is in the tangent value at the phase angle
Direct ratio, the tangent value at the phase angle is fissipation factor.
In the semiconductor devices constituted with high K medium material, capacitor element is due to the change of its working frequency
Change scope is smaller, and the energy loss that the relaxation phenomena causes is shared in the energy that alternating electric field is provided
Ratio it is smaller, therefore the change of the energy loss is smaller, then the energy loss is in controlled range.
However, for DRAM memory or MOS transistor, the excursion of its working frequency is larger,
By taking DRAM memory as an example, the scope of its working frequency is between 1GHz to 1Hz；And working frequency
Excursion it is big so that the energy loss that the relaxation phenomena causes is changed greatly, then the energy is damaged
Consumption is difficult to regulation and control, then the influence of the relaxation phenomena is more notable.
On the other hand, except the energy loss that relaxation phenomena causes, the leakage current in high K medium material
Easily cause the energy loss of semiconductor devices.In high K medium material, Hf based dielectric materials compared to
Other high K medium materials have relatively low leakage current；However, Hf based dielectric materials are while can produce higher
Relaxation electric current.Therefore, reduce, the relaxation electric current in Hf based dielectric materials can greatly improve partly leads
Energy loss problem in body device, improves with the performance of semiconductor device of high K medium material manufacture.
In order to reduce the relaxation electric current in Hf based dielectric materials, can in Hf based dielectric materials doped lanthanum
(La) ion and Nitrogen ion, the relaxation phenomena of Hf based dielectric materials is suppressed with this.However, in Hf bases
The lanthanum ion that adulterated in dielectric material can cause that the dielectric coefficient of Hf based dielectric materials is reduced, and easily cause institute's shape
Into semiconductor devices degradation.
In order to solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：Carry
For substrate；Boundary layer is formed in the substrate surface；High-k dielectric layer is formed in the interface layer surfaces；
Carry out the first annealing process, first annealing process be used to being adulterated in the high-k dielectric layer optimization from
Son, the optimization ion is used for the defect filled up in the high-k dielectric layer.
Wherein, the defect that the optimization ion can be filled up in the high-k dielectric layer, and the defect is held
Bigger relaxation electric current is easily produced in relaxation process.On the one hand, the defect institute in the high-k dielectric layer
The electron trap of composition can optimised ion filled up such that it is able to enable the defect in high-k dielectric layer
Pole removes from forbidden band so that electronics is difficult to be captured by electron trap when being migrated in the high-k dielectric layer,
Relaxation electric current so as to make the high-k dielectric layer produced in relaxation process reduces.On the other hand,
Lacking oxygen in the high-k dielectric layer can be filled up by the optimization ion, so as to avoid boundary layer
Interior oxonium ion is migrated because of the attraction by Lacking oxygen in the high-k dielectric layer；The high-k dielectric layer
Interior polarized atom is not easily susceptible to the interference of oxonium ion in relaxation process, can effectively reduce k high and be situated between
Relaxation electric current in matter layer.And, the optimization ion will not reduce the dielectric constant of high-k dielectric layer.
Therefore, the semiconductor structure performance improvement for being formed, the transistor formed by the semiconductor structure is just
Bias Temperature is unstable and negative temperature bias are unstable is inhibited.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings
Specific embodiment of the invention is described in detail.
Fig. 1 to Fig. 7 is that the cross-section structure of the forming process of the semiconductor structure of one embodiment of the invention is illustrated
Figure.
Refer to Fig. 1, there is provided substrate 100；Dummy gate structure 110 is formed on the surface of the substrate 100,
The dummy gate structure 110 includes dummy gate layer 111 and the side positioned at the sidewall surfaces of dummy gate layer 111
Wall 112.
In the present embodiment, the substrate 100 is planar substrates.The substrate 100 include silicon substrate,
Silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator (SOI) substrate, germanium on insulator (GOI) substrate,
Glass substrate or III-V substrate (such as silicon nitride or GaAs etc.).In the present embodiment, institute
Substrate 100 is stated for silicon substrate.
There is isolation structure in the substrate 100；The material of the isolation structure is insulating materials, for example
Silica；The surface of the isolation structure is higher or lower than the surface of the substrate 100.
In another embodiment, the substrate is used to form fin formula field effect transistor.The substrate includes：
Substrate, the fin positioned at substrate surface and the separation layer positioned at substrate surface, the separation layer covering
The partial sidewall surface of the fin, and the separation layer surface less than fin top surface.It is described
Dummy gate structure is across the fin, and the dummy gate structure is located at partial sidewall and the top of the fin
Portion surface.
The substrate and fin are formed by etched plane semiconductor base；Or, the fin is by choosing
Selecting property epitaxial deposition process is formed at substrate surface.The material of the separation layer be silica, silicon nitride,
Silicon oxynitride, low k dielectric materials (dielectric coefficient be more than or equal to 2.5, less than 3.9) or ultralow k be situated between
(dielectric coefficient is less than 2.5 to material, less than 3.9).
In the present embodiment, the semiconductor structure for being formed is used to constitute high-k/metal gate (High k Metal
Gate, abbreviation HKMG) transistor, and the high-k/metal gate transistor uses rear grid (Gate Last)
Technique is formed.Therefore, the surface of the substrate 100 is firstly the need of formation dummy gate structure 110, the pseudo- grid
Pole structure 110 is used to be taken up space position for the high-k dielectric layer that is subsequently formed and grid layer.
The material of the dummy gate layer 111 is polysilicon.The side wall 112 is used to define what is be subsequently formed
The distance between source region and drain region and dummy gate layer 111；The material of the side wall 112 is silica, nitrogen
One or more combination in SiClx, silicon oxynitride.
In the present embodiment, the dummy gate structure 110 can also include the puppet positioned at the surface of substrate 100
Gate dielectric layer；The dummy gate layer 111 is located at the pseudo- gate dielectric layer surface.The pseudo- gate dielectric layer
Material is silica；The grid oxide layer is used for during follow-up removal dummy gate layer 111, protection lining
The surface of bottom 100.
Fig. 2 is refer to, source region and drain region are formed in the substrate 100 of the both sides of the dummy gate structure 110
113；After the source region and drain region 113 is formed, dielectric layer 120 is formed on the surface of the substrate 100,
The dielectric layer 120 exposes the top surface of the dummy gate structure 110.
In the present embodiment, the forming step in the source region and drain region 113 includes：In the dummy grid knot
Stressor layers are formed in the substrate 100 of the both sides of structure 110；Doped p-type ion or N-type in the stressor layers
Ion, forms source region and drain region 113.
When the transistor for being formed is PMOS transistor, the stress layer material is SiGe, and described
Stressor layers side wall is in " Σ " shape with the surface of substrate 100, and stressor layers side wall has drift angle, and described
Drift angle extends to the bottom of dummy gate structure 110.When the transistor for being formed is nmos pass transistor, institute
Stress layer material is stated for SiC, and the stressor layers bottom of the first area 201 is less than the table of the substrate 100
Face.
The technique of doped p-type ion or N-type ion is doping process in situ, ion implanting in stressor layers
One or two combinations in technique.
In another embodiment, the source region and drain region are formed at dummy gate structure by ion implantation technology
In the substrate 100 of 110 both sides.
The forming step of the dielectric layer 120 includes：In the substrate 100 and the table of dummy gate structure 110
Face forms deielectric-coating；The deielectric-coating is planarized, until exposing the dummy gate structure 110
Top surface, form the dielectric layer 120.
The material of the dielectric layer 120 be silica, silicon nitride, silicon oxynitride, low k dielectric materials or
Ultra-low k dielectric material.The formation process of the deielectric-coating is chemical vapor deposition method, physical vapor is sunk
Product technique or atom layer deposition process.In the present embodiment, the formation process of the deielectric-coating is fluidisation
Learn vapour deposition (Flowable Chemical Vapor Deposition, abbreviation FCVD) technique.It is described
Flatening process is CMP process.
Fig. 3 is refer to, the dummy gate layer 111 (as shown in Figure 2) is removed, in the dielectric layer 120
It is interior to form the opening 121 for exposing the surface of substrate 100.
The opening 121 is used to form high-k dielectric layer and grid layer.Remove the dummy gate layer 111
Technique is dry etch process or wet-etching technology；The dry etch process is isotropic dry method
One or two combinations in etching technics, anisotropic dry etch process are carried out.
In the present embodiment, also there is pseudo- gate dielectric layer between the dummy gate layer 111 and substrate 100,
After the dummy gate layer 111 is removed, also including removing the pseudo- gate dielectric layer and exposing opening 121
The surface of substrate 100 of bottom.
In the present embodiment, the material of the dummy gate layer 111 is polysilicon, removes the dummy gate layer
111 technique is wet-etching technology；The etching liquid of the wet-etching technology includes hydrofluoric acid and hydrogen peroxide
Mixed solution or the mixed solution including sulfuric acid and hydrogen peroxide.In another embodiment, institute is removed
The technique of dummy gate layer 111 is stated for dry etch process, the etching liquid of the dry etching includes Cl2、HBr
In one or two mixing.
In the present embodiment, the material of the pseudo- gate dielectric layer is silica, removes the pseudo- gate dielectric layer
Technique be wet-etching technology, the etching liquid of the wet-etching technology is hydrofluoric acid.
Fig. 4 is refer to, the surface of substrate 100 exposed in the opening 121 forms boundary layer 130.
The boundary layer 130 is for strengthening the combination between the high-k dielectric layer and substrate 100 that are subsequently formed
Intensity, it is to avoid produce leakage current because there is lattice mismatch between the high-k dielectric layer and substrate 100.
In the present embodiment, the material of the boundary layer 130 is silica；The shape of the boundary layer 130
It is oxidation technology into technique；The oxidation technology includes thermal oxidation technology or wet process oxidation technology.
In another embodiment, the substrate includes：Substrate, the fin positioned at substrate surface, Yi Jiwei
In the separation layer of substrate surface, and described opening exposes the side wall and top surface of part fin, then institute
State boundary layer and be located at the fin side wall and top surface for being open and exposing.
Fig. 5 is refer to, the first annealing process is carried out.
In the present embodiment, first annealing process formed boundary layer 130 after, formed it is follow-up
Carried out before high-k dielectric layer.First annealing process can be to optimization of being adulterated in the boundary layer 130
Ion；After high-k dielectric layer is subsequently formed, by the driving of the second annealing process, can make described
Optimization ion can spread in the high-k dielectric layer.The optimization ion diffuses into the high K medium
After layer, the defect that can be filled up in the high-k dielectric layer, such as electron trap or Lacking oxygen etc.；From
And the factor for influenceing polarized atom relaxation is eliminated, thus reduce relaxation electric current, the k high that raising is formed
The performance and stability of metal gate transistor.
The optimization ion includes one or more in Nitrogen ion, hydrogen ion and fluorine ion.The nitrogen from
Son, hydrogen ion and fluorine ion are used not only for filling up the defect in follow-up high-k dielectric layer, are subtracted with this
Relaxation electric current in few high-k dielectric layer, additionally it is possible to improve the dielectric coefficient of the high-k dielectric layer, enter one
Step improves the performance of formed high-k/metal gate transistor.
In the present embodiment, the gas of first annealing process includes NH2F；First annealing process
Parameter include：Annealing temperature is 850 DEG C~1050 DEG C, and air pressure is 1Torr~1ATM.Wherein, it is described
NH2F gases include simultaneously Nitrogen ion, hydrogen ion and fluorine ion, can in the boundary layer 130 simultaneously
Doping Nitrogen ion, hydrogen ion and fluorine ion.
First annealing process except in the boundary layer 130 doping Nitrogen ion, hydrogen ion and fluorine from
Outside son, additionally it is possible to for activating the p-type ion in the source region and drain region 113 or N-type ion.
In another embodiment, the gas of first annealing process also includes NH2F and H2Gaseous mixture
Body；It is that the parameter of the first annealing process includes：Annealing temperature is 850 DEG C~1050 DEG C, and air pressure is 1Torr~1
ATM, the NH2F and H2Volume ratio be 1:100~100:1.
Fig. 6 is refer to, height is formed in the sidewall surfaces of the opening 121 and the surface of boundary layer 130 of bottom
K dielectric layers 131.
In the present embodiment, the high-k dielectric layer 131 is used to be formed grid Jie of high-k/metal gate transistor
Matter layer.
The formation process of the high-k dielectric layer 131 is chemical vapor deposition method, physical vapour deposition (PVD) work
Skill or atom layer deposition process.In the present embodiment, the formation process of the high-k dielectric layer 131 is original
Sublayer depositing operation, the high-k dielectric layer 131 formed using the atom layer deposition process has good
Gradient coating performance, can be tightly covered on the side wall and lower surface of opening 121, advantageously reduce institute
Leakage current in the transistor of formation.
The material of the high-k dielectric layer 131 is Hf based dielectric materials；In the present embodiment, the k high
The material of dielectric layer 131 is HfO2.Leakage current in the Hf based dielectric materials is relatively low, therefore, with institute
When stating Hf based dielectric materials as gate dielectric layer, be conducive to the performance of the formed transistor of raising.However,
The relaxation electric current of the Hf based dielectric materials is higher, therefore, it is situated between as grid using the Hf based dielectric materials
Matter layer is for improving the limited in one's ability of transistor performance.
In the present embodiment, Nitrogen ion, hydrogen ion or the fluorine ion energy for being adulterated in the boundary layer 130
It is enough to be spread in the high-k dielectric layer 131, and the defect that can be filled up in the high-k dielectric layer 131,
Such as electron trap or Lacking oxygen, so as to eliminate hinder polarized atom relaxation in the high-k dielectric layer 131
Defect, reduce the relaxation time, and relaxation electric current is reduced with this.Therefore, with the Hf based dielectric materials
During as gate dielectric layer, i.e., can reduce leakage current, relaxation electric current can be reduced again so that formed
Transistor performance is improved.
Fig. 7 is refer to, after high-k dielectric layer 131 is formed, the second annealing process is carried out.
Second annealing process is used to drive the optimization ion of doping in the boundary layer 130 to the k high
Diffusion in dielectric layer 131 so that what the optimization ion can be filled up in the high-k dielectric layer 131 lacks
Fall into, the relaxation electric current in the high-k dielectric layer 131 is suppressed with this.
In the present embodiment, the gas of second annealing process includes N2.Second annealing process is removed
Drive Optimization ion is diffused into outside high-k dielectric layer 131, additionally it is possible to further activate the source region and
P-type ion or N-type ion in drain region 113；Additionally, second annealing process can also be further
The defect in the high-k dielectric layer 131 is discharged, to reduce relaxation electric current.
On the one hand, the electron trap that the optimization ion can be filled up in the high-k dielectric layer 131, makes
The defect level for obtaining high-k dielectric layer 131 is removed from forbidden band, so as to reduce polarized atom in relaxation mistake
Journey, electronics will not be captured by electron trap, then the interference that the polarized atom is subject in relaxation process subtracts
It is small, the relaxation time can be reduced, and reduce relaxation electric current.
On the other hand, the optimization ion can eliminate Lacking oxygen in the high-k dielectric layer 131, then institute
Stating high-k dielectric layer 131 will not pull oxonium ion from the boundary layer.And in the high-k dielectric layer 131
Oxonium ion content it is higher, relaxation electric current is bigger.Therefore, in doping in the high-k dielectric layer 131
The optimization ion can reduce the reduction of relaxation electric current.Also, the optimization ion can also optimize described
Contact interface between boundary layer 130 and the high-k dielectric layer 131, is reduced at the contact interface
Defect such that it is able to reduce the leakage current of the boundary layer 130 and high-k dielectric layer 131.
In the present embodiment, the optimization ion is the one kind or many in Nitrogen ion, hydrogen ion and fluorine ion
Kind, the doping optimization ion can also improve the high-k dielectric layer in the high-k dielectric layer 131
131 dielectric coefficient (k), so as to improve leakage current reduction, the service behaviour of formed semiconductor structure
Improve.
In the present embodiment, after second annealing process, also include：Subsequently in the opening
The surface of high-k dielectric layer 131 form the grid layer of filling full gate mouthfuls 121；Using chemically mechanical polishing work
Skill is planarized to the grid layer and high-k dielectric layer 131, until exposing the dielectric layer 120
Untill surface, gate dielectric layer and grid layer are formed in the opening 121.
Wherein, the material of the grid layer is one or more in metal and metallic compound；The gold
Category includes copper, tungsten, aluminium, silver, titanium and tantalum；The metallic compound includes titanium nitride and tantalum nitride；Institute
The formation process for stating grid layer is chemical vapor deposition method, physical gas-phase deposition, ald
One or more in technique, electroplating technology and chemical plating process.
In the present embodiment, the semiconductor structure for being formed is high-k/metal gate transistor, and the k high is situated between
Matter layer 131 as the transistor for being formed gate dielectric layer, and leakage current and relaxation in the transistor for being formed
Henan electric current reduces, and, positive bias latitude unstability (PBTI) or back bias voltage temperature of the transistor
Degree unstability (NBTI) is improved.Therefore, the transistor performance for being formed improves, reliability is carried
It is high.
In other embodiments, the semiconductor structure for being formed can also be used to form random access memory
(RAM), capacitor or flash memories；The random access memory can be dynamic RAM
(DRAM)；The high-k dielectric layer can as random access memory or the gate dielectric layer of flash memories,
Or as capacitor electrode between dielectric layer.Due to being adulterated in the high-k dielectric layer by optimization ion,
So that the relaxation electric current in the high-k dielectric layer reduces, thus, it is also possible to make formed random storage
The performance improvement of device, capacitor or flash memories.
To sum up, in the present embodiment, first annealing process is after boundary layer is formed, formation k high is situated between
Carried out before matter layer.The defect that the optimization ion can be filled up in the high-k dielectric layer, and it is described scarce
Fall into and bigger relaxation electric current is easily produced in relaxation process.On the one hand, lacking in the high-k dielectric layer
Fall into constituted electron trap can optimised ion filled up such that it is able to make scarce in high-k dielectric layer
Fall into can pole removed from forbidden band so that electronics is difficult by electron trap when being migrated in the high-k dielectric layer
Capture such that it is able to reduce the produced relaxation electric current in relaxation process of the high-k dielectric layer.Separately
On the one hand, the Lacking oxygen in the high-k dielectric layer can be filled up by the optimization ion, so as to avoid
Oxonium ion in boundary layer is migrated because of the attraction by Lacking oxygen in the high-k dielectric layer；The k high
Polarized atom in dielectric layer is not easily susceptible to the interference of oxonium ion in relaxation process, can effectively reduce
Relaxation electric current in high-k dielectric layer.And, the optimization ion will not reduce the dielectric of high-k dielectric layer
Constant.Therefore, the semiconductor structure performance improvement for being formed, the crystal formed by the semiconductor structure
The positive bias temperature of pipe is unstable and negative temperature bias are unstable is inhibited.
Fig. 8 to Figure 10 is that the cross-section structure of the forming process of the semiconductor structure of another embodiment of the present invention shows
It is intended to.
On the basis of Fig. 4, please continue to refer to Fig. 8, in the table of substrate 100 that the opening 121 exposes
Face forms boundary layer 230.
The material of the boundary layer 230 is silica；The formation process of the boundary layer 230 is oxidation work
Skill；The oxidation technology includes thermal oxidation technology or wet process oxidation technology.In the present embodiment, using hot oxygen
Chemical industry skill forms the boundary layer 230.
In another embodiment, the substrate includes：Substrate, the fin positioned at substrate surface, Yi Jiwei
In the separation layer of substrate surface, and described opening exposes the side wall and top surface of part fin, then institute
State boundary layer and be located at the fin side wall and top surface for being open and exposing.
Fig. 9 is refer to, height is formed in the sidewall surfaces of the opening 121 and the surface of boundary layer 230 of bottom
K dielectric layers 231.
In the present embodiment, the high-k dielectric layer 231 is used to be formed grid Jie of high-k/metal gate transistor
Matter layer.
The formation process of the high-k dielectric layer 231 is chemical vapor deposition method, physical vapour deposition (PVD) work
Skill or atom layer deposition process.In the present embodiment, the formation process of the high-k dielectric layer 231 is original
Sublayer depositing operation.
The material of the high-k dielectric layer 231 is Hf based dielectric materials；In the present embodiment, the k high
The material of dielectric layer 231 is HfO2.Leakage current in the Hf based dielectric materials is relatively low, therefore, with institute
When stating Hf based dielectric materials as gate dielectric layer, be conducive to the performance of the formed transistor of raising.
However, the relaxation electric current of the Hf based dielectric materials is higher, therefore, with the Hf bases medium material
Expect as gate dielectric layer for improving the limited in one's ability of transistor performance.In order to reduce high-k dielectric layer 231
Interior relaxation electric current, subsequently needs excellent in the interior doping of the high-k dielectric layer 231 by the first annealing process
Change ion, for filling up the defect in the high-k dielectric layer 231, relaxation electric current is reduced with this.
In the present embodiment, after the high-k dielectric layer 231 is formed, the first lehr attendant is directly carried out
Skill.
In one embodiment, after the high-k dielectric layer is formed, the first follow-up annealing process is carried out
Before, also including carrying out the second annealing process.The gas of second annealing process includes N2, described
Two annealing process are used to activate the p-type ion or N-type ion in source region and drain region, additionally it is possible to reduce described
Defect in high-k dielectric layer, reduces leakage current and relaxation electric current.
Figure 10 is refer to, the first annealing process is carried out, first annealing process is used to be situated between in the k high
Doping optimization ion in matter layer 231, the optimization ion is used to fill up in the high-k dielectric layer 231
Defect.
The optimization ion includes one or more in Nitrogen ion, hydrogen ion and fluorine ion.The nitrogen from
Son, hydrogen ion and fluorine ion are used not only for the defect filled up in the high-k dielectric layer 231, with this
Reduce the relaxation electric current in high-k dielectric layer 231, additionally it is possible to improve the dielectric of the high-k dielectric layer 231
Coefficient, further increases the performance of formed high-k/metal gate transistor.
In the present embodiment, the gas of first annealing process includes NH2F；First annealing process
Parameter include：Annealing temperature is 850 DEG C~1050 DEG C, and air pressure is 1Torr~1ATM.Wherein, it is described
NH2F gases include Nitrogen ion, hydrogen ion and fluorine ion simultaneously, can be in the high-k dielectric layer 231
Adulterate Nitrogen ion, hydrogen ion and fluorine ion simultaneously.
First annealing process except in the high-k dielectric layer 231 doping Nitrogen ion, hydrogen ion and
Outside fluorine ion, additionally it is possible to for activating the p-type ion in the source region and drain region 113 or N-type ion.
On the one hand, the electron trap that the optimization ion can be filled up in the high-k dielectric layer 231, makes
The defect level for obtaining high-k dielectric layer 231 is removed from forbidden band, so as to reduce polarized atom in relaxation mistake
Journey, electronics will not be captured by electron trap, then the interference that the polarized atom is subject in relaxation process subtracts
It is small, the relaxation time can be reduced, and reduce relaxation electric current.
On the other hand, the optimization ion can eliminate Lacking oxygen in the high-k dielectric layer 231, then institute
Stating high-k dielectric layer 231 will not pull oxonium ion from the boundary layer 230.And the high-k dielectric layer 231
Interior oxonium ion content is higher, and relaxation electric current is bigger.Therefore, the doping in the high-k dielectric layer 231
Described in optimization ion can reduce relaxation electric current reduction.
In another embodiment, the gas of first annealing process also includes NH2F and H2Gaseous mixture
Body；It is that the parameter of the first annealing process includes：Annealing temperature is 850 DEG C~1050 DEG C, and air pressure is 1Torr~1
ATM, the NH2F and H2Volume ratio be 1:100~100:1.
In the present embodiment, after first annealing process, also include：Subsequently in the opening 121
The interior surface of high-k dielectric layer 231 forms the grid layer of filling full gate mouthful 121；Using chemically mechanical polishing
Technique is planarized to the grid layer and high-k dielectric layer 231, until exposing the dielectric layer 120
Untill surface, gate dielectric layer and grid layer are formed in the opening 121.Wherein, the grid layer
Material is one or more in metal and metallic compound；The metal include copper, tungsten, aluminium, silver,
Titanium and tantalum.
In other embodiments, the semiconductor structure for being formed can also be used to form random access memory
(RAM), capacitor or flash memories；The high-k dielectric layer can be used as random access memory or flash memory
The gate dielectric layer of memory, or as capacitor electrode between dielectric layer；The random access memory can
It is dynamic RAM (DRAM).
To sum up, in the present embodiment, after interface layer surfaces form high-k dielectric layer, then carry out first and move back
Ignition technique, for the optimization ion that adulterated in the high-k dielectric layer.The optimization ion is used to fill up institute
The defect in high-k dielectric layer is stated, to reduce the relaxation electric current in the high-k dielectric layer.Due to described
One annealing process is directly doped to the high-k dielectric layer so that the optimization ion can be filled out fully
The defect in the high-k dielectric layer is mended, can more effectively reduce relaxation electric current.
Figure 11 to Figure 12 is the cross-section structure of the forming process of the semiconductor structure of further embodiment of this invention
Schematic diagram.
Refer to Figure 11, there is provided substrate 300；Boundary layer 301 is formed on the surface of the substrate 300；Institute
State the surface of boundary layer 301 and form high-k dielectric layer 302.
In the present embodiment, the substrate 300 is planar substrates.The substrate 300 include silicon substrate,
Silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator (SOI) substrate, germanium on insulator (GOI) substrate,
Glass substrate or III-V substrate (such as silicon nitride or GaAs etc.).In the present embodiment, institute
Substrate 300 is stated for silicon substrate.There is isolation structure in the substrate 300；The material of the isolation structure
It is insulating materials, such as silica；The surface of the isolation structure is higher or lower than the table of the substrate 300
Face.
In another embodiment, the substrate is used to form fin formula field effect transistor.The substrate includes：
Substrate, the fin positioned at substrate surface and the separation layer positioned at substrate surface, the separation layer covering
The partial sidewall surface of the fin, and the separation layer surface less than fin top surface.It is described
Dummy gate structure is across the fin, and the dummy gate structure is located at partial sidewall and the top of the fin
Portion surface.
The substrate and fin are formed by etched plane semiconductor base；Or, the fin is by choosing
Selecting property epitaxial deposition process is formed at substrate surface.The material of the separation layer be silica, silicon nitride,
Silicon oxynitride, low k dielectric materials (dielectric coefficient be more than or equal to 2.5, less than 3.9) or ultralow k be situated between
(dielectric coefficient is less than 2.5 to material, less than 3.9).
In the present embodiment, the semiconductor structure for being formed is used to constitute high-k/metal gate (High k Metal
Gate, abbreviation HKMG) transistor, and the high-k/metal gate transistor uses rear grid (Gate Last)
Technique is formed.Therefore, the surface of the substrate 300 is firstly the need of formation dummy gate layer, the dummy gate layer
For being taken up space position for the grid layer of metal material being subsequently formed.
The present embodiment high-k/metal gate transistor formation process for k high in preceding technique (high-k
First), before the dummy gate layer is formed, form boundary layer 301 on the surface of substrate 300 and k high is situated between
Matter layer 302, and the high-k dielectric layer 302 be used for as the transistor for being formed gate dielectric layer, subsequently
After removal dummy gate layer, grid layer is formed on the surface of the high-k dielectric layer 302.
In other embodiments, the semiconductor structure can also be used to be formed random access memory (RAM),
Capacitor or flash memories；The random access memory can be dynamic RAM (DRAM)；Institute
Stating high-k dielectric layer can be as random access memory or the gate dielectric layer of flash memories, or as electric capacity
Dielectric layer between the electrode of device.
The combination that the boundary layer 301 is used to strengthen between the high-k dielectric layer 302 and substrate 300 is strong
Degree, it is to avoid produce leakage current because there is lattice mismatch between the high-k dielectric layer 302 and substrate 300.
In the present embodiment, the material of the boundary layer 301 is silica；The shape of the boundary layer 301
It is oxidation technology into technique；The oxidation technology includes thermal oxidation technology or wet process oxidation technology.
In another embodiment, the substrate includes：Substrate, the fin positioned at substrate surface, Yi Jiwei
In the separation layer of substrate surface, and described opening exposes the side wall and top surface of part fin, then institute
State boundary layer and be located at the fin side wall and top surface for being open and exposing.
In the present embodiment, the high-k dielectric layer 302 is used to be formed grid Jie of high-k/metal gate transistor
Matter layer.
The formation process of the high-k dielectric layer 302 is chemical vapor deposition method, physical vapour deposition (PVD) work
Skill or atom layer deposition process.In the present embodiment, the formation process of the high-k dielectric layer 302 is original
Sublayer depositing operation.
The material of the high-k dielectric layer 302 is Hf based dielectric materials；In the present embodiment, the k high
The material of dielectric layer 302 is HfO2.Leakage current in the Hf based dielectric materials is relatively low, therefore, with institute
When stating Hf based dielectric materials as gate dielectric layer, be conducive to the performance of the formed transistor of raising.However,
The relaxation electric current of the Hf based dielectric materials is higher, therefore, the follow-up institute in the high-k dielectric layer 302
Doping optimization ion, for filling up the defect in the high-k dielectric layer 302, relaxation electric current is reduced with this.
In the present embodiment, after the high-k dielectric layer 302 is formed, the first lehr attendant is directly carried out
Skill.
In another embodiment, after the high-k dielectric layer is formed, the first follow-up lehr attendant is carried out
Before skill, also including carrying out the second annealing process.The gas of second annealing process includes N2, it is described
Second annealing process is used to activate the p-type ion or N-type ion in source region and drain region, additionally it is possible to reduce institute
The defect in high-k dielectric layer is stated, leakage current and relaxation electric current is reduced.
Figure 12 is refer to, the first annealing process is carried out, first annealing process is used to be situated between in the k high
Doping optimization ion in matter layer 302.The optimization ion is used to fill up in the high-k dielectric layer 302
Defect.
The optimization ion includes one or more in Nitrogen ion, hydrogen ion and fluorine ion.The nitrogen from
Son, hydrogen ion and fluorine ion are used not only for the defect filled up in the high-k dielectric layer 302, with this
Reduce the relaxation electric current in high-k dielectric layer 302, additionally it is possible to improve the dielectric of the high-k dielectric layer 302
Coefficient, further increases the performance of formed high-k/metal gate transistor.
In the present embodiment, the gas of first annealing process includes NH2F；First annealing process
Parameter include：Annealing temperature is 850 DEG C~1050 DEG C, and air pressure is 1Torr~1ATM.Wherein, it is described
NH2F gases include Nitrogen ion, hydrogen ion and fluorine ion simultaneously, can be in the high-k dielectric layer 302
Adulterate Nitrogen ion, hydrogen ion and fluorine ion simultaneously.
First annealing process except in the high-k dielectric layer 302 doping Nitrogen ion, hydrogen ion and
Outside fluorine ion, additionally it is possible to for activating the p-type ion in the source region and drain region 113 or N-type ion.
On the one hand, the electron trap that the optimization ion can be filled up in the high-k dielectric layer 302, makes
The defect level for obtaining high-k dielectric layer 302 is removed from forbidden band, so as to reduce polarized atom in relaxation mistake
Journey, electronics will not be captured by electron trap, then the interference that the polarized atom is subject in relaxation process subtracts
It is small, the relaxation time can be reduced, and reduce relaxation electric current.
On the other hand, the optimization ion can eliminate Lacking oxygen in the high-k dielectric layer 302, then institute
Stating high-k dielectric layer 302 will not pull oxonium ion from the boundary layer 301.And the high-k dielectric layer 302
Interior oxonium ion content is higher, and relaxation electric current is bigger.Therefore, the doping in the high-k dielectric layer 302
Described in optimization ion can reduce relaxation electric current reduction.
In another embodiment, the gas of first annealing process also includes NH2F and H2Gaseous mixture
Body；It is that the parameter of the first annealing process includes：Annealing temperature is 850 DEG C~1050 DEG C, and air pressure is 1Torr~1
ATM, the NH2F and H2Volume ratio be 1:100~100:1.
In the present embodiment, after first annealing process, also include：In the high-k dielectric layer
302 surfaces form dummy grid film；The dummy grid film, high-k dielectric layer 302 and boundary layer 301 are etched,
And the surface of section substrate 300 is exposed, form dummy gate layer on the surface of high-k dielectric layer 302；Described
The sidewall surfaces of dummy gate layer, high-k dielectric layer 302 and boundary layer 301 form side wall；In the pseudo- grid
Source region and drain region are formed in the substrate 300 of pole layer, high-k dielectric layer 302, boundary layer 301 and side wall both sides；
After the source region and drain region is formed, dielectric layer, the dielectric layer are formed on the surface of the substrate 300
Expose the top surface of the dummy gate structure；The dummy gate layer is removed, the shape in the dielectric layer
Into the opening for exposing high-k dielectric layer 302；The surface of high-k dielectric layer 302 in the opening is formed
The grid layer of filling full gate mouthful.Wherein, the material of the grid layer is in metal and metallic compound
Plant or various；The metal includes copper, tungsten, aluminium, silver, titanium and tantalum.
In other embodiments, first annealing process can also be after boundary layer 301 is formed, shape
Carried out before into the high-k dielectric layer 302；Carry out first annealing process and form the k high
After dielectric layer 302, carry out the second annealing process, drive the optimization of doping in the boundary layer 301 from
Son spreads in the high-k dielectric layer 302, to fill up the defect in the high-k dielectric layer 302, subtracts
Small relaxation electric current.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, can make various changes or modifications, therefore guarantor of the invention
Shield scope should be defined by claim limited range.
Claims (18)
1. a kind of forming method of semiconductor structure, it is characterised in that including：
Substrate is provided；
Boundary layer is formed in the substrate surface；
High-k dielectric layer is formed in the interface layer surfaces；
The first annealing process is carried out, first annealing process is excellent for being adulterated in the high-k dielectric layer
Change ion, the optimization ion is used for the defect filled up in the high-k dielectric layer.
2. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the optimization ion
Including one or more in Nitrogen ion, hydrogen ion and fluorine ion.
3. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the high K medium
The material of layer is Hf based dielectric materials.
4. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the Hf bases medium
Material is HfO2。
5. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the boundary layer
Material is silica；The formation process of the boundary layer is thermal oxidation technology.
6. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that forming the boundary
After surface layer, before forming the high-k dielectric layer, first annealing process is carried out.
7. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that forming the height
After k dielectric layers, first annealing process is carried out.
8. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that first annealing
The gas of technique includes NH2F。
9. the forming method of semiconductor structure as claimed in claim 8, it is characterised in that first annealing
The parameter of technique includes：Annealing temperature is 850 DEG C~1050 DEG C, and air pressure is 1Torr~1ATM.
10. the forming method of semiconductor structure as claimed in claim 8, it is characterised in that first annealing
The gas of technique also includes H2。
The forming method of 11. semiconductor structures as claimed in claim 10, it is characterised in that first annealing
NH described in technique2F and H2Volume ratio be 1:100~100:1.
The forming method of 12. semiconductor structures as claimed in claim 1, it is characterised in that also include：In shape
Into after high-k dielectric layer, the second annealing process is carried out；The gas of second annealing process includes N2。
The forming method of 13. semiconductor structures as claimed in claim 1, it is characterised in that also include：In shape
Into before the boundary layer, dummy gate structure, the dummy gate structure bag are formed in the substrate surface
Include dummy gate layer and the side wall positioned at dummy gate layer sidewall surfaces；In the dummy gate structure both sides
Substrate in formed source region and drain region；After the source region and drain region is formed, in the substrate surface
Dielectric layer is formed, the dielectric layer exposes the top surface of the dummy gate structure；Remove the puppet
Grid layer, forms the opening for exposing substrate surface in the dielectric layer；Exposed in the opening
Substrate surface formed boundary layer；Formed in the sidewall surfaces of the opening and the interface layer surfaces of bottom
High-k dielectric layer.
The forming method of 14. semiconductor structures as claimed in claim 1, it is characterised in that also include：Institute
State high-k dielectric layer surface and form dummy grid film；Etch the dummy grid film, high-k dielectric layer and interface
Layer, and section substrate surface is exposed, form dummy gate layer on high-k dielectric layer surface；In the puppet
The sidewall surfaces of grid layer, high-k dielectric layer and boundary layer form side wall；In the dummy gate layer, height
Source region and drain region are formed in the substrate of k dielectric layers, boundary layer and side wall both sides；Forming the source region
After drain region, dielectric layer is formed in the substrate surface, the dielectric layer exposes the dummy grid
The top surface of structure；The dummy gate layer is removed, is formed in the dielectric layer and is exposed k Jie high
The opening of matter layer.
The forming method of 15. semiconductor structure as described in claim 13 or 14, it is characterised in that described
High-k dielectric layer surface in opening forms the grid layer of filling full gate mouthful.
The forming method of 16. semiconductor structures as claimed in claim 15, it is characterised in that the grid layer
Material is one or more in metal and metallic compound；The metal include copper, tungsten, aluminium, silver,
Titanium and tantalum；The metallic compound includes titanium nitride and tantalum nitride.
The forming method of 17. semiconductor structures as claimed in claim 1, it is characterised in that the substrate includes：
Substrate, the fin positioned at substrate surface and the separation layer positioned at substrate surface, the separation layer cover
Cover the partial sidewall surface of the fin, and the separation layer top surface of the surface less than fin.
The forming method of 18. semiconductor structures as claimed in claim 17, it is characterised in that the boundary layer position
In the side wall and top surface of the fin.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109037334A (en) * | 2017-06-12 | 2018-12-18 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN110690109A (en) * | 2018-07-05 | 2020-01-14 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN110957358A (en) * | 2018-09-26 | 2020-04-03 | 台湾积体电路制造股份有限公司 | Transistor structure and manufacturing method thereof |
| CN111106065A (en) * | 2018-10-26 | 2020-05-05 | 台湾积体电路制造股份有限公司 | Method for manufacturing gate structure and integrated circuit with interface layer |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1604278A (en) * | 2003-10-01 | 2005-04-06 | 台湾积体电路制造股份有限公司 | A method for treating a gate structure |
| CN103632976A (en) * | 2012-08-29 | 2014-03-12 | 中芯国际集成电路制造(上海)有限公司 | Formation method for transistor |
| CN103681276A (en) * | 2012-09-18 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Forming method of metal gate, forming method of MOS transistor and forming method of CMOS structure |
-
2015
- 2015-08-31 CN CN201510548258.XA patent/CN106711034B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1604278A (en) * | 2003-10-01 | 2005-04-06 | 台湾积体电路制造股份有限公司 | A method for treating a gate structure |
| CN103632976A (en) * | 2012-08-29 | 2014-03-12 | 中芯国际集成电路制造(上海)有限公司 | Formation method for transistor |
| CN103681276A (en) * | 2012-09-18 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Forming method of metal gate, forming method of MOS transistor and forming method of CMOS structure |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109037334A (en) * | 2017-06-12 | 2018-12-18 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN110690109A (en) * | 2018-07-05 | 2020-01-14 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN110957358A (en) * | 2018-09-26 | 2020-04-03 | 台湾积体电路制造股份有限公司 | Transistor structure and manufacturing method thereof |
| US11088029B2 (en) | 2018-09-26 | 2021-08-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Gate stack treatment |
| TWI744690B (en) * | 2018-09-26 | 2021-11-01 | 台灣積體電路製造股份有限公司 | Transistor structure and method for forming semiconductor structure |
| US11670553B2 (en) | 2018-09-26 | 2023-06-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Gate stack treatment |
| CN110957358B (en) * | 2018-09-26 | 2024-02-06 | 台湾积体电路制造股份有限公司 | Transistor structure and method for manufacturing the same |
| CN111106065A (en) * | 2018-10-26 | 2020-05-05 | 台湾积体电路制造股份有限公司 | Method for manufacturing gate structure and integrated circuit with interface layer |
| CN111106065B (en) * | 2018-10-26 | 2022-06-28 | 台湾积体电路制造股份有限公司 | Method for manufacturing gate structure and integrated circuit with interface layer |
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