CN106711019B - The method for preparing metal-semiconductor alloy using controlled imperfections graphene insert layer - Google Patents
The method for preparing metal-semiconductor alloy using controlled imperfections graphene insert layer Download PDFInfo
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Abstract
The present invention provides a kind of method for preparing metal-semiconductor alloy using controlled imperfections graphene insert layer, comprising the following steps: 1) provides semiconductor substrate；2) graphene is formed in semiconductor substrate surface；3) ion implanting is carried out to graphene, to obtain the controllable defect graphene of density；4) metal layer is formed in defect graphene surface；5) structure that step 4) obtains is made annealing treatment, forms metal-semiconductor alloy layer.By forming graphene insert layer between semiconductor substrate and metal layer, the contact performance at the interface of semiconductor substrate and metal-semiconductor alloy layer can effectively improve, metal-semiconductor alloy layer better quality that extension obtains, performance are more stable；Graphene insert layer electron mobility with higher can be effectively reduced the metal-semiconductor alloy layer resistance of epitaxial growth and the contact resistance of semiconductor substrate and metal-semiconductor alloy layer, to improve its electric property.
Description
Technical field
The present invention relates to field of material preparation, prepare gold using controlled imperfections graphene insert layer more particularly to a kind of
Category-semiconducting alloy method.
Background technique
In the prior art, when semiconductor substrate surface directly grows metal film layer, the metal film layer of growth with
The contact performance at the interface of semiconductor substrate is poor, and the poor quality of the metal film layer grown, stability are poor.Such as figure
Shown in 1, Fig. 1 is the TEM for making annealing treatment the sample obtained after 30s in 400 DEG C after Ge substrate surface directly forms Ni metal layer
Figure, as shown in Figure 1, either the equal convex-concave in interface of the surface of NiGe film layer or NiGe film layer and the Ge substrate is not
It is flat, it is in uneven thickness.
To solve the above-mentioned problems, existing improved method is present semiconductor substrate surface one layer of insert layer of formation, and
Metal film layer is formed in insertion layer surface again afterwards, the material of existing insert layer is generally Al, Ti or Pd.However, traditional
Insert layer can not substrate solve the above problems, and traditional insert layer is mostly metal layer, can be to the metallic film of subsequent growth
The performance of layer causes certain adverse effect.
Summary of the invention
In view of the foregoing deficiencies of prior art, controlled imperfections graphene is utilized the purpose of the present invention is to provide a kind of
The method that insert layer prepares metal-semiconductor alloy grows metal foil in semiconductor substrate surface in the prior art for solving
The poor quality of metal film layer existing for film layer, the poor problem of stability.
His related purpose to achieve the above object, the present invention provides a kind of to be prepared using controlled imperfections graphene insert layer
The method of metal-semiconductor alloy, the described method comprises the following steps:
1) semiconductor substrate is provided；
2) graphene is formed in the semiconductor substrate surface；
3) ion implanting is carried out to the graphene, to obtain the controllable defect graphene of density；
4) metal layer is formed in the defect graphene surface；
5) structure that step 4) obtains is made annealing treatment, forms metal-semiconductor alloy layer.
One kind as the method for the invention for preparing metal-semiconductor alloy using controlled imperfections graphene insert layer is excellent
Scheme is selected, between step 1) and step 2), further includes the steps that carrying out RCA cleaning to the semiconductor substrate.
One kind as the method for the invention for preparing metal-semiconductor alloy using controlled imperfections graphene insert layer is excellent
It selects scheme, is one or more layers in the graphene that the semiconductor substrate surface is formed in step 2).
One kind as the method for the invention for preparing metal-semiconductor alloy using controlled imperfections graphene insert layer is excellent
It selects scheme, in step 2), the graphene is formed in the semiconductor substrate surface using chemical vapour deposition technique or transfer method.
One kind as the method for the invention for preparing metal-semiconductor alloy using controlled imperfections graphene insert layer is excellent
It selects scheme, in step 2), the graphene is formed in the semiconductor substrate surface using direct transfer process or PMMA transfer method.
One kind as the method for the invention for preparing metal-semiconductor alloy using controlled imperfections graphene insert layer is excellent
It selects scheme, in step 3), injection element H, B or P of ion implanting is carried out to the graphene.
One kind as the method for the invention for preparing metal-semiconductor alloy using controlled imperfections graphene insert layer is excellent
Select scheme, in step 3), the Implantation Energy that ion implanting is carried out to the graphene is 1keV~600keV, and implantation dosage is
1E14~1E17.
One kind as the method for the invention for preparing metal-semiconductor alloy using controlled imperfections graphene insert layer is excellent
Scheme is selected, in step 4), using electron beam evaporation method, magnetron sputtering method or physical vaporous deposition in the defect graphene table
Face forms the metal layer.
One kind as the method for the invention for preparing metal-semiconductor alloy using controlled imperfections graphene insert layer is excellent
Select scheme, in step 4), the material of the metal layer is Ni, Co, Ti, Pt, NiPt, NiTi or TiPt, the thickness of the metal layer
Degree is 2nm~1000nm.
One kind as the method for the invention for preparing metal-semiconductor alloy using controlled imperfections graphene insert layer is excellent
Scheme is selected, the annealing atmosphere made annealing treatment to the structure that step 4) obtains is vacuum, N2, Ar or nitrogen and hydrogen mixture, annealing
Temperature is 200 DEG C~1000 DEG C, and annealing time is 15s~100s.
As described above, the method for the invention for preparing metal-semiconductor alloy using controlled imperfections graphene insert layer, tool
Have following the utility model has the advantages that the present invention can be with by forming graphene insert layer, graphene between semiconductor substrate and metal layer
The speed that semiconductor substrate is reacted with metal layer is adjusted, so that reaction is carried out to compare slow speed, so that semiconductor substrate
It is relatively flat with the interface of metal-semiconductor alloy layer, effectively improve semiconductor substrate and metal-semiconductor alloy layer
The contact performance at interface, metal-semiconductor alloy layer better quality that extension obtains, performance are more stable；Compared to traditional
Insert layer, graphene insert layer electron mobility with higher, the metal-semiconductor that can be effectively reduced epitaxial growth close
Layer gold resistance reduces the contact resistance of semiconductor substrate and metal-semiconductor alloy layer, to improve its electric property.
Detailed description of the invention
Fig. 1 is shown as Ge substrate surface in the prior art and is directly formed after Ni metal layer after 400 DEG C of annealing 30s
The TEM of obtained sample schemes.
Fig. 2 is shown as the method for the invention that metal-semiconductor alloy is prepared using controlled imperfections graphene insert layer
Flow chart.
Fig. 3 to Fig. 7 is shown as the side of the invention that metal-semiconductor alloy is prepared using controlled imperfections graphene insert layer
The structural schematic diagram of each step in method.
Fig. 8 is shown as making annealing treatment after Ge substrate surface of the invention forms graphene insert layer, Ni metal layer in 500 DEG C
The TEM of the sample obtained after 30s schemes, wherein the element of the graphene layer ion implanting is B, implantation dosage 2E15.
Component label instructions
1 semiconductor substrate
2 graphenes
3 defect graphenes
4 metal layers
5 metal-semiconductor alloy layers
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Fig. 2 to Fig. 8 is please referred to it should be noted that diagram provided in the present embodiment only illustrates this hair in a schematic way
Bright basic conception, though only show in diagram with related component in the present invention rather than component count when according to actual implementation,
Shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its component
Being laid out kenel may also be increasingly complex.
Referring to Fig. 2, preparing metal-semiconductor alloy using controlled imperfections graphene insert layer the present invention also provides a kind of
Method, it is described using controlled imperfections graphene insert layer prepare metal-semiconductor alloy method the following steps are included:
1) semiconductor substrate is provided；
2) graphene is formed in the semiconductor substrate surface；
3) ion implanting is carried out to the graphene, to obtain the controllable defect graphene of density；
4) metal layer is formed in the defect graphene surface；
5) structure that step 4) obtains is made annealing treatment, forms metal-semiconductor alloy layer.
In step 1), S1 step and Fig. 3 in Fig. 2 are please referred to, semiconductor substrate 1 is provided.
As an example, the semiconductor substrate 1 can be existing any semiconductor substrate, and for example, the semiconductor lining
Bottom 1 can be but be not limited only to Si substrate, Ge substrate, B substrate, Te substrate, SiGe substrate, GaAs substrate.
As an example, further including the RCA (Radio that the semiconductor substrate 1 is carried out to standard after step 1)
Corporation of America) cleaning the step of, to remove the pollutant on 1 surface of semiconductor substrate.To described half
Conductor substrate 1 carries out the specific steps of the RCA cleaning of standard and method is to be not repeated herein known to those skilled in the art.
In step 2), S2 step and Fig. 4 in Fig. 2 are please referred to, forms graphene 2 on 1 surface of semiconductor substrate.
As an example, the graphene 2 is preferably intrinsic graphene.
As an example, the number of plies in the graphene 2 of 1 surface of semiconductor substrate formation can be according to actual needs
It is selected, i.e., the number of plies of the graphene 2 formed on 1 surface of semiconductor substrate can be one layer, or two
Layer, can also be multilayer.
As an example, the graphene 2 can be formed on 1 surface of semiconductor substrate using chemical vapour deposition technique,
The graphene 2 grown in advance can also be transferred to the surface of the semiconductor substrate 1 using transfer method.
Specifically, forming the specific side of the graphene 2 on 1 surface of semiconductor substrate using chemical vapour deposition technique
Method may include steps of:
A) semiconductor substrate 1 is placed in chemical vapour deposition reactor furnace；
B) under hydrogen and inert atmosphere, the semiconductor substrate 1 is heated to certain temperature, the temperature can be
But it is not limited only to 810 DEG C~910 DEG C；
C) it keeps temperature-resistant in step b), is passed through carbon source into the reacting furnace under hydrogen and inert atmosphere and carries out instead
Answer, to form the graphene 2 on 1 surface of semiconductor substrate, the carbon source can for methane, acetylene, ethylene, methanol,
Ethyl alcohol, polymethyl methacrylate, polystyrene or dimethyl silicone polymer etc.；
D) carbon source is closed after completion of the reaction, and is cooled to room temperature under hydrogen and inert atmosphere.
As an example, direct transfer process or PMMA (polymethyl methacrylate) transfer method can be used the graphene
2 are transferred to the surface of the semiconductor substrate 1.
Specifically, being to be grown in the intrinsic graphene of brass bottom surface as an example, using directly turning with the graphene 2
Shifting method includes the following steps: the specific method on the surface that the graphene 2 is transferred to the semiconductor substrate 1
A) graphene 2 grown in copper substrate is chosen；
B) copper substrate that surface growth has the graphene 2 is placed in etchant solution and is corroded 2 hours, the corrosion
Solution can be the Fe (NO of a certain concentration (for example concentration is 0.1g/ml)3)3Solution or FeCl3Solution, make the graphene 2 with
The copper substrate separation；
C) graphene 2 is picked up using the ready semiconductor substrate 1, i.e., be transferred to the graphene 2
The surface of the semiconductor substrate 1.
As an example, using Fe (NO3)3Solution or FeCl3After solution separates the graphene 2 with the copper substrate,
It can also include being placed in the graphene 2 before being picked up the graphene 2 using the ready semiconductor substrate 1
Corrode 1 hour in the HCl solution of certain molar concentration (for example molar concentration is 10%), it is residual to remove 2 surface of graphene
The step of copper stayed.
Specifically, being to be grown in the intrinsic graphene of brass bottom surface as an example, being turned using PMMA with the graphene 2
Shifting method includes the following steps: the specific method on the surface that the graphene 2 is transferred to the semiconductor substrate 1
A) graphene 2 grown in copper substrate is chosen；
B) PMMA is coated uniformly on to the surface of the graphene 2；
C) copper substrate that surface growth has the graphene 2 is placed in etchant solution and is corroded 2 hours, the corrosion
Solution can be the Fe (NO of a certain concentration (for example concentration is 0.1g/ml)3)3Solution or FeCl3Solution, make the graphene 2 with
The copper substrate separation；
D) graphene 2 is picked up using the ready semiconductor substrate 1, i.e., be transferred to the graphene 2
The surface of the semiconductor substrate 1；
E) PMMA on 2 surface of graphene is removed using annealing method or acetone cleaning.
As an example, using Fe (NO3)3Solution or FeCl3After solution separates the graphene 2 with the copper substrate,
It can also include being placed in the graphene 2 before being picked up the graphene 2 using the ready semiconductor substrate 1
Corrode 1 hour in the HCl solution of certain molar concentration (for example molar concentration is 10%), it is residual to remove 2 surface of graphene
The step of copper stayed.
In step 3), S3 step and Fig. 5 in Fig. 2 are please referred to, ion implanting is carried out to the graphene 2, to obtain
The controllable defect graphene 3 of size, density.
As an example, the structure that step 2) is obtained, which is placed in ion implantation apparatus, carries out ion implanting, in the graphene 2
Middle injected element can be but be not limited only to H, B or P
As an example, to the graphene 2 carry out ion implanting Implantation Energy can be but be not limited only to 1keV~
600keV, implantation dosage can be but be not limited only to 1E14~1E17.
In step 4), S4 step and Fig. 6 in Fig. 2 are please referred to, in the forming metal layer on surface of the defect graphene 3
4。
As an example, can be using electron beam evaporation method, magnetron sputtering method or physical vaporous deposition in the defect stone
The surface of black alkene 3 forms the metal layer 4.Using electron beam evaporation method, magnetron sputtering method or physical vaporous deposition described
The specific method that the surface of defect graphene 3 forms the metal layer 4 is to be not repeated herein known to those skilled in the art.
As an example, the material of the metal layer 4 can be any metal or alloy, it is preferable that in the present embodiment, institute
The material for stating metal layer 4 can be but be not limited only to Ni, Co, Ti, Pt, NiPt, NiTi or TiPt.
As an example, the thickness of the metal layer 4 can be set according to actual needs, it is preferable that in the present embodiment,
The metal layer 4 with a thickness of 2nm~1000nm.
In step 5), S5 step and Fig. 7 in Fig. 2 are please referred to, the structure that step 4) obtains is made annealing treatment, shape
At metal-semiconductor alloy layer 5.
As an example, the annealing atmosphere made annealing treatment to the structure that step 4) obtains can be vacuum atmosphere, N2Gas
Atmosphere, Ar atmosphere or nitrogen and hydrogen mixture atmosphere, annealing temperature are 200 DEG C~1000 DEG C, and annealing time is 15s~100s.
During annealing, the semiconductor material in the semiconductor substrate 1 can be with the gold in the metal layer 4
Belong to material to react, when the two reacts, the defect graphene 3 plays the role of one layer of barrier layer, adjustable
The speed that the semiconductor material is reacted with the metal material, so that reaction is carried out with comparing slow speed, so that
The semiconductor material reaches balance with reacting for the metal material, so that the semiconductor substrate 1 is partly led with the metal-
The interface of body alloy-layer 5 is relatively flat, effectively improves the semiconductor substrate 1 and the metal-semiconductor alloy layer 5
The contact performance at interface, so that the better quality of the metal-semiconductor alloy layer 5 of epitaxial growth, performance are more steady
It is fixed, as shown in figure 8, Fig. 8 is that Ge substrate surface of the invention is formed after graphene insert layer, Ni metal layer at 500 DEG C of annealing
The TEM figure of the sample obtained after reason 30s, wherein the element of the graphene layer ion implanting is B, implantation dosage 2E15, is incited somebody to action
Fig. 8 and Fig. 1 comparison it is found that either NiGe layers of sample of surface in Fig. 8 or NiGe layers and the interface of Ge substrate it is smooth
Sample compared with Fig. 1 is spent by significantly taking on a new look；Simultaneously as the defect graphene 3 electron transfer with higher
Rate can be effectively reduced the resistance of the metal-semiconductor alloy layer 5 of epitaxial growth, reduce the semiconductor substrate 1 with
The contact resistance of the metal-semiconductor alloy layer 5, to improve its electric property.
Please continue to refer to Fig. 8, as shown in Figure 8, in annealing process, the graphene insert layer can be completely removed, will not
Any adverse effect is caused to the performance of the metal-semiconductor alloy layer 5 of formation.
In conclusion the present invention provides and a kind of prepares metal-semiconductor alloy using controlled imperfections graphene insert layer
Method, it is described to prepare the method for metal-semiconductor alloy the following steps are included: 1) providing using controlled imperfections graphene insert layer
Semiconductor substrate；2) graphene is formed in the semiconductor substrate surface；3) ion implanting is carried out to the graphene, to obtain
The controllable defect graphene of density；4) metal layer is formed in the defect graphene surface；5) structure step 4) obtained into
Row annealing, forms metal-semiconductor alloy layer.The present invention between semiconductor substrate and metal layer by forming graphene
Insert layer, the speed that the adjustable semiconductor substrate of graphene is reacted with metal layer so that reaction with compare slow speed into
Row effectively improves semiconductor substrate and gold so that semiconductor substrate and the interface of metal-semiconductor alloy layer are relatively flat
The contact performance at category-semiconductor alloy layer interface, metal-semiconductor alloy layer better quality that extension obtains, performance are more
Stablize；Compared to traditional insert layer, it is raw can be effectively reduced extension for graphene insert layer electron mobility with higher
Long metal-semiconductor alloy layer resistance reduces the contact resistance of semiconductor substrate and metal-semiconductor alloy layer, to mention
Its high electric property.
The effect of the principle of the present invention is only illustrated in above-described embodiment, and is not intended to limit the present invention.It is any to be familiar with
The personage of this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Therefore,
Such as those of ordinary skill in the art is completed without departing from the spirit and technical ideas disclosed in the present invention
All equivalent modifications or change, should be covered by the claims of the present invention.
Claims (10)
1. a kind of method for preparing metal-semiconductor alloy using controlled imperfections graphene insert layer, which is characterized in that the side
Method the following steps are included:
1) semiconductor substrate is provided；
2) graphene is formed in the semiconductor substrate surface；
3) ion implanting is carried out to the graphene, to obtain the controllable defect graphene of density；
4) metal layer is formed in the defect graphene surface；
5) structure that step 4) obtains is made annealing treatment, formation metal-semiconductor alloy layer, it is described to lack in annealing process
Graphene is fallen into for adjusting the speed that the semiconductor substrate is reacted with the metal layer.
2. the method according to claim 1 for preparing metal-semiconductor alloy using controlled imperfections graphene insert layer,
It is characterized in that: between step 1) and step 2), further including the steps that carrying out RCA cleaning to the semiconductor substrate.
3. the method according to claim 1 for preparing metal-semiconductor alloy using controlled imperfections graphene insert layer,
It is characterized in that: being one or more layers in the graphene that the semiconductor substrate surface is formed in step 2).
4. the method according to claim 1 for preparing metal-semiconductor alloy using controlled imperfections graphene insert layer,
It is characterized in that: in step 2), the graphite being formed in the semiconductor substrate surface using chemical vapour deposition technique or transfer method
Alkene.
5. the method according to claim 4 for preparing metal-semiconductor alloy using controlled imperfections graphene insert layer,
It is characterized in that: in step 2), the graphite being formed in the semiconductor substrate surface using direct transfer process or PMMA transfer method
Alkene.
6. the method according to claim 1 for preparing metal-semiconductor alloy using controlled imperfections graphene insert layer,
It is characterized in that: in step 3), injection element H, B or P of ion implanting is carried out to the graphene.
7. the method according to claim 1 for preparing metal-semiconductor alloy using controlled imperfections graphene insert layer,
Be characterized in that: in step 3), the Implantation Energy that ion implanting is carried out to the graphene is 1keV~600keV, and implantation dosage is
1E14~1E17.
8. the method according to claim 1 for preparing metal-semiconductor alloy using controlled imperfections graphene insert layer,
It is characterized in that: in step 4), using electron beam evaporation method, magnetron sputtering method or physical vaporous deposition in the defect graphene
Surface forms the metal layer.
9. the method according to claim 1 for preparing metal-semiconductor alloy using controlled imperfections graphene insert layer,
Be characterized in that: in step 4), the material of the metal layer is Ni, Co, Ti, Pt, NiPt, NiTi or TiPt, the metal layer
With a thickness of 2nm~1000nm.
10. the method according to claim 1 for preparing metal-semiconductor alloy using controlled imperfections graphene insert layer,
It is characterized by: the annealing atmosphere of annealing is vacuum, N in step 5)2, Ar or nitrogen and hydrogen mixture, annealing temperature 200
DEG C~1000 DEG C, annealing time is 15s~100s.
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| CN103208425A (en) * | 2013-03-22 | 2013-07-17 | 中国科学院上海微系统与信息技术研究所 | Process for manufacturing high-dielectric constant (K) metal gate and germanium (Ge) based metal oxide semiconductor (MOS) device prepared through graphene |
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| CN103208425A (en) * | 2013-03-22 | 2013-07-17 | 中国科学院上海微系统与信息技术研究所 | Process for manufacturing high-dielectric constant (K) metal gate and germanium (Ge) based metal oxide semiconductor (MOS) device prepared through graphene |
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| 《Graphene as a diffusion barrier for Al and Ni/Au contacts on silicon》;Hong-Yeol Kim et al.;《Journal of Vacuum Science & Technology B》;20120423;第30卷(第3期);7503-7511 * |
| Juree Hong et al..《Graphene as an atomically thin barrier to Cu diffusion into Si》.《Nanoscale》.2012,第6卷(第13期),7503-7511. * |
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