CN106710554A - Scintillation drift optimization circuit as well as optimization method thereof, array substrate and display device - Google Patents

Abstract

The invention provides a flicker drift optimization circuit, an optimization method, an array substrate, and a display device, which relate to the field of display technology and can eliminate residual charges in capacitors and improve the phenomenon of flicker drift. Wherein, the flicker drift optimization circuit includes a trigger module, a charge outflow control module, a first switch tube and a second switch tube; the control terminal of the first switch tube is connected to the trigger module, the input terminal is connected to the drive signal input terminal, and the output terminal is connected to the charge outflow control module. The control modules are connected; the first switch tube is turned on during the charge elimination period, so that the charge outflow control module works, and the residual charge in the capacitor of each sub-pixel flows out; the control terminal of the second switch tube is connected with the output terminal of the trigger module, and the input terminal is connected with the trigger module output terminal. The drive signal input terminals are connected; the second switch tube is turned on during the display control period, so that the output terminal of the second switch tube outputs a control signal to control the display of each sub-pixel. The above-mentioned flicker drift optimization circuit is used to improve the phenomenon of flicker drift in the display screen.

Description

Flicker drift optimization circuit and optimization method, array substrate, display device

technical field

The invention relates to the technical field of liquid crystal display, in particular to a flicker drift optimization circuit and optimization method, an array substrate, and a display device.

Background technique

At present, liquid crystal displays have been widely used in people's lives, and with the development of display technology, people have higher and higher requirements for images displayed on liquid crystal displays.

After each power-off of the liquid crystal display, the capacitor in each sub-pixel of the array substrate will retain some charge. When the liquid crystal display is turned on next time, when the source driver charges the capacitor of each sub-pixel to display the screen, the remaining charge in the capacitor will cause the polarity of the voltage of each pixel electrode to deviate. The deviation will cause the voltage of the common electrode to deviate from the standard value, causing flickering and drifting of the picture displayed on the liquid crystal display, resulting in a decrease in the quality of the picture displayed on the liquid crystal display, and even causing discomfort to people in serious cases.

Contents of the invention

The invention provides a flicker drift optimization circuit and optimization method, an array substrate, and a display device, which can eliminate the residual charge in the capacitor before the display device is turned on, and improve the flicker drift phenomenon in the display screen.

To achieve the above object, the present invention adopts the following technical solutions:

The first aspect of the present invention provides a flicker drift optimization circuit, a working cycle of the flicker drift optimization circuit is divided into a charge elimination period and a display control period; the flicker drift optimization circuit includes a trigger module, a charge outflow control module, a second A switch tube and a second switch tube; wherein, the control terminal of the first switch tube is connected to the output terminal of the trigger module, the input terminal of the first switch tube is connected to the drive signal input terminal, and the first switch tube is connected to the output terminal of the trigger module. The output end of the switch tube is connected to the charge outflow control module; the first switch tube is used to: conduct under the control of the trigger module during the charge elimination period, and input the drive signal input terminal Under the action of the driving signal, the charge outflow control module is made to work, so that the residual charge in the capacitance of each sub-pixel flows out; during the display control period, it is turned off under the control of the trigger module, so that the charge outflow The control module does not work; the control terminal of the second switch tube is connected to the output terminal of the trigger module, and the input terminal of the second switch tube is connected to the drive signal input terminal; the second switch tube is used for: In the display control period, it is turned on under the control of the trigger module, and under the action of the driving signal input from the driving signal input terminal, the output terminal of the second switching tube outputs a control signal to control each Sub-pixel display; during the period of charge elimination, it is turned off under the control of the trigger module, and each sub-pixel is controlled not to display.

Using the flicker drift optimization circuit provided by the present invention, based on the connection relationship between the various parts in the flicker drift optimization circuit, during the charge elimination period, the trigger module controls the first switch to be turned on and the second switch to be turned off. During the control period, the trigger module controls the first switch tube to be turned off and the second switch tube to be turned on. In this way, before the liquid crystal display is turned on to display images, the charge outflow control module first controls the outflow of remaining charges in the capacitors of the sub-pixels to eliminate the residual charges in the capacitors. In this way, the residual charges in the capacitors of the sub-pixels can be prevented from disturbing the voltage of the common electrode, and the voltage of the common electrode can be prevented from deviating from a standard value, thereby greatly improving the phenomenon of flicker drift in the display screen.

The second aspect of the present invention provides a flicker drift optimization method, which is applied to the flicker drift optimization circuit to optimize the flicker drift; the flicker drift optimization circuit includes a trigger module, a charge outflow control module, a first switch tube and The second switching tube; a working cycle of the flicker drift optimization circuit is divided into a charge elimination period and a display control period; the flicker drift optimization method includes: during the charge elimination period, the trigger module controls the second switch The switch is turned off to control each sub-pixel to not display; the trigger module controls the first switch to be turned on, and under the action of the drive signal input from the drive signal input terminal, the charge outflow control module works to make The charge remaining in the capacitance of each sub-pixel flows out; during the display control period, the trigger module controls the second switch to be turned on, and under the action of the drive signal input from the drive signal input terminal, the second switch The output terminal of the tube outputs a control signal to control the display of each sub-pixel; the trigger module controls the first switch tube to be turned off, so that the charge outflow control module does not work.

The beneficial effect of the flicker drift optimization method provided by the present invention is the same as that of the flicker drift optimization circuit provided by the first aspect of the present invention, and will not be repeated here.

A third aspect of the present invention provides an array substrate, and the array substrate includes the flicker drift optimization circuit according to the first aspect of the present invention.

The beneficial effect of the array substrate provided by the present invention is the same as that of the flicker drift optimization circuit provided by the first aspect of the present invention, and will not be repeated here.

A fourth aspect of the present invention provides a display device, the display device comprising the array substrate according to the third aspect of the present invention.

The beneficial effect of the display device provided by the present invention is the same as that of the flicker drift optimization circuit provided by the first aspect of the present invention, and will not be repeated here.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a first structural schematic diagram of a flicker drift optimization circuit provided by Embodiment 1 of the present invention;

FIG. 2 is a second structural schematic diagram of the flicker drift optimization circuit provided by Embodiment 1 of the present invention;

FIG. 3 is a timing diagram of various signal changes during the working process of the flicker drift optimization circuit provided by Embodiment 1 of the present invention.

Explanation of reference signs:

1-trigger module; 2-charge outflow control module;

3-capacitor; 11-delay unit;

K ₁ - the first switch tube; K ₂ - the second switch tube;

V _GH - drive signal input terminal; VDD - trigger signal input terminal;

XOR-exclusive OR gate; VDD_D-the output terminal of the delay unit;

INV ₁ - first inverter; INV ₂ - second inverter;

CLK ₁ _P-the forward control terminal of the first switch tube; CLK ₁ _N-the reverse control terminal of the first switch tube;

CLK ₂ _P-the positive control terminal of the second switch tube; CLK ₂ _N-the reverse control terminal of the second switch tube;

CLC _i - liquid crystal capacitor; CSC _i - storage capacitor;

R ₃ - third resistor; V _com - common voltage terminal;

GND—ground terminal; M ₁₁ ˜M _1N —the first transistor;

R ₁ - the first resistor; V _GH _1 - the output terminal of the first switching tube;

R ₂ - second resistance; C _oom - parasitic capacitance;

M _2i - the second transistor; V _GH _2 - the output end of the second switching transistor.

detailed description

In order to make the above objects, features and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Apparently, the described embodiments are only some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

Embodiment one

As shown in FIG. 1 , this embodiment provides a flicker drift optimization circuit. A working cycle of the flicker drift optimization circuit is divided into a charge elimination period and a display control period.

The flicker drift optimization circuit may specifically include a trigger module 1 , a charge outflow control module 2 , a first switch K ₁ and a second switch K ₂ .

Wherein, the control terminal of the _first switching tube K1 is connected to the output terminal of the trigger module ₁ , the input terminal of the first switching tube K1 is connected to the drive signal input terminal _VGH , and the output terminal of the _first switching tube K1 is connected to the charge outflow The control module 2 is connected.

The _first switch tube K1 is used for: during the charge elimination period, it is turned on under the control of the trigger module 1, and under the action of the drive signal input by the drive signal input terminal V _GH , the charge flows out of the control module 2 to work, and then the The charge remaining in the capacitor 3 in each sub-pixel flows out; during the display control period, it is turned off under the control of the trigger module 1, so that the charge outflow control module 2 does not work.

The control terminal of the _second switch tube K2 is connected to the output terminal of the trigger module 1, and the input terminal of the _second switch tube K2 is connected to the drive signal input terminal _VGH .

The _second switch tube K2 is used for: during the display control period, it is turned on under the control of the trigger module 1, and under the action of the drive signal input from the drive signal input terminal V _GH , the output terminal of the _second switch tube K2 Output control signals to charge the capacitor 3 in the sub-pixels to control the display of each sub-pixel; during the charge elimination period, turn off under the control of the trigger module 1 to control each sub-pixel to not display.

Using the flicker drift optimization circuit provided in this embodiment, based on the connection relationship between the various parts in the flicker drift optimization circuit, during the charge elimination period, the trigger module ₁ controls the first switch tube K1 to conduct, and the second switch tube K ₂ is turned off, and during the display control period, the trigger module ₁ controls the first switch tube K1 to be turned off, and the _second switch tube K2 to be turned on. In this way, before the liquid crystal display is turned on to display images, the charge outflow control module 2 first controls the outflow of the remaining charges in the capacitor 3 of the sub-pixel to eliminate the residual charges in the capacitor 3 . In this way, the residual charge in the capacitor 3 of the sub-pixel can be prevented from disturbing the voltage of the common electrode, and the voltage of the common electrode can be prevented from deviating from a standard value, thereby greatly improving the phenomenon of flicker drift in the display screen.

As shown in FIG. 2 , the trigger module 1 may specifically include a trigger signal input terminal VDD, a delay unit 11 and an exclusive OR gate XOR.

Wherein, the input terminal of the delay unit 11 is connected to the trigger signal input terminal VDD, the first input terminal of the exclusive OR gate XOR is connected to the trigger signal input terminal VDD, and the second input terminal of the exclusive OR gate XOR is connected to the output terminal VDD_D of the delay unit , the output terminal of the XOR gate XOR is connected with the control terminal of the _first switching tube K1 and the control terminal of the _second switching tube K2.

The working principle of the delay unit 11 and the exclusive OR gate XOR is described below by taking the trigger signal outputting a high level trigger signal from the trigger signal input terminal VDD as an example:

When the trigger signal input terminal VDD just outputs a high-level trigger signal, the first input terminal of the exclusive OR gate XOR receives a high-level signal, and since the delay unit 11 has the function of delaying the output of the signal, at the current moment, The signal output from the output terminal VDD_D of the delay unit is low level, and the second input terminal of the exclusive OR gate XOR receives the low level signal. Based on the working principle of the exclusive OR gate XOR, the signal output from the output terminal of the exclusive OR gate XOR is at a high level at this moment.

When the trigger signal input terminal VDD continuously outputs a high-level trigger signal for a period of time, and the trigger signal has been delayed by the delay unit 11 for output, both the first input terminal and the second input terminal of the exclusive OR gate XOR receive If the signal is high level, the signal output by the exclusive OR gate XOR is low level at this moment.

Optionally, the delay unit 11 may include 2M first inverters INV ₁ , where M is an integer greater than or equal to 1. 2M first inverters INV ₁ are used to form the delay unit 11, and the trigger signal input by the trigger signal input terminal VDD needs to be transmitted and converted through a plurality of first inverters INV ₁ , which causes the signal to be delayed for a period of time. The output, on the other hand, adopts 2M first inverters INV ₁ , which can also ensure that the state of the delayed trigger signal output by the delay unit 11 is the same as that of the trigger signal.

It should be noted that the _first switching tube K1 and the _second switching tube K2 in this embodiment can be conducted at _a low level or at a high level. The type of the _second switching tube K2 is determined.

Preferably, both the first switching tube K ₁ and the second switching tube K ₂ may be transmission gate switches, and in this case, the flicker drift optimization circuit provided in this embodiment further includes a second inverter INV ₂ . The output terminals of the XOR gate XOR are respectively connected to the forward control terminal CLK ₁ _P of the first switch tube, the reverse control terminal CLK ₂ _N of the second switch tube and the input terminal of the second inverter INV ₂ ; The output terminals of the phaser INV ₂ are respectively connected to the inverting control terminal CLK ₁ _N of the first switching transistor and the forward controlling terminal CLK ₂ _P of the second switching transistor. In view of this connection relationship, when the output terminal of the exclusive OR gate XOR outputs a high-level signal, the positive control terminal CLK ₁ _P of the first switch tube receives the high-level signal output by the exclusive OR gate XOR, and the first switch tube The inversion control terminal CLK ₁ _N receives the low-level signal inverted by the second inverter INV ₂ , so that the first switch tube K ₁ is turned on. At the same time, the positive control terminal CLK ₂ _P of the second switch tube receives the low-level signal inverted by the second inverter INV ₂ , and the reverse control terminal CLK ₂ _N of the second switch tube receives the exclusive OR gate The high-level signal output by the XOR turns off the second switch tube K ₂ .

On the contrary, when the output terminal of the exclusive OR gate XOR outputs a low-level signal, the positive control terminal CLK ₁ _P of the first switch tube receives the low-level signal output by the exclusive OR gate XOR, and the first switch tube The inverting control terminal CLK ₁ _N receives the high-level signal inverted by the second inverter INV ₂ , so that the first switching tube K ₁ is turned off. At the same time, the positive control terminal CLK ₂ _P of the second switch tube receives the high-level signal inverted by the second inverter INV ₂ , and the reverse control terminal CLK ₂ _N of the second switch tube receives the exclusive OR gate The low-level signal output by the XOR makes the _second switch tube K2 turn on.

It can be seen that, according to the specific structure of the flicker drift optimization circuit provided in this embodiment, only one signal output from the output terminal of the exclusive OR gate XOR is needed to make the _first switching tube K1 and the _second switching tube K2 In two different states at the same time.

Further, the charge outflow control module 2 in the flicker drift optimization circuit may specifically include a plurality of first transistors M ₁₁ -M _1N corresponding to the capacitances in the sub-pixels one by one, and the gates of the first transistors M ₁₁ -M _1N are all The first resistor R ₁ is connected to the output terminal V _GH _1 of the first switch tube, the drains of the first transistors M ₁₁ ~M _1N are all connected to the ground terminal GND through the second resistor R ₂ , and the first transistors M ₁₁ ~M The source of _1N is connected to the capacitor.

When the gates of the first transistors M ₁₁ -M _1N receive the high-level signal output by the output terminal V _GH _1 of the first switching tube, the first transistors M ₁₁ -M _1N are turned on, and the liquid crystal capacitor CLC _i and the storage The charge remaining in the capacitor CSC _i can flow into the ground terminal GND through the second resistor R ₂ .

It should be noted that the capacitance of each sub-pixel specifically includes a liquid crystal capacitor CLC _i and a storage capacitor CSC _i connected in series. The liquid crystal capacitor CLC _i and the storage capacitor CSC _i are respectively connected to the ground terminal GND through the third resistor _R3 , and the storage capacitor CSC _i is connected to the source of the first transistor corresponding to the sub-pixel. According to the connection relationship between the liquid crystal capacitor CLC _i and the storage capacitor CSC _i , when the first transistors M ₁₁ ~ M _1N are turned on, the remaining charges in the liquid crystal capacitor CLC _i and the storage capacitor CSC _i can not only flow to the ground through the second resistor R ₂ The terminal GND can also flow to the ground terminal GND through the third resistor R ₃ , thus increasing the outflow path of the residual charge, thereby ensuring that all the residual charge flows out.

In addition, each sub-pixel should further include a second transistor M _2i , where i is the label of the column where the second transistor is located. The gate of the second transistor M _2i is connected to the output terminal V _{GH_2} of the second switching tube, the drain of the second transistor M _2i is connected to the corresponding liquid crystal capacitor CLC _i , and the source of the second transistor M _2i is connected to the corresponding first The source of a transistor is connected and also connected to the source line.

When the _second switch tube K2 is turned on, under the action of the drive signal input from the drive signal input terminal _VGH , the second transistor _M2i is turned on, and the source line outputs a display drive signal to the corresponding sub-pixel, driving the corresponding sub-pixels for display.

It can be understood that FIG. 2 only schematically shows the structure of a row of sub-pixels in the array substrate, wherein CLC ₁ , CSC ₁ and M ₂₁ respectively correspond to the liquid crystal capacitance, the storage capacitor and the second Transistors, CLC ₂ , CSC ₂ and M ₂₂ respectively correspond to the liquid crystal capacitor, storage capacitor and second transistor in the second column of sub-pixels in a row, and so on, CLC _N , CSC _N and M _2N respectively correspond to the Nth column of sub-pixels in a row The liquid crystal capacitance, the storage capacitance and the second transistor in the. i=1 to N as described above.

In addition, the liquid crystal capacitor CLC _i and the storage capacitor CSC _i are also connected to the first plate of the parasitic capacitor C _oom , and the second plate of the parasitic capacitor C _oom is connected to the ground terminal GND. In addition, the first plates of the liquid crystal capacitor CLC _i , the storage capacitor CSC _i and the parasitic capacitor C _oom are also connected to the common voltage terminal V _com .

The functions of the parasitic capacitance C _oom and the common voltage terminal V _com are the same as those in the prior art, and will not be repeated here.

In order to describe more clearly how the flicker drift optimization circuit provided in this embodiment works, the following combines the specific structure of the flicker drift optimization circuit shown in FIG. 2 and the timing diagram of signal changes shown in FIG. The working process of the flicker drift optimization circuit is described in detail. Wherein, FIG. 3 is a time sequence diagram of signal changes in the period between the last power-off of the liquid crystal display and the next power-on display screen of the liquid crystal display.

In the first period, after the liquid crystal display is turned off, the trigger signal output by the trigger signal input terminal VDD and the drive signal output by the drive signal input terminal V _GH are both low level, and the delayed trigger signal output by the output terminal VDD_D of the delay unit is also low. is low level.

Therefore, the signal received by the forward control terminal CLK ₁ _P of the first switch tube is low level, the signal received by the reverse control terminal CLK ₁ _N is high level, and the first switch tube K ₁ is turned off. The signal output from the output terminal V _GH _1 of the first switching tube is at a low level, the first transistors M ₁₁ -M _1N cannot be turned on, and the residual charges in the liquid crystal capacitor CLC _i and the storage capacitor CSC _i cannot flow out.

At the same time, the signal received by the forward control terminal CLK ₂ _P of the second switch tube is high level, the signal received by the reverse control terminal CLK ₂ _N is low level, and the second switch tube K ₂ is turned on. However, since the drive signal output by the drive signal input terminal V _GH is at low level, the signal output from the output terminal V _{GH_2} of the second switch tube is also at low level, so that the second transistor M _2i cannot be turned on, so that each The sub-pixel is in a non-display state.

In the second period, the trigger signal output by the trigger signal input terminal VDD starts to be at a high level, and the drive signal output by the drive signal input terminal V _GH is at a low level. Due to the delay effect of the delay unit 11, at this time, the delay The delayed trigger signal output by the output terminal VDD_D of the unit is still at low level, and the signal output by the output terminal of the exclusive OR gate XOR is at high level.

Therefore, the signal received by the forward control terminal CLK ₁ _P of the first switch tube is at a high level, the signal received by the reverse control terminal CLK ₁ _N is at a low level, and the first switch tube K ₁ is turned on. However, since the drive signal output by the drive signal input terminal V _GH is at a low level, the signal output from the output terminal V _GH _1 of the first switching tube is also at a low level, and the first transistors M ₁₁ -M _1N cannot be turned on, and the liquid crystal The residual charge in the capacitor CLC _i and the storage capacitor CSC _i cannot flow out.

At the same time, the signal received by the positive control terminal CLK ₂ _P of the second switch tube K ₂ is low level, the signal received by the reverse control terminal CLK ₂ _N is high level, the second switch tube K ₂ is turned off, The signal output from the output terminal V _GH _2 of the second switching transistor K ₂ is at a low level, and the second transistors M ₂₁ -M _2N cannot be turned on, so that each sub-pixel is in a non-display state.

In the third period, the trigger signal output from the trigger signal input terminal VDD maintains a high level, and the drive signal output from the drive signal input terminal _VGH also maintains a high level.

In the third period, the signal output from the output terminal VDD_D of the delay unit is still at low level, therefore, the signal output from the output terminal of the exclusive OR gate XOR is at high level. At this time, the signal received by the forward control terminal CLK ₁ _P of the first switch tube is at a high level, the signal received by the reverse control terminal CLK ₁ _N is at a low level, and the first switch tube K ₁ is turned on. Since the drive signal output by the drive signal input terminal V _GH is at a high level, the signal output from the first switch tube output terminal V _GH _1 is also at a high level, the first transistors M ₁₁ -M _1N are turned on, and the liquid crystal capacitor CLC _i and the residual charge in the storage capacitor CSC _i can flow to the ground terminal through the _second resistor R2 and the third resistor _R3 .

At the same time, the signal received by the forward control terminal CLK ₂ _P of the second switch tube is low level, the signal received by the reverse control terminal CLK ₂ _N is high level, the second switch tube K ₂ is turned off, and the second switch tube K 2 is turned off. The signal output from the output terminal V _GH _2 of the switch tube K ₂ is at a low level, and the second transistor M _2i cannot be turned on, so that each sub-pixel is in a non-display state.

It should be noted that, when all the residual charges in the liquid crystal capacitor CLC _i and the storage capacitor CSC _i are left, the corresponding residual voltage V is discharged to zero potential.

It can be understood that the third period corresponds to the charge elimination period in the working cycle of the flicker drift optimization circuit.

In the fourth period, the trigger signal input terminal VDD has been outputting a high-level trigger signal for a period of time, and the driving signal output by the driving signal input terminal V _GH is still at a high level during this period.

In the fourth period, the delay trigger signal output by the output terminal VDD_D of the delay unit is at high level, therefore, the signal output by the output terminal of the exclusive OR gate XOR is at low level. At this time, the signal received by the positive control terminal CLK ₁ _P of the first switching tube is low level, the signal received by the reverse control terminal CLK ₁ _N is high level, the first switching tube K ₁ is turned off, and the first switch The signal output by the transistor output terminal V _GH _1 is at low level, the first transistors M ₁₁ -M _1N cannot be turned on, and the residual charge in the liquid crystal capacitor CLC _i and the storage capacitor CSC _i cannot flow out.

At the same time, the signal received by the forward control terminal CLK ₂ _P of the second switch tube is high level, the signal received by the reverse control terminal CLK ₂ _N is low level, and the second switch tube K ₂ is turned on. Since the drive signal output by the drive signal input terminal V _GH is at a high level, the signal output from the output terminal V _{GH_2} of the second switching tube is at a high level, the second transistor _M2i is turned on, and the output from the source line The display driving signal drives the corresponding sub-pixels to display, that is, enters the normal display of the picture.

It can be understood that the fourth period corresponds to a display control period within the working cycle of the flicker drift optimization circuit.

Table 1 List of state changes of each signal corresponding to different time periods

In order to make the content in the table more clear and concise, in Table 1, VDD is used to refer to the trigger signal output from the trigger signal input terminal VDD, VDD_D is used to refer to the delayed trigger signal output from the output terminal VDD_D of the delay unit, and V _GH is used to refer to The drive signal output by the drive signal input terminal V _GH is represented by CLK ₁ _P and CLK ₁ _N respectively referring to the signals received by the forward control terminal CLK ₁ _P and the reverse control terminal CLK ₁ _N of the first switch tube, and V _GH _1 and V _GH _2 respectively refer to the signals output by the first switch tube output terminal V _GH _1 and the second switch tube output terminal V _GH _2, and CLK ₂ _P and CLK ₂ _N respectively refer to the positive signal of the second switch tube The signal received to the control terminal CLK ₂ _P and the reverse control terminal CLK ₂ _N. The symbols shown in the timing diagram of Fig. 3 are the same.

It should be noted that, according to actual conditions, the high-level trigger signal output by the trigger signal input terminal VDD may be 3.3V, and the high-level drive signal output by the drive signal input terminal _VGH may be 22V.

Embodiment two

This embodiment provides a flicker drift optimization method, which is applied to the flicker drift optimization circuit provided in Embodiment 1, and the flicker drift can be optimized by using the flicker drift optimization method.

As mentioned above, please refer to FIG. 2, the flicker drift optimization circuit may include a trigger module 1, a charge outflow control module 2, a first switch K ₁ and a second switch K ₂ ; a working cycle of the flicker drift optimization circuit is divided into Charge elimination period and display control period.

Correspondingly, the flicker drift optimization method specifically includes:

During the charge elimination period, the trigger module 1 controls the second switch tube K ₂ to turn off, and controls each sub-pixel to not display; the trigger module 1 controls the first switch tube K ₁ to turn on, and the drive signal input at the drive signal input terminal V _GH Under the action of the charge outflow control module 2, the charge remaining in the capacitor of each sub-pixel flows out.

In the display control period, the trigger module 1 controls the _second switch tube K2 to conduct, and under the action of the drive signal input by the drive signal input terminal V _GH , the output terminal of the _second switch tube K2 outputs a control signal to control each sub-switch Pixel display; the trigger module 1 controls the first switch tube K ₁ to turn off, so that the charge outflow control module 2 does not work.

Compared with the prior art, the beneficial effects of the flicker drift optimization method provided in this embodiment are the same as those of the flicker drift optimization circuit provided in the first embodiment above, and will not be repeated here.

When the _first switching tube K1 and the _second switching tube K2 in the flicker drift optimization circuit are transmission gate switches, and the flicker drift optimization circuit includes a second inverter INV ₂ , correspondingly, the flicker drift optimization method Also includes:

During the charge elimination period, the output terminal of the exclusive OR gate XOR outputs a high-level signal to the positive direction control terminal CLK ₁ _P of the first switch tube, and the second inverter INV ₂ converts the signal output from the output terminal of the exclusive OR gate XOR The high-level signal is inverted, the output terminal of the second inverter INV ₂ outputs a low-level signal to the inverting control terminal CLK ₁ _N of the first switch tube, and the first switch tube K ₁ is turned on.

The output terminal of the exclusive OR gate XOR outputs a high-level signal to the reverse control terminal CLK ₂ _N of the second switch tube, and the output terminal of the second inverter INV ₂ supplies the positive control terminal CLK ₂ _P of the second switch tube. A low-level signal is output, and the _second switch tube K2 is turned off.

During the display control period, the output terminal of the XOR gate XOR outputs a low-level signal to the positive control terminal CLK ₁ _P of the first switch tube, and the second inverter INV ₂ converts the signal output from the output terminal of the XOR gate XOR The low-level signal is inverted, the output terminal of the second inverter INV ₂ outputs a high-level signal to the inverting control terminal CLK ₁ _N of the first switch tube, and the first switch tube K ₁ is turned off.

The output terminal of the XOR gate XOR outputs a low-level signal to the reverse control terminal CLK ₂ _N of the second switch tube, and the output terminal of the second inverter INV ₂ supplies the positive control terminal CLK ₂ _P of the second switch tube. A high-level signal is output, and the _second switch tube K2 is turned on.

Embodiment three

This embodiment provides an array substrate, and the array substrate includes the flicker drift optimization circuit provided in the first embodiment.

Using the array substrate provided in this embodiment, since it includes the flicker drift optimization circuit provided in Embodiment 1, before the liquid crystal display is turned on to display the picture, it can first control the outflow of the remaining charge in the capacitor and eliminate the residual charge in the capacitor. charge. In this way, the residual charge in the capacitor can be prevented from disturbing the voltage of the common electrode, and the voltage of the common electrode can be prevented from deviating from a standard value, thereby greatly improving the phenomenon of flicker drift in the display screen.

Embodiment Four

This embodiment provides a display device, which includes the array substrate as described in the third embodiment.

With the display device provided in this embodiment, since it includes the array substrate provided in Embodiment 3, before the display device is turned on to display a picture, the charge remaining in the capacitance of the sub-pixel has been eliminated, and thus the large To a certain extent, the phenomenon of flickering and drifting in the display screen has been improved.

The above description is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention are all Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (10)

1. A flicker shift optimization circuit, wherein a duty cycle of the flicker shift optimization circuit is divided into a charge elimination period and a display control period; the flicker drift optimization circuit comprises a trigger module, a charge outflow control module, a first switch tube and a second switch tube; wherein,

the control end of the first switch tube is connected with the output end of the trigger module, the input end of the first switch tube is connected with the driving signal input terminal, and the output end of the first switch tube is connected with the charge outflow control module; the first switch tube is used for: in the charge elimination period, the control circuit is conducted under the control of the trigger module, and under the action of a driving signal input by the driving signal input terminal, the charge outflow control module works to make residual charges in the capacitor of each sub-pixel flow out; in the display control time interval, the display control module is controlled to be switched off so that the charge outflow control module does not work;

the control end of the second switch tube is connected with the output end of the trigger module, and the input end of the second switch tube is connected with the driving signal input terminal; the second switch tube is used for: in the display control time period, the display control circuit is conducted under the control of the trigger module, and under the action of a driving signal input by the driving signal input terminal, the output end of the second switching tube outputs a control signal to control each sub-pixel to display; and in the charge elimination period, the display is switched off under the control of the trigger module, and each sub-pixel is controlled not to display.

2. The flicker drift optimization circuit of claim 1, wherein the trigger block comprises a trigger signal input terminal, a delay unit, and an exclusive or gate; wherein,

the input end of the delay unit is connected with the trigger signal input terminal; the first input end of the exclusive-OR gate is connected with the trigger signal input terminal, the second input end of the exclusive-OR gate is connected with the output end of the delay unit, and the output end of the exclusive-OR gate is connected with the control end of the first switch tube and the control end of the second switch tube.

3. The flicker drift optimization circuit of claim 2, wherein the delay cell comprises 2M first inverters, wherein M is an integer greater than or equal to 1.

4. The flicker drift optimization circuit of claim 2, wherein the first switching tube and the second switching tube are transmission gate switches; the flicker drift optimization circuit further comprises a second inverter; the output end of the exclusive-or gate is respectively connected with the forward control end of the first switch tube, the reverse control end of the second switch tube and the input end of the second phase inverter, and the output end of the second phase inverter is respectively connected with the reverse control end of the first switch tube and the forward control end of the second switch tube.

5. The flicker drift optimization circuit according to claim 1, wherein the charge outflow control module comprises a plurality of first transistors corresponding to the capacitors in the sub-pixels, the gates of the first transistors are connected to the output terminal of the first switching tube through a first resistor, the drains of the first transistors are connected to the ground terminal through a second resistor, and the sources of the first transistors are connected to the capacitors in the corresponding sub-pixels.

6. The flicker shift optimization circuit according to claim 5, wherein the capacitor of each sub-pixel comprises a liquid crystal capacitor and a storage capacitor, and the liquid crystal capacitor and the storage capacitor are respectively connected to the ground terminal through a third resistor; one end of the third resistor is connected with the first pole plate of the parasitic capacitor, and the other end of the third resistor is connected with the second pole plate of the parasitic capacitor.

7. A flicker drift optimization method is characterized in that the method is applied to a flicker drift optimization circuit to optimize flicker drift; the flicker drift optimization circuit comprises a trigger module, a charge outflow control module, a first switch tube and a second switch tube; one working cycle of the flicker drift optimization circuit is divided into a charge elimination period and a display control period; the flicker drift optimization method comprises the following steps:

in the charge elimination period, the triggering module controls the second switching tube to be switched off and controls each sub-pixel not to display; the trigger module controls the first switch tube to be conducted, and under the action of a driving signal input by the driving signal input terminal, the charge outflow control module works to make residual charges of the capacitor of each sub-pixel flow out;

in the display control time period, the trigger module controls the second switch tube to be conducted, and under the action of a driving signal input by the driving signal input terminal, the output end of the second switch tube outputs a control signal to control each sub-pixel to display; the triggering module controls the first switch tube to be switched off, so that the charge outflow control module does not work.

8. The flicker drift optimization method according to claim 7, wherein the flicker drift optimization circuit further comprises a second inverter, and the first switch tube and the second switch tube are transmission gate switches; the flicker drift optimization method further comprises:

in the charge elimination period, the output end of the exclusive-or gate outputs a high-level signal to the forward control end of the first switch tube, the second phase inverter inverts the high-level signal output by the output end of the exclusive-or gate, the output end of the second phase inverter outputs a low-level signal to the reverse control end of the first switch tube, and the first switch tube is turned on;

the output end of the exclusive-or gate outputs a high-level signal to the reverse control end of the second switching tube, the output end of the second phase inverter outputs a low-level signal to the forward control end of the second switching tube, and the second switching tube is turned off;

in the display control period, the output end of the exclusive or gate outputs a low-level signal to the forward control end of the first switch tube, the second phase inverter inverts the low-level signal output by the output end of the exclusive or gate, the output end of the second phase inverter outputs a high-level signal to the reverse control end of the first switch tube, and the first switch tube is turned off;

the output end of the exclusive-or gate outputs a low-level signal to the reverse control end of the second switch tube, the output end of the second phase inverter outputs a high-level signal to the forward control end of the second switch tube, and the second switch tube is conducted.

9. An array substrate comprising the scintillation drift optimization circuit of any one of claims 1 to 6.

10. A display device comprising the array substrate according to claim 9.