CN106710554A - Scintillation drift optimization circuit as well as optimization method thereof, array substrate and display device - Google Patents

Scintillation drift optimization circuit as well as optimization method thereof, array substrate and display device Download PDF

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Publication number
CN106710554A
CN106710554A CN201710049150.5A CN201710049150A CN106710554A CN 106710554 A CN106710554 A CN 106710554A CN 201710049150 A CN201710049150 A CN 201710049150A CN 106710554 A CN106710554 A CN 106710554A
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switch tube
control
output end
display
flicker
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CN106710554B (en
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李云松
陆旭
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BOE Technology Group Co Ltd
Chongqing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chongqing BOE Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

The invention provides a scintillation drift optimization circuit as well as an optimization method thereof, an array substrate and a display device, relates to the technical field of display and aims to eliminate residual charge in capacitors and improve the phenomena of scintillation drift. The scintillation drift optimization circuit comprises a triggering module, a charge outflow control module, a first switch tube and a second switch tube; the control end of the first switch tube is connected with the triggering module; the input end of the first switch tube is connected with a driving signal input terminal; the output end of the first switch tube is connected with a charge outflow control module; the first switch tube is switched on in a charge eliminating time period, so that the charge outflow control module operates and enables residual charge in capacitors of sub-pixels to flow out; the control end of the second switch tube is connected with the output end of the triggering module; the input end of the second switch tube is connected with a driving signal input terminal; the second switch tube is switched on in a display control time period, so that control signals are output by the output end of the second switch tube and are used for controlling display of the sub-pixels. The scintillation drift optimization circuit is used for improving the phenomena of scintillation drift in display images.

Description

Flicker drift optimization circuit and optimization method, array substrate and display device
Technical Field
The invention relates to the technical field of liquid crystal display, in particular to a flicker drift optimization circuit, an optimization method, an array substrate and a display device.
Background
At present, liquid crystal displays have been widely used in human life, and with the development of display technology, people have higher and higher requirements for pictures displayed by liquid crystal displays.
After each power-off of the lcd, a part of the charge remains in the capacitor of each sub-pixel of the array substrate. When the lcd is turned on next time, in the process of charging the capacitor of each sub-pixel by the source driver to display the image, the residual charges in the capacitor may cause the positive and negative polarities of the voltage of each pixel electrode to deviate, and the deviation may cause the voltage of the common electrode to deviate from the standard value, so that the image displayed by the lcd may flicker, resulting in the quality of the image displayed by the lcd being reduced, and in severe cases, the lcd may feel uncomfortable.
Disclosure of Invention
The invention provides a flicker drift optimization circuit, a flicker drift optimization method, an array substrate and a display device, which can eliminate residual charges in a capacitor before the display device is started and improve the flicker drift phenomenon in a display picture.
In order to achieve the purpose, the invention adopts the following technical scheme:
a first aspect of the present invention provides a flicker shift optimization circuit, one duty cycle of which is divided into a charge elimination period and a display control period; the flicker drift optimization circuit comprises a trigger module, a charge outflow control module, a first switch tube and a second switch tube; the control end of the first switch tube is connected with the output end of the trigger module, the input end of the first switch tube is connected with the driving signal input terminal, and the output end of the first switch tube is connected with the charge outflow control module; the first switch tube is used for: in the charge elimination period, the control circuit is conducted under the control of the trigger module, and under the action of a driving signal input by the driving signal input terminal, the charge outflow control module works to make residual charges in the capacitor of each sub-pixel flow out; in the display control time interval, the display control module is controlled to be switched off so that the charge outflow control module does not work; the control end of the second switch tube is connected with the output end of the trigger module, and the input end of the second switch tube is connected with the driving signal input terminal; the second switch tube is used for: in the display control time period, the display control circuit is conducted under the control of the trigger module, and under the action of a driving signal input by the driving signal input terminal, the output end of the second switching tube outputs a control signal to control each sub-pixel to display; and in the charge elimination period, the display is switched off under the control of the trigger module, and each sub-pixel is controlled not to display.
By adopting the flicker drift optimization circuit provided by the invention, based on the connection relationship among all parts in the flicker drift optimization circuit, the trigger module controls the first switch tube to be switched on and the second switch tube to be switched off in the charge elimination period, and the trigger module controls the first switch tube to be switched off and the second switch tube to be switched on in the display control period. Therefore, before the liquid crystal display starts up to display the picture, the charge outflow control module controls the outflow of the residual charges in the capacitors of the sub-pixels to eliminate the residual charges in the capacitors. Therefore, the disturbance of residual charges in the capacitor of the sub-pixel to the voltage of the common electrode can be avoided, the voltage of the common electrode is prevented from deviating from a standard value, and the phenomenon of flicker drift in a display picture is improved to a great extent.
The invention provides a flicker drift optimization method, which is applied to a flicker drift optimization circuit to optimize flicker drift; the flicker drift optimization circuit comprises a trigger module, a charge outflow control module, a first switch tube and a second switch tube; one working cycle of the flicker drift optimization circuit is divided into a charge elimination period and a display control period; the flicker drift optimization method comprises the following steps: in the charge elimination period, the triggering module controls the second switching tube to be switched off and controls each sub-pixel not to display; the trigger module controls the first switch tube to be conducted, and under the action of a driving signal input by the driving signal input terminal, the charge outflow control module works to make residual charges of the capacitor of each sub-pixel flow out; in the display control time period, the trigger module controls the second switch tube to be conducted, and under the action of a driving signal input by the driving signal input terminal, the output end of the second switch tube outputs a control signal to control each sub-pixel to display; the triggering module controls the first switch tube to be switched off, so that the charge outflow control module does not work.
The advantageous effects of the flicker shift optimization method provided by the present invention are the same as the advantageous effects of the flicker shift optimization circuit provided by the first aspect of the present invention, and are not described herein again.
A third aspect of the invention provides an array substrate comprising a scintillation drift optimisation circuit as described in the first aspect of the invention.
The beneficial effects of the array substrate provided by the invention are the same as those of the flicker shift optimization circuit provided by the first aspect of the invention, and are not described herein again.
A fourth aspect of the present invention provides a display device comprising the array substrate according to the third aspect of the present invention.
The advantageous effects of the display device provided by the present invention are the same as the advantageous effects of the flicker shift optimization circuit provided by the first aspect of the present invention, and are not described herein again.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a first schematic structural diagram of a flicker shift optimization circuit according to a first embodiment of the present invention;
fig. 2 is a schematic structural diagram of a flicker shift optimization circuit according to a first embodiment of the present invention;
fig. 3 is a timing diagram of signal changes during the operation of the flicker drift optimization circuit according to an embodiment of the present invention.
Description of reference numerals:
1-a trigger module; 2-a charge outflow control module;
3-capacitance; 11-a delay unit;
K1-a first switching tube; K2-a second switching tube;
VGH-a drive signal input terminal; a VDD-trigger signal input terminal;
an XOR-XOR gate; VDD _ D-output of delay cell;
INV1-a first inverter; INV2-a second inverter;
CLK1p-a positive control end of the first switch tube; CLK1N-the reverse control end of the first switch tube;
CLK2p-a positive control end of a second switching tube; CLK2N-the reverse control end of the second switch tube;
CLCi-a liquid crystal capacitance; CSCi-a storage capacitance;
R3-a third resistance; vcom-a common voltage terminal;
GND-ground; m11～M1N-a first transistor;
R1-a first resistance; vGH1-output end of the first switch tube;
R2-a second resistance; coom-a parasitic capacitance;
M2i-a second transistor; vGH_2-output end of second switch tube.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example one
As shown in fig. 1, the present embodiment provides a flicker shift optimization circuit whose one duty cycle is divided into a charge elimination period and a display control period.
The flicker drift optimization circuit specifically comprises a trigger module 1, a charge outflow control module 2 and a first switch tube K1And a second switching tube K2。
Wherein, the first switch tube K1The control end of the trigger module 1 is connected with the output end of the trigger module 1, and the first switch tube K1Input terminal and driving signal input terminal VGHConnected to a first switching tube K1Is connected to the charge outflow control module 2.
First switch tube K1For: in the charge elimination period, the switch-on is controlled by the trigger module 1 and the drive signal input terminal VGHUnder the action of the input driving signal, the charge outflow control module 2 works, and further the charges remained in the capacitors 3 in the sub-pixels flow out; and in the display control period, the display control module is switched off under the control of the trigger module 1, so that the charge outflow control module 2 does not work.
Second switch tube K2The control end of the trigger module 1 is connected with the output end of the trigger module 1, and the second switch tube K2Input terminal and driving signal input terminal VGHAre connected.
Second switch tube K2For: in the display control period, the display control circuit is conducted under the control of the trigger module 1 and at the drive signal input terminal VGHOf the input drive signalUnder the action of the second switch tube K2The output end of the voltage regulator outputs a control signal to charge the capacitor 3 in the sub-pixel and control the display of each sub-pixel; in the charge elimination period, the display is turned off under the control of the trigger module 1, and the sub-pixels are controlled not to display.
By adopting the flicker drift optimization circuit provided by the embodiment, based on the connection relationship among the parts in the flicker drift optimization circuit, the trigger module 1 controls the first switch tube K during the charge elimination period1Conducting the second switch tube K2Turning off, and in the display control time interval, the trigger module 1 controls the first switch tube K1Turn-off, second switch tube K2And conducting. Thus, before the liquid crystal display starts up to display the picture, the charge outflow control module 2 controls the outflow of the residual charges in the capacitor 3 of the sub-pixel to eliminate the residual charges in the capacitor 3. Therefore, the disturbance of the residual charge in the capacitor 3 of the sub-pixel to the common electrode voltage can be avoided, the common electrode voltage is prevented from deviating from the standard value, and the phenomenon of flicker drift in the display picture is improved to a great extent.
As shown in fig. 2, the trigger module 1 may specifically include a trigger signal input terminal VDD, a delay unit 11, and an exclusive or gate XOR.
The input end of the delay unit 11 is connected with a trigger signal input terminal VDD, the first input end of the XOR gate is connected with the trigger signal input terminal VDD, the second input end of the XOR gate is connected with the output end VDD _ D of the delay unit, and the output end of the XOR gate is connected with the first switch tube K1Control terminal and second switching tube K2Are connected with each other.
The following description will be made of the operation principle of the delay unit 11 and the exclusive or gate XOR, taking as an example that the trigger signal input terminal VDD outputs a high-level trigger signal:
when the trigger signal input terminal VDD outputs a high-level trigger signal, the first input terminal of the XOR gate XOR receives a high-level signal, and since the delay unit 11 has the function of delaying the signal for output, at the present moment, the signal output by the output terminal VDD _ D of the delay unit is at a low level, and the second input terminal of the XOR gate XOR receives a low-level signal. Based on the working principle of the exclusive or gate XOR, the signal output by the output terminal of the exclusive or gate XOR is at a high level at the moment.
When the trigger signal input terminal VDD continues to output the trigger signal with the high level for a period of time and the trigger signal is also output after being delayed by the delay unit 11, the first input terminal and the second input terminal of the XOR gate XOR both receive the signal with the high level, and the signal output by the XOR gate XOR at this time is the low level.
Optionally, the delay unit 11 may include 2M first inverters INV1Wherein M is an integer greater than or equal to 1. Using 2M first inverters INV1The delay unit 11 is formed by a plurality of first inverters INV for the trigger signal inputted from the trigger signal input terminal VDD1Performing transmission and conversion, which makes the signal output after delaying for a period of time, and on the other hand, using 2M first inverters INV1It is also ensured that the state of the delayed trigger signal output by the delay unit 11 is the same as the state of the trigger signal.
In this embodiment, the first switch tube K1And a second switching tube K2Can be conducted at low level or high level according to the first switch tube K1And a second switching tube K2Is determined.
Preferably, the first switch tube K1And a second switching tube K2May be a transmission gate switch, in this case, the flicker drift optimization circuit provided in this embodiment further includes a second inverter INV2. The output ends of the XOR gates are respectively connected with the positive control end CLK of the first switch tube1P, reverse control end CLK of second switch tube2N and a second inverter INV2The input ends of the two are connected; second inverter INV2Respectively with the reverse control terminal CLK of the first switch tube1N and the positive control end CLK of the second switch tube2P are connected. IdentificationIn this connection, when the output terminal of the XOR gate XOR outputs a high-level signal, the positive control terminal CLK of the first switch tube1P receives the high level signal outputted from the XOR gate, and the reverse control terminal CLK of the first switch tube1N is received by the second inverter INV2The inverted low level signal makes the first switch tube K1And conducting. At the same time, the positive control terminal CLK of the second switch tube2P is received by the second inverter INV2The inverted low level signal, the inverted control terminal CLK of the second switch tube2N receives the high level signal outputted from the XOR gate, so that the second switch tube K2And (6) turning off.
In contrast, when the output terminal of the XOR gate XOR outputs a low-level signal, the positive control terminal CLK of the first switch tube1A P receiving low level signal output by the XOR gate, and a reverse control terminal CLK of the first switch tube1N is received by the second inverter INV2High level signal after phase inversion enables the first switch tube K1And (6) turning off. At the same time, the positive control terminal CLK of the second switch tube2P is received by the second inverter INV2The inverted high level signal, the inverted control terminal CLK of the second switch tube2N receives the low level signal outputted from the XOR gate, so that the second switch tube K2And conducting.
It can be known that, according to the specific structure of the flicker drift optimization circuit provided in this embodiment, only one signal output from the output terminal of the XOR gate XOR is needed to enable the first switch tube K to be connected to the output terminal of the XOR gate XOR1And a second switching tube K2In two different states at the same time.
Further, the charge outflow control module 2 in the flicker drift optimization circuit may specifically include a plurality of first transistors M in one-to-one correspondence with the capacitances in the sub-pixels11～M1NFirst transistor M11～M1NAre all connected through a first resistor R1And the output end V of the first switch tubeGH1 is connected to a first transistor M11～M1NAll pass through the second resistor R2Connected to ground GND, a first transistor M11～M1NIs connected to the capacitor.
When the first transistor M11～M1NThe grid electrode of the first switch tube receives the output end V of the first switch tubeGHThe first transistor M is connected to the output signal of _111～M1NConducting, liquid crystal capacitor CLCiAnd a storage capacitor CSCiThe residual charge in the second resistor can pass through the second resistor R2Flows into the ground GND.
It should be noted that the capacitor of each sub-pixel specifically includes a liquid crystal capacitor CLC connected in seriesiAnd a storage capacitor CSCi. Liquid crystal capacitor CLCiAnd a storage capacitor CSCiRespectively pass through a third resistor R3Connected to ground GND and storage capacitor CSCiAnd the source electrode of the first transistor corresponding to the sub-pixel is connected. According to liquid crystal capacitance CLCiAnd a storage capacitor CSCiWhen the first transistor M is connected11～M1NWhen turned on, the liquid crystal capacitor CLCiAnd a storage capacitor CSCiCan be charged not only via the second resistor R2Flows to the ground GND and can also pass through the third resistor R3And the residual charges flow to the ground end GND, so that the outflow path of the residual charges is increased, and the residual charges can be ensured to completely flow out.
In addition, each sub-pixel should further include a second transistor M2iWhere i is the reference number of the column in which the second transistor is located. Second transistor M2iGrid of the first switch tube and the output end V of the second switch tubeGHA 2 connection, a second transistor M2iAnd the corresponding liquid crystal capacitor CLCiConnected, a second transistor M2iIs connected to the source of the corresponding first transistor and is also connected to the source line.
When the second switch tube K2At the time of conduction, at the drive signal input terminal VGHThe second transistor M is driven by the input driving signal2iConducting, the source line outputs to the corresponding sub-pixelAnd the display driving signal drives the corresponding sub-pixel to display.
It will be understood that fig. 2 is only schematic to show the structure of a row of sub-pixels in an array substrate, wherein the CLC is configured to1、CSC1And M21Respectively corresponding to the liquid crystal capacitor, the storage capacitor and the second transistor, CLC2、CSC2And M22Respectively corresponding to the liquid crystal capacitor, the storage capacitor and the second transistor in the second column of sub-pixels in one row, and so on, CLCN、CSCNAnd M2NThe liquid crystal capacitor, the storage capacitor and the second transistor in the sub-pixel of the Nth column in one row respectively. I is 1 to N as described above.
In addition, a liquid crystal capacitor CLCiStorage capacitor CSCiAnd also parasitic capacitance CoomIs connected to the first plate of the capacitor CoomThe second pole plate is connected with the ground terminal GND. In addition, a liquid crystal capacitor CLCiStorage capacitor CSCiAnd a parasitic capacitance CoomThe first polar plate is also connected with a common voltage terminal Vcom。
Parasitic capacitance CoomAnd a common voltage terminal VcomThe functions are the same as those in the prior art, and are not described in detail herein.
In order to more clearly describe how the flicker shift optimization circuit provided in this embodiment works, the following describes in detail the working process of the flicker shift optimization circuit provided in this embodiment with reference to the specific structure of the flicker shift optimization circuit shown in fig. 2 and the timing chart of the signal change shown in fig. 3. FIG. 3 is a timing diagram of signal changes in the period from the last power-off to the next power-on of the LCD.
In the first time interval, after the liquid crystal display is turned off, the trigger signal output by the trigger signal input terminal VDD and the drive signal input terminal VGHThe output driving signals are all low level, and the delay trigger signal output by the output end VDD _ D of the delay unit is also low level.
Therefore, the positive control terminal CLK of the first switch tube1The P received signal is low level, and the control terminal CLK is reversed1The signal received by N is high level, the first switch tube K1And (6) turning off. First switch tube output end VGHThe signal output from _1is low level, the first transistor M11～M1NNon-conductive liquid crystal capacitor CLCiAnd a storage capacitor CSCiThe residual charge in (2) cannot flow out.
At the same time, the positive control terminal CLK of the second switch tube2P received signal is high level, reverse control terminal CLK2The signal received by N is low level, the second switch tube K2And conducting. But due to the drive signal input terminal VGHThe output driving signal is low level, so the output end V of the second switch tubeGHThe signal output from _2is also low, so that the second transistor M is turned on2iAnd the sub-pixels can not be conducted, so that the sub-pixels are in a non-display state.
In the second period, the trigger signal output from the trigger signal input terminal VDD is at high level, and the drive signal input terminal V is at high levelGHThe output driving signal is at low level, and due to the delay action of the delay unit 11, the delayed trigger signal output by the output terminal VDD _ D of the delay unit is still at low level, and the signal output by the output terminal of the XOR gate XOR is at high level.
Therefore, the positive control terminal CLK of the first switch tube1P received signal is high level, reverse control terminal CLK1The signal received by N is low level, the first switch tube K1And conducting. But due to the drive signal input terminal VGHThe output driving signal is low level, so the output end V of the first switch tubeGHThe signal output from _1is also low, the first transistor M11～M1NNon-conductive liquid crystal capacitor CLCiAnd a storage capacitor CSCiThe residual charge in (2) cannot flow out.
At the same time, the second switch tube K2Is turning toTo the control terminal CLK2The P received signal is low level, and the control terminal CLK is reversed2The signal received by N is high level, the second switch tube K2Turn-off, second switch tube K2Output end VGHThe signal output from the second transistor M is at low level21～M2NAnd the sub-pixels can not be conducted, so that the sub-pixels are in a non-display state.
In the third period, the trigger signal output from the trigger signal input terminal VDD is kept at high level, and the drive signal input terminal VGHThe output drive signal is also high.
In the third period, the signal output from the output terminal VDD _ D of the delay unit is still at a low level, and therefore, the signal output from the output terminal of the XOR gate XOR is at a high level. At this time, the positive control terminal CLK of the first switch tube1P received signal is high level, reverse control terminal CLK1The signal received by N is low level, the first switch tube K1And conducting. Due to the drive signal input terminal VGHThe output driving signal is high level, so the output end V of the first switch tubeGHThe signal output from _1is also high level, the first transistor M11～M1NConducting, liquid crystal capacitor CLCiAnd a storage capacitor CSCiThe residual charge in (1) can be passed through the second resistor R2And a third resistor R3Towards ground.
At the same time, the positive control terminal CLK of the second switch tube2The P received signal is low level, and the control terminal CLK is reversed2The signal received by N is high level, the second switch tube K2Turn-off, second switch tube K2Output end VGHThe signal output from the second transistor M is at low level2iAnd the sub-pixels can not be conducted, so that the sub-pixels are in a non-display state.
In addition, when the liquid crystal capacitor CLCiAnd a storage capacitor CSCiAfter all the residual charges in (2) are left, the corresponding residual voltage V is discharged to zero potential.
It will be appreciated that the third period corresponds to a charge removal period within the duty cycle of the flicker drift optimization circuit.
A fourth period in which the trigger signal input terminal VDD has continuously output the high-level trigger signal for a period of time, and the period drives the signal input terminal VGHThe output drive signal is still high.
In the fourth period, the delay trigger signal output by the output terminal VDD _ D of the delay unit is at a high level, and thus, the signal output by the output terminal of the XOR gate XOR is at a low level. At this time, the positive control terminal CLK of the first switch tube1The P received signal is low level, and the control terminal CLK is reversed1The signal received by N is high level, the first switch tube K1Turn-off, first switch tube output end VGHThe signal output from _1is low level, the first transistor M11～M1NNon-conductive liquid crystal capacitor CLCiAnd a storage capacitor CSCiThe residual charge in (2) cannot flow out.
At the same time, the positive control terminal CLK of the second switch tube2P received signal is high level, reverse control terminal CLK2The signal received by N is low level, the second switch tube K2And conducting. Due to the drive signal input terminal VGHThe output driving signal is high level, so the output end V of the second switch tubeGHThe signal outputted from the second transistor M is high level2iAnd conducting, and driving the corresponding sub-pixel to display by the display driving signal output by the source line, namely entering normal display of the picture.
It will be appreciated that the fourth period corresponds to a display control period within the duty cycle of the flicker drift optimization circuit.
Table list of state changes of signals corresponding to different time periods
To make the watchThe contents in the table are clearer and more concise, in the table I, VDD is used for indicating the trigger signal output by the trigger signal input terminal VDD, VDD _ D is used for indicating the delay trigger signal output by the output terminal VDD _ D of the delay unit, and V is used for indicating the delay trigger signal output by the output terminal VDD _ D of the delay unitGHReference drive signal input terminal VGHThe output drive signal is CLK1P and CLK1N respectively denote the positive control terminal CLK of the first switch tube1P and a reverse control terminal CLK1N received signal, using VGH1 and VGH2 respectively denote the output end V of the first switch tubeGH1 and a second switch tube output end VGHSignal of _2 output, and with CLK2P and CLK2N respectively denote the positive control terminal CLK of the second switch tube2P and a reverse control terminal CLK2N received signal. The reference numerals shown in the timing diagram of fig. 3 are the same.
In addition, according to practical situations, the high level trigger signal output from the trigger signal input terminal VDD may be 3.3V, and the driving signal input terminal VGHThe output high level driving signal may be 22V.
Example two
The embodiment provides a flicker drift optimization method, which is applied to the flicker drift optimization circuit provided in the first embodiment, and the flicker drift can be optimized by adopting the flicker drift optimization method.
As described above, referring to fig. 2, the flicker drift optimization circuit may include a trigger module 1, a charge outflow control module 2, and a first switch tube K1And a second switching tube K2(ii) a One duty cycle of the flicker drift optimization circuit is divided into a charge elimination period and a display control period.
Correspondingly, the flicker drift optimization method specifically comprises the following steps:
in the charge elimination period, the trigger module 1 controls the second switch tube K2Turning off to control each sub-pixel not to displayShown in the specification; the trigger module 1 controls the first switch tube K1Is conducted at a drive signal input terminal VGHUnder the action of the input driving signal, the charge outflow control module 2 works to make the residual charges of the capacitors of the sub-pixels flow out.
In the display control time interval, the trigger module 1 controls the second switch tube K2Is conducted at a drive signal input terminal VGHUnder the action of the input driving signal, the second switch tube K2The output end of the pixel outputs a control signal to control the display of each sub-pixel; the trigger module 1 controls the first switch tube K1And turning off the circuit to enable the charge outflow control module 2 not to work.
Compared with the prior art, the advantageous effect of the flicker drift optimization method provided by this embodiment is the same as that of the flicker drift optimization circuit provided by the first embodiment, and details are not repeated here.
First switch tube K in flicker drift optimization circuit1And a second switching tube K2All are transmission gate switches, and the flicker drift optimization circuit comprises a second inverter INV2Correspondingly, the flicker drift optimization method further comprises the following steps:
during the charge elimination period, the output end of the XOR gate is connected to the positive control end CLK of the first switch tube1P outputs a high level signal, a second inverter INV2Inverting the high level signal outputted from the output terminal of the XOR gate, and a second inverter INV2To the reverse control terminal CLK of the first switch tube1N outputs a low level signal, and a first switch tube K1And conducting.
The output end of the XOR gate is connected with the reverse control end CLK of the second switch tube2N output high level signal, second inverter INV2To the positive control terminal CLK of the second switching tube2P outputs low level signal, the second switch tube K2And (6) turning off.
In the display control period, the output end of the XOR gate is connected to the first switch tubePositive control terminal CLK of1P outputs a low level signal, a second inverter INV2Inverting the low level signal outputted from the output terminal of the XOR gate, and a second inverter INV2To the reverse control terminal CLK of the first switch tube1N outputs high level signal, the first switch tube K1And (6) turning off.
The output end of the XOR gate is connected with the reverse control end CLK of the second switch tube2A signal of low level is output from N, and a second inverter INV2To the positive control terminal CLK of the second switching tube2P outputs high level signal, the second switch tube K2And conducting.
EXAMPLE III
The embodiment provides an array substrate, which comprises the flicker drift optimization circuit provided in the first embodiment.
By adopting the array substrate provided by the embodiment, because the flicker drift optimization circuit provided by the first embodiment is included, the outflow of the residual charges in the capacitor can be controlled to eliminate the residual charges in the capacitor before the liquid crystal display is started to display the picture. Therefore, the disturbance of residual charges in the capacitor to the voltage of the common electrode can be avoided, the voltage of the common electrode is prevented from deviating from a standard value, and the phenomenon of flicker drift in a display picture is improved to a great extent.
Example four
The present embodiment provides a display device, which includes the array substrate according to the third embodiment.
By adopting the display device provided by the third embodiment, because the array substrate provided by the third embodiment is included, the charges remaining in the capacitors of the sub-pixels are eliminated before the display device is turned on to display the picture, and the phenomenon of flicker drift in the display picture is improved to a great extent.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims (10)

1. A flicker shift optimization circuit, wherein a duty cycle of the flicker shift optimization circuit is divided into a charge elimination period and a display control period; the flicker drift optimization circuit comprises a trigger module, a charge outflow control module, a first switch tube and a second switch tube; wherein,
the control end of the first switch tube is connected with the output end of the trigger module, the input end of the first switch tube is connected with the driving signal input terminal, and the output end of the first switch tube is connected with the charge outflow control module; the first switch tube is used for: in the charge elimination period, the control circuit is conducted under the control of the trigger module, and under the action of a driving signal input by the driving signal input terminal, the charge outflow control module works to make residual charges in the capacitor of each sub-pixel flow out; in the display control time interval, the display control module is controlled to be switched off so that the charge outflow control module does not work;
the control end of the second switch tube is connected with the output end of the trigger module, and the input end of the second switch tube is connected with the driving signal input terminal; the second switch tube is used for: in the display control time period, the display control circuit is conducted under the control of the trigger module, and under the action of a driving signal input by the driving signal input terminal, the output end of the second switching tube outputs a control signal to control each sub-pixel to display; and in the charge elimination period, the display is switched off under the control of the trigger module, and each sub-pixel is controlled not to display.
2. The flicker drift optimization circuit of claim 1, wherein the trigger block comprises a trigger signal input terminal, a delay unit, and an exclusive or gate; wherein,
the input end of the delay unit is connected with the trigger signal input terminal; the first input end of the exclusive-OR gate is connected with the trigger signal input terminal, the second input end of the exclusive-OR gate is connected with the output end of the delay unit, and the output end of the exclusive-OR gate is connected with the control end of the first switch tube and the control end of the second switch tube.
3. The flicker drift optimization circuit of claim 2, wherein the delay cell comprises 2M first inverters, wherein M is an integer greater than or equal to 1.
4. The flicker drift optimization circuit of claim 2, wherein the first switching tube and the second switching tube are transmission gate switches; the flicker drift optimization circuit further comprises a second inverter; the output end of the exclusive-or gate is respectively connected with the forward control end of the first switch tube, the reverse control end of the second switch tube and the input end of the second phase inverter, and the output end of the second phase inverter is respectively connected with the reverse control end of the first switch tube and the forward control end of the second switch tube.
5. The flicker drift optimization circuit according to claim 1, wherein the charge outflow control module comprises a plurality of first transistors corresponding to the capacitors in the sub-pixels, the gates of the first transistors are connected to the output terminal of the first switching tube through a first resistor, the drains of the first transistors are connected to the ground terminal through a second resistor, and the sources of the first transistors are connected to the capacitors in the corresponding sub-pixels.
6. The flicker shift optimization circuit according to claim 5, wherein the capacitor of each sub-pixel comprises a liquid crystal capacitor and a storage capacitor, and the liquid crystal capacitor and the storage capacitor are respectively connected to the ground terminal through a third resistor; one end of the third resistor is connected with the first pole plate of the parasitic capacitor, and the other end of the third resistor is connected with the second pole plate of the parasitic capacitor.
7. A flicker drift optimization method is characterized in that the method is applied to a flicker drift optimization circuit to optimize flicker drift; the flicker drift optimization circuit comprises a trigger module, a charge outflow control module, a first switch tube and a second switch tube; one working cycle of the flicker drift optimization circuit is divided into a charge elimination period and a display control period; the flicker drift optimization method comprises the following steps:
in the charge elimination period, the triggering module controls the second switching tube to be switched off and controls each sub-pixel not to display; the trigger module controls the first switch tube to be conducted, and under the action of a driving signal input by the driving signal input terminal, the charge outflow control module works to make residual charges of the capacitor of each sub-pixel flow out;
in the display control time period, the trigger module controls the second switch tube to be conducted, and under the action of a driving signal input by the driving signal input terminal, the output end of the second switch tube outputs a control signal to control each sub-pixel to display; the triggering module controls the first switch tube to be switched off, so that the charge outflow control module does not work.
8. The flicker drift optimization method according to claim 7, wherein the flicker drift optimization circuit further comprises a second inverter, and the first switch tube and the second switch tube are transmission gate switches; the flicker drift optimization method further comprises:
in the charge elimination period, the output end of the exclusive-or gate outputs a high-level signal to the forward control end of the first switch tube, the second phase inverter inverts the high-level signal output by the output end of the exclusive-or gate, the output end of the second phase inverter outputs a low-level signal to the reverse control end of the first switch tube, and the first switch tube is turned on;
the output end of the exclusive-or gate outputs a high-level signal to the reverse control end of the second switching tube, the output end of the second phase inverter outputs a low-level signal to the forward control end of the second switching tube, and the second switching tube is turned off;
in the display control period, the output end of the exclusive or gate outputs a low-level signal to the forward control end of the first switch tube, the second phase inverter inverts the low-level signal output by the output end of the exclusive or gate, the output end of the second phase inverter outputs a high-level signal to the reverse control end of the first switch tube, and the first switch tube is turned off;
the output end of the exclusive-or gate outputs a low-level signal to the reverse control end of the second switch tube, the output end of the second phase inverter outputs a high-level signal to the forward control end of the second switch tube, and the second switch tube is conducted.
9. An array substrate comprising the scintillation drift optimization circuit of any one of claims 1 to 6.
10. A display device comprising the array substrate according to claim 9.
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