CN106685561B - A kind of the bit synchronous mapping treatment method and device of band filtering - Google Patents
A kind of the bit synchronous mapping treatment method and device of band filtering Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
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Abstract
The invention discloses a kind of bit synchronous mapping treatment methods of band filtering, comprising: obtains system clock number Pserver value according to frame boundaries value, the corresponding Pserver value of preceding k frame is sequentially stored into mean filter, obtains mean value Pserver_average；Differentiate whether currently available mean value Pserver_average exceeds the tolerance of standard denominator value, if exceeded, currently available mean value Pserver_average is then replaced with the standard denominator value, using the mean value Pserver_average as denominator, the number for the ODUk frame notch that will test is as molecule, according to integral/differential rule mapping output ODUk frame notch.The present invention further simultaneously discloses a kind of bit synchronous mapping processing unit of band filtering.
Description
Technical Field
The invention relates to the field of Optical Transport Network (OTN) transmission chip communication, in particular to a Bit-Synchronous Mapping (BMP) processing method and device with filtering.
Background
For the chip of the OTN mapping frame class, the BMP is an important mapping method. The BMP mapping method can follow the service rate of the client side, but when the BMP follows the service rate of the client side, the service rate of the client side may be jittered, so how to better overcome the service rate jitter of the client side and output a service layer signal meeting the frequency offset requirement specified by a protocol is a problem to be solved.
At present, the jitter of the service rate of the client side can be overcome by adopting a method which completely follows the service rate of the client side, and the method can meet the requirement for the services which are encapsulated by a Generic Framing Procedure (GFP); but performs poorly for traffic that has not undergone GFP encapsulation. Alternatively, a fixed step fit is used for following, but this method is slow in following and also introduces low frequency jitter.
For some services, such as Synchronous Digital Hierarchy (SDH), Fibre Channel (FC), Infiniband (IB), Common Public Radio Interface (CPRI), etc., when they are directly mapped to an optical Channel Data Unit (ODU) in a BMP manner, the jitter of the service rate at the client side is a challenge to the mapping module, so that a specific method is adopted to reduce the jitter of the service rate at the client side, which is of great significance for improving the performance of the mapping chip and recovering the clock of the chip.
Disclosure of Invention
In view of this, embodiments of the present invention are expected to provide a bit synchronization mapping processing method and apparatus with filtering, so that the rate of an ODUk frame can accurately follow a client service within a certain range, and jitter of the service rate of the client is reduced, thereby ensuring that the rate of the output ODUk frame conforms to a protocol specification.
In order to achieve the above purpose, the technical solution of the embodiment of the present invention is realized as follows:
the embodiment of the invention provides a bit synchronization mapping processing method with filtering, which comprises the following steps: obtaining the number Pserver values of the system clocks according to the frame boundary value, and sequentially storing the Pserver values corresponding to the previous k frames into a mean value filter to obtain a mean value Pserver _ average;
judging whether the currently obtained mean value Pserver _ average exceeds the tolerance range of the standard denominator value, if so, replacing the currently obtained mean value Pserver _ average with the standard denominator value, taking the mean value Pserver _ average as a denominator, taking the number of the detected ODUk frame gaps as a numerator, and mapping and outputting the ODUk frame gaps according to an integral/differential rule.
In the foregoing scheme, the obtaining a Pserver value according to a frame boundary value includes: and taking the number of client service gaps corresponding to the payload of one ODUk frame as a frame boundary value, and counting the number of corresponding system clocks according to the frame boundary value to obtain a Pserver value.
In the above scheme, the standard denominator value is a standard self-oscillation denominator obtained when the output frequency offset is 0 ppm.
In the above scheme, a frequency offset detection circuit is adopted to determine whether the currently obtained mean value Pserver _ average exceeds the tolerance range of the standard denominator value.
The embodiment of the invention also provides a bit synchronization mapping processing device with filtering, which comprises:
the acquisition module is used for acquiring the number Pserver values of the system clocks according to the frame boundary value, and sequentially storing the Pserver values corresponding to the previous k frames into the mean value filter to obtain a mean value Pserver _ average;
the judging module is used for judging whether the currently obtained average value Pserver _ average exceeds the tolerance range of the standard denominator value;
the replacing module is used for replacing the currently obtained mean value Pserver _ average with the standard denominator value when the judging module judges and determines that the tolerance range of the standard denominator value is exceeded;
and the mapping output module is used for mapping and outputting the ODUk frame gap according to an integral/differential rule by taking the average value Pserver _ average as a denominator and the number of the detected ODUk frame gaps as a numerator.
In the foregoing scheme, the obtaining, by the obtaining module, a Pserver value according to a frame boundary value includes: and taking the number of client service gaps corresponding to the payload of one ODUk frame as a frame boundary value, and counting the number of corresponding system clocks according to the frame boundary value to obtain a Pserver value.
In the above scheme, the standard denominator value is a standard self-oscillation denominator obtained when the output frequency offset is 0 ppm.
In the above scheme, a frequency offset detection circuit is adopted to determine whether the currently obtained mean value Pserver _ average exceeds the tolerance range of the standard denominator value.
According to the bit synchronization mapping processing method and device with filtering, provided by the embodiment of the invention, the number Pserver values of the system clocks are obtained according to the frame boundary value, and the Pserver values corresponding to the previous k frames are sequentially stored in a mean filter to obtain a mean value Pserver _ average; judging whether the currently obtained mean value Pserver _ average exceeds the tolerance range of the standard denominator value, if so, replacing the currently obtained mean value Pserver _ average with the standard denominator value, taking the mean value Pserver _ average as a denominator, taking the number of the detected ODUk frame gaps as numerators, and mapping and outputting the ODUk frame gaps according to an integral/differential (sigma/delta) rule. Therefore, the output ODUk frame gap can follow the client side service in the range meeting the frequency offset requirement, and the jitter of the service rate of the client side can be eliminated to the maximum extent, so that the rate of the output ODUk frame is ensured not to exceed the frequency offset requirement specified by the protocol.
Drawings
Fig. 1 is a schematic flow chart of an implementation of a bit synchronization mapping processing method with filtering according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a flow chart of implementing a k-order mean filter according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a filtering bit synchronization mapping processing apparatus according to an embodiment of the present invention.
Detailed Description
So that the manner in which the features and aspects of the embodiments of the present invention can be understood in detail, a more particular description of the embodiments of the invention, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the appended drawings.
As shown in fig. 1, the implementation procedure of the bit synchronization mapping processing method with filtering according to the embodiment of the present invention includes the following steps:
step 101: obtaining the number Pserver values of the system clocks according to the frame boundary value, and sequentially storing the Pserver values corresponding to the previous k frames into a mean value filter to obtain a mean value Pserver _ average;
the obtaining of the system clock number Pserver value according to the frame boundary value specifically includes: and taking the number of client service gaps corresponding to the payload of one ODUk frame as a frame boundary value, and counting the number of corresponding system clocks according to the frame boundary value to obtain a Pserver value.
Here, k in the ODUk indicates a level of the ODU, and a value of k may be 0, 1, 2e, 3, and 4, and at present, an ODU1, an ODU2, and an ODU3 have been defined in a protocol.
Step 102: judging whether the currently obtained mean value Pserver _ average exceeds the tolerance range of the standard denominator value, if so, executing step 103, otherwise, executing step 104;
judging whether the currently obtained mean value Pserver _ average exceeds the tolerance range of the standard denominator value by using a frequency offset detection circuit; the standard denominator value is a standard self-oscillation denominator obtained when the output frequency offset is 0 ppm.
Step 103: and replacing the currently obtained mean value Pserver _ average with the standard denominator value.
Step 104: and mapping and outputting the ODUk frame gap according to an integral/differential rule by taking the average value Pserver _ average as a denominator and the number of the detected ODUk frame gaps as a numerator.
The step 101 in fig. 1 sequentially stores the Pserver values corresponding to the previous k frames into an average filter, where the average filter may be implemented by using a k-order average filter, and a flow of implementing filtering by using the k-order average filter in the embodiment of the present invention is shown in fig. 2, where the specific implementation process is as follows:
and (3) comparing the Pserver value corresponding to the previous k frames: pserver0 and Pserver1.. the Pserver (k-1) is sequentially stored in a mean filter, the mean value Pserver _ average is sequentially output, and the remainder Pserver _ remaining after the mean value is obtained is stored; the value range of k can be any natural number.
Here, when a new frame Pserver (k) is generated, since the capacity of the averaging filter is k frames, Pserver0 is removed from the averaging filter, Pserver (k) is shifted in, the average value is continuously averaged by adding the previous Pserver _ remaining value, and then the output average value Pserver _ average and remainder Pserver _ remaining are updated.
Because the obtained mean value Pserver _ average is influenced by the first k Pserver values, the jitter of the first k Pserver values is smoothed, and each mean value Pserver _ average is updated, so that the continuity of the Pserver values is ensured, and meanwhile, the existence of the remainder Pserver _ remaining ensures that the calculation of the Pserver values is not lost quantitatively.
In practical applications, when special cases are encountered, for example: when the customer service rate has a large frequency offset due to a line fault, an alarm, etc., the ODUk frame gap mapped and output in step 104 in fig. 1 may exceed the frequency offset range specified by the protocol in terms of rate, and at this time, the ODUk frame gap cannot be directly output and must be discriminated by a frequency offset detection circuit to output an ODUk frame gap meeting the requirement of the protocol frequency offset.
The following further details how to determine the obtained mean value Pserver _ average through a frequency offset detection circuit according to the embodiments of the present invention:
firstly, taking the number of ODUk frame gaps (for example, the bit width of an ODUk frame is 32bit, and the number of ODUk frame gaps corresponding thereto is 3824) as a numerator, and using a formula when the output frequency offset is 0 ppm: calculating a standard self-oscillation denominator from the rate of 0ppm self-oscillation denominator (bit width 3824/ODUk frame) of the system clock;
here, the ODUk frame gap is reflected to a certain extent and affects the rate of the ODUk frame, and a larger ODUk frame gap indicates a smaller ODUk frame rate, and vice versa.
Secondly, comparing each obtained mean value Pserver _ average with the self-oscillation denominator of the standard, when the current obtained mean value Pserver _ average exceeds the tolerance range of the standard denominator value, considering that the ODUk frame gap generated by the current obtained mean value Pserver _ average will exceed the frequency offset meeting the protocol specification, replacing the current obtained mean value Pserver _ average with the standard denominator value, and outputting the ODUk frame gap without the frequency offset.
Here, the protocol-compliant frequency offset may be a 100ppm frequency offset; however, in the detection of this super-frequency offset, it is particularly critical how to determine the tolerance range of the standard denominator value. The tolerance range of the standard denominator value determines the precision of frequency deviation detection, and since the standard denominator value calculated according to the above formula is not necessarily an integer, the numerator denominator needs to be amplified simultaneously according to the proportion, and the frame boundary is also amplified by the same factor.
The tolerance range of the standard denominator value is set by a user, and depends on the frequency offset corresponding to one more system clock or one less system clock, the mean value Pserver _ average calculated by the mean filter, the standard denominator value and the frequency offset 100ppm meeting the protocol specification.
For example, if the frequency offset corresponding to each one or less system clock is 2.8ppm, the frequency offset is considered to exceed 100ppm as specified by the protocol when the mean value Pserver _ average calculated by the mean filter is greater than the standard denominator value or exceeds 35 system clocks. At this time, the frequency offset corresponding to 35 system clocks is 2.8 × 35 to 98ppm, and the frequency offset corresponding to 36 system clocks is 2.8 × 36 to 100.8ppm, and since 100.8ppm exceeds 100ppm, and 98ppm does not exceed 100ppm, the tolerance range of the standard denominator value in this case is 35 system clocks.
How to improve the accuracy of frequency offset detection according to the present invention is further described in detail with a specific embodiment.
In this embodiment of the present invention, assuming that a system clock is 360M, a bit width corresponding to a client side service output ODUk frame gap is 32bit, the system clock is mapped into the ODU0 in a BMP mapping manner, a rate of the ODU0 is 1.24416G, and a standard denominator value at this time is 3824 × 360 × 32/(1000 × 1.24416) ═ 35407.407, that is: there are approximately 35407 system clocks for each frame of ODU0 at 360M clocks.
According to sigma/delta rule, 3824 is used as a numerator, 35407 is used as a denominator, and the ODUk frame gap is followed by the client side service output, and at this time, the frequency offset corresponding to one more or one less system clock is 28.24 ppm. Obviously, such a following is too "coarse"; at this time, the numerator and denominator are simultaneously amplified by 10 times, the frame boundary is also amplified by 10 times, and the Pserver value corresponding to the filter input is correspondingly increased (the Pserver value is increased by increasing the number k of Pserver (k)), so that the frequency offset corresponding to each more or less system clock is 2.8 ppm. The method realizes the improvement of the detection precision of the frequency deviation by amplifying the numerator and the denominator (the period of sampling the denominator).
Here, it belongs to the prior art how to calculate the ODUk frame gap of the client side service output according to the sigma/delta rule, and details are not described here.
Through the above processing, the output ODUk frame gap follows the client side service in the range meeting the frequency offset requirement, and the jitter of the client side service is eliminated to the greatest extent. When the service layer signal of the client is super-frequency offset, the ODUk signal meeting the frequency offset requirement can be output. Compared with the existing BMP circuit, the jitter can be better removed by increasing the value of the filter k, and meanwhile, the high-precision frequency offset detection ensures the requirement of the output frequency offset.
In order to implement the foregoing method, an embodiment of the present invention further provides a bit synchronization mapping processing apparatus with filtering, as shown in fig. 3, the apparatus includes an obtaining module 31, a determining module 32, a replacing module 33, and a mapping output module 34; wherein,
the obtaining module 31 is configured to obtain the number Pserver values of the system clocks according to the frame boundary value, and sequentially store the Pserver values corresponding to the previous k frames in the mean filter to obtain a mean value Pserver _ average;
a judging module 32, configured to judge whether the currently obtained mean value Pserver _ average exceeds a tolerance range of the standard denominator value;
a replacing module 33, configured to replace the currently obtained mean value Pserver _ average with the standard denominator value when the judging module 32 judges and determines that the tolerance range of the standard denominator value is exceeded;
and a mapping output module 34, configured to map and output the ODUk frame gap according to an integral/differential rule, where the mean value Pserver _ average is used as a denominator, and the number of detected ODUk frame gaps is used as a numerator.
Here, the obtaining module 31 obtains the Pserver value according to the frame boundary value, and includes: and taking the number of client service gaps corresponding to the payload of one ODUk frame as a frame boundary value, and counting the number of corresponding system clocks according to the frame boundary value to obtain a Pserver value.
Here, a frequency offset detection circuit is used to judge whether the currently obtained mean value Pserver _ average exceeds the tolerance range of the standard denominator value.
Wherein, the standard denominator value is a standard self-oscillation denominator obtained when the output frequency offset is 0 ppm.
In practical applications, the obtaining module 31, the judging module 32, the replacing module 33, and the mapping output module 34 may be implemented by a Central Processing Unit (CPU), a microprocessor Unit (MPU), a Digital Signal Processor (DSP), a Field Programmable Gate Array (FPGA), or the like on a mapping chip with filtering.
Acquiring a Pserver value according to a frame boundary value, and sequentially storing the Pserver value corresponding to a previous k frame into a mean filter to obtain a mean Pserver _ average; judging whether the currently obtained mean value Pserver _ average exceeds the tolerance range of the standard denominator value, if so, replacing the currently obtained mean value Pserver _ average with the standard denominator value, taking the mean value Pserver _ average as a denominator, taking the number of the detected ODUk frame gaps as numerators, and mapping and outputting the ODUk frame gaps according to a sigma/delta rule. Therefore, the output ODUk frame gap can follow the client side service in the range meeting the frequency offset requirement, and the jitter of the client service rate can be eliminated to the maximum extent, so that the output ODUk frame rate is ensured not to exceed the frequency offset requirement specified by the protocol.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, and any modifications, equivalents, improvements, etc. that are within the spirit and principle of the present invention should be included in the present invention.
Claims (6)
1. A bit synchronization mapping processing method with filtering, the method comprising:
obtaining the number Pserver values of the system clocks according to the frame boundary value, and sequentially storing the Pserver values corresponding to the previous k frames into a mean value filter to obtain a mean value Pserver _ average, wherein k is a natural number;
judging whether the currently obtained mean value Pserver _ average exceeds the tolerance range of a standard denominator value, if so, replacing the currently obtained mean value Pserver _ average with the standard denominator value, taking the mean value Pserver _ average as a denominator, taking the number of the detected ODUk frame gaps as a numerator, and mapping and outputting the ODUk frame gaps according to an integral-differential rule;
wherein, the frame boundary value refers to the number of client service gaps corresponding to an ODUk frame payload;
the standard denominator value is a standard self-oscillation denominator obtained when the output frequency offset is 0ppm, where the self-oscillation denominator is the system clock × bit width of the ODUk frame × number of ODUk frame gaps ÷ rate of the ODUk frame.
2. The method of claim 1, wherein obtaining the Pserver value according to the frame boundary value comprises: and counting the number of corresponding system clocks according to the frame boundary value to obtain a Pserver value.
3. The method of claim 1, wherein a frequency offset detection circuit is used to determine whether the current mean value Pserver _ average exceeds a tolerance range of a standard denominator value.
4. A filtered bit synchronization map processing apparatus, the apparatus comprising:
the acquisition module is used for acquiring the number Pserver values of the system clocks according to the frame boundary value, and sequentially storing the Pserver values corresponding to the previous k frames into the mean filter to obtain a mean value Pserver _ average, wherein k is a natural number;
the judging module is used for judging whether the currently obtained average value Pserver _ average exceeds the tolerance range of the standard denominator value;
the replacing module is used for replacing the currently obtained mean value Pserver _ average with the standard denominator value when the judging module judges and determines that the tolerance range of the standard denominator value is exceeded;
a mapping output module, configured to map and output the ODUk frame gap according to an integral-differential rule, where the average value Pserver _ average is used as a denominator, and the number of detected ODUk frame gaps is used as a numerator;
wherein, the frame boundary value refers to the number of client service gaps corresponding to an ODUk frame payload;
the standard denominator value is a standard self-oscillation denominator obtained when the output frequency offset is 0ppm, where the self-oscillation denominator is the system clock × bit width of the ODUk frame × number of ODUk frame gaps ÷ rate of the ODUk frame.
5. The apparatus of claim 4, wherein the obtaining module obtains the Pserver value according to the frame boundary value, and comprises: and counting the number of corresponding system clocks according to the frame boundary value to obtain a Pserver value.
6. The apparatus of claim 4, wherein a frequency offset detection circuit is employed to determine whether the currently obtained mean value Pserver _ average exceeds a tolerance range of a standard denominator value.
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| CN201510761157.0A CN106685561B (en) | 2015-11-10 | 2015-11-10 | A kind of the bit synchronous mapping treatment method and device of band filtering |
| PCT/CN2016/103513 WO2017080361A1 (en) | 2015-11-10 | 2016-10-27 | Bit-synchronous mapping processing method and apparatus for band filtering, and computer storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1968063A (en) * | 2006-10-26 | 2007-05-23 | 华为技术有限公司 | Clock recovery method and apparatus |
| CN101547055A (en) * | 2009-04-25 | 2009-09-30 | 华为技术有限公司 | Method and device for transmitting data in optical transfer network |
| CN103731223A (en) * | 2012-10-16 | 2014-04-16 | 中兴通讯股份有限公司 | Method and device for recovering clock |
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| JP3570507B2 (en) * | 2001-03-28 | 2004-09-29 | 日本電気株式会社 | STM mapping circuit and method |
| CN101651512B (en) * | 2009-09-24 | 2013-06-05 | 中兴通讯股份有限公司 | Method, system and device for realizing transparent transmission of data traffic |
| WO2014013602A1 (en) * | 2012-07-20 | 2014-01-23 | 富士通株式会社 | Transmission device |
| EP2747318B1 (en) * | 2012-12-19 | 2015-03-25 | Alcatel Lucent | Method and apparatus for transmitting signals in an optical transport network |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1968063A (en) * | 2006-10-26 | 2007-05-23 | 华为技术有限公司 | Clock recovery method and apparatus |
| CN101547055A (en) * | 2009-04-25 | 2009-09-30 | 华为技术有限公司 | Method and device for transmitting data in optical transfer network |
| CN103731223A (en) * | 2012-10-16 | 2014-04-16 | 中兴通讯股份有限公司 | Method and device for recovering clock |
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Application publication date: 20170517 Assignee: Xi'an Chris Semiconductor Technology Co. Ltd. Assignor: SHENZHEN ZTE MICROELECTRONICS TECHNOLOGY CO., LTD. Contract record no.: 2019440020036 Denomination of invention: Method and apparatus for processing Bit-synchronous mapping for band filtering Granted publication date: 20181204 License type: Common License Record date: 20190619 |