CN105515749B - A kind of method and system for realizing clock transparent transmission during asynchronous mapping - Google Patents
A kind of method and system for realizing clock transparent transmission during asynchronous mapping Download PDFInfo
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Abstract
The method that the invention discloses a kind of to realize clock transparent transmission during asynchronous mapping, is applied to AMP demapping device, comprising: is divided to obtain ODU2 signaling protein14-3-3 clock to OTU2 signaling protein14-3-3 clock according to the Rate Relationship of ODU2 signal and OTU2 signal；The Rate Relationship that ODU1 and ODU2 are determined according to the JC value extracted from ODU2 signal is divided to obtain the recovered clock of ODU1 according to recovered clock of the Rate Relationship to ODU2；The Rate Relationship that STMk signal Yu ODU1 signal are determined according to the JC value extracted from ODU1 signal is divided to obtain STMk signaling protein14-3-3 clock according to recovered clock of the Rate Relationship to ODU1.The reference clock frequency that the present invention enables to demapping end to restore client traffic data follows directly after the clock frequency of original client business datum.The invention also discloses corresponding systems.
Description
Technical field
The present invention relates to technical field of photo communication, more particularly to one kind to realize clock transparent transmission during asynchronous mapping
Method and system.
Background technique
As shown in Figure 1, transmission device of today not only needs the data of transmission services itself, while being also required to transmission characterization
The clock information of traffic data rate enables to the business of the whole network to keep clock synchronous in this way.Clock transparent transmission refers to be passed in downstream
When light sending port (sending the port of business to client) on transfer device (demapping end) is used to send the reference of business datum
Clock frequency can follow the clock of light-receiving port (port for receiving client traffic) business of upstream transmission equipment (mapping end)
Frequency.
It, can be using the adjustment in business mapping related in ITU-T G.709/Y.1331 agreement in order to realize clock transparent transmission
Control JC, Cm (t), Cn (t) and CnD (t) parameter.The value of these parameters has reacted the rate information of business, i.e. clock information.
Wherein JC value is used for asynchronous mapping process (Asynchronous Mapping Procedure, AMP), and JC value is that AMP is mapped into
The parameter of the former service rate information of the reflection generated in journey, and Cm (t), Cn (t) and CnD (t) value are used for general mapping process
(Generic Mapping Procedure, GMP).At the mapping end of upstream, client traffic is being mapped to low order ODUk
(Optical channel Data Unit, Optical Channel Data Unit-k) and the process mapped from low order ODUk to high-order ODUK
In, mapping block generates these values, and is inserted into expense, and is transmitted to downstream with ODUk.
GMP is mapped, G.709/Y.1331 ITU-T defines how to obtain using Cm (t), Cn (t) and CnD (t) value
Transmission clock, i.e. the demapping port in downstream, De-mapping module extract Cm (t) and CnD (t) from expense, then calculate
To Cn (t).This transparent transmission mode separately handles data path and clock path, does not interfere with each other.
AMP is mapped, G.709/Y.1331 ITU-T but there is no definition of how to obtain the side of transmission clock using JC value
Method.And in the related technology, a kind of clock frequency being recovered former business using JC value is achieved in that: at demapping end, being made
Enabled with writing for JC value control sending side FIFO, so that the water level to FIFO is adjusted, and the water level of FIFO can be to outside
The centre frequency of LVCO (low pass voltage controlled oscillator) device carries out fine tuning up and down, so that tranmitting data register follows reception clock.
This mode is not substantially real clock transparent transmission, because there is no real clock paths for this mode, it is to borrow
The centre frequency of external LVCO device is just able to achieve time clock tracking, be it is a kind of follow rather than follow directly after indirectly, and this reality
The higher cost of existing mode.
Therefore, how under conditions of not adding any external devices, original is recovered using JC value in AMP mapping process
The clock frequency of business is problem to be solved.
Summary of the invention
The method that technical problem to be solved by the invention is to provide a kind of to realize clock transparent transmission during asynchronous mapping
And system, the reference clock frequency for enabling to demapping end to restore client traffic data follow directly after original client business datum
Clock frequency.
In order to solve the above-mentioned technical problems, the present invention provides a kind of during asynchronous mapping realizes the side of clock transparent transmission
Method is applied to asynchronous mapping process AMP demapping device, this method comprises:
According to the optical channel transmission unit OTU2 signal of Optical Channel Data Unit-k ODU2 signal and the carrying ODU2 signal
Rate Relationship OTU2 signaling protein14-3-3 clock CLK_OTU2_REC is divided to obtain the ODU2 signaling protein14-3-3 clock
CLK_ODU2_REC；
Determined according to the JC value extracted from ODU2 signal overhead be mapped to the ODU1 signal of the ODU2 signal with it is described
The Rate Relationship of ODU2 signal divides the ODU2 signaling protein14-3-3 clock CLK_ODU2_REC according to the Rate Relationship
Frequency obtains the ODU1 signaling protein14-3-3 clock CLK_ODU1_REC；
Determined according to the JC value extracted from ODU1 signal overhead be mapped to the STMk signal of the ODU1 signal with it is described
The Rate Relationship of ODU1 signal divides the ODU1 signaling protein14-3-3 clock CLK_ODU1_REC according to the Rate Relationship
Frequency obtains the STMk signaling protein14-3-3 clock CLK_STMk_REC.
Further, this method further includes following features:
OTU2 signaling protein14-3-3 clock CLK_OTU2_REC is carried out according to the Rate Relationship of ODU2 signal and OTU2 signal
Frequency dividing obtains the ODU2 signaling protein14-3-3 clock CLK_ODU2_REC, comprising:
CLK_ODU2_REC=k1*CLK_OTU2_REC；
Wherein, 239/255 k1.
Further, this method further includes following features:
When the bit wide that the bit wide of ODU1 signal is 16bit and ODU2 signal is 64bit, according to the Rate Relationship to institute
ODU2 signaling protein14-3-3 clock CLK_ODU2_REC is stated to be divided to obtain the ODU1 signaling protein14-3-3 clock CLK_ODU1_
REC, comprising:
CLK_ODU1_REC=((7616-JC/2)/7648) * CLK_ODU2_REC；
Wherein, the frequency of CLK_ODU1_REC is adjusted by accumulation JC value, comprising: whenever the frame or multiframe received
The cumulative JC of JC value entrained by ODU2 signalAccumulationReach one word of positive adjustment or negative sense adjusts a word, then CLK_ODU1_
The frequency of REC adjusts a unit, then JCAccumulationIt resets, JC value restarts to accumulate after new ODU2 signal frame arrives.
Further, this method further includes following features:
When STMk signal is STM16 signal, and the bit wide of ODU1 signal and STM16 signal is all 16bit, according to described
When Rate Relationship is divided to obtain the STM16 signaling protein14-3-3 to the ODU1 signaling protein14-3-3 clock CLK_ODU1_REC
Clock CLK_STM16_REC, comprising:
CLK_STM16_REC=((7616-JC/2)/7648) * CLK_ODU1_REC；
Wherein, the frequency of CLK_STM16_REC is adjusted by accumulation JC value, comprising: whenever the frame that receives or more
The cumulative JC of JC value entrained by frame ODU1 signalAccumulationReach one word of positive adjustment or negative sense adjusts a word, then CLK_
The frequency of STM16_REC adjusts a unit, then JCAccumulationIt resets, JC value restarts to accumulate after new ODU1 signal frame arrives
It is tired.
Further, this method further includes following features:
The ODU1 signaling protein14-3-3 clock CLK_ODU1_REC is divided to obtain according to the Rate Relationship described
After STMk signaling protein14-3-3 clock CLK_STMk_REC, further includes:
The duty ratio of the STMk signaling protein14-3-3 clock CLK_STMk_REC is adjusted to 50%.
In order to solve the above-mentioned technical problem, the present invention also provides a kind of realizes clock transparent transmission during asynchronous mapping
System is applied to asynchronous mapping process AMP demapping device, comprising:
ODU2 recovering clock signals module, for according to Optical Channel Data Unit-k ODU2 signal and the carrying ODU2 signal
The Rate Relationship of optical channel transmission unit OTU2 signal OTU2 signaling protein14-3-3 clock CLK_OTU2_REC divide
To the ODU2 signaling protein14-3-3 clock CLK_ODU2_REC；
ODU1 recovering clock signals module, described in being mapped to according to the JC value extracted from ODU2 signal overhead is determining
The Rate Relationship of the ODU1 signal of ODU2 signal and the ODU2 signal, according to the Rate Relationship to the extensive of the ODU2 signal
Multiple clock CLK_ODU2_REC is divided to obtain the ODU1 signaling protein14-3-3 clock CLK_ODU1_REC；
STMk recovering clock signals module, described in being mapped to according to the JC value extracted from ODU1 signal overhead is determining
The Rate Relationship of the STMk signal of ODU1 signal and the ODU1 signal, according to the Rate Relationship to the extensive of the ODU1 signal
Multiple clock CLK_ODU1_REC is divided to obtain the STMk signaling protein14-3-3 clock CLK_STMk_REC.
Further, which further includes following features:
ODU2 recovering clock signals module, for the Rate Relationship according to ODU2 signal and OTU2 signal to OTU2 signal
Recovered clock CLK_OTU2_REC is divided to obtain the ODU2 signaling protein14-3-3 clock CLK_ODU2_REC, comprising:
CLK_ODU2_REC=k1*CLK_OTU2_REC；
Wherein, 239/255 k1.
Further, which further includes following features:
ODU1 recovering clock signals module, the bit wide for working as ODU1 signal are that the bit wide of 16bit and ODU2 signal is
When 64bit, the ODU2 signaling protein14-3-3 clock CLK_ODU2_REC is divided to obtain according to the Rate Relationship described
ODU1 signaling protein14-3-3 clock CLK_ODU1_REC, comprising:
CLK_ODU1_REC=((7616-JC/2)/7648) * CLK_ODU2_REC；
Wherein, the frequency of CLK_ODU1_REC is adjusted by accumulation JC value, comprising: whenever the frame or multiframe received
The cumulative JC of JC value entrained by ODU2 signalAccumulationReach one word of positive adjustment or negative sense adjusts a word, then CLK_ODU1_
The frequency of REC adjusts a unit, then JCAccumulationIt resets, JC value restarts to accumulate after new ODU2 signal frame arrives.
Further, which further includes following features:
STMk recovering clock signals module, for working as STMk signal for STM16 signal, and ODU1 signal and STM16 signal
Bit wide when being all 16bit, the ODU1 signaling protein14-3-3 clock CLK_ODU1_REC is divided according to the Rate Relationship
Frequency obtains the STM16 signaling protein14-3-3 clock CLK_STM16_REC, comprising:
CLK_STM16_REC=((7616-JC/2)/7648) * CLK_ODU1_REC；
Wherein, the frequency of CLK_STM16_REC is adjusted by accumulation JC value, comprising: whenever the frame that receives or more
The cumulative JC of JC value entrained by frame ODU1 signalAccumulationReach one word of positive adjustment or negative sense adjusts a word, then CLK_
The frequency of STM16_REC adjusts a unit, then JCAccumulationIt resets, JC value restarts to accumulate after new ODU1 signal frame arrives
It is tired.
Further, which further includes following features:
STMk recovering clock signals module is also used to according to the Rate Relationship to the ODU1 signaling protein14-3-3 clock
CLK_ODU1_REC is divided after obtaining the STMk signaling protein14-3-3 clock CLK_STMk_REC, by the STMk signal
The duty ratio of recovered clock CLK_STMk_REC is adjusted to 50%.
Compared with prior art, it is provided by the invention it is a kind of during asynchronous mapping realize clock transparent transmission method and be
System passes through one under OTU2 signaling protein14-3-3 clock domain according to the principle of the rule of AMP mapping and JC adjustment rate variance
Serial scaling down processing obtains the reference clock frequency for restoring client traffic data, and demapping end is enabled to restore client's industry
The reference clock frequency of business data follows directly after the clock frequency of original client business datum.
Detailed description of the invention
Fig. 1 is the schematic diagram at transmission device in the prior art (including mapping end and demapping end).
Fig. 2 is a kind of flow chart of method that clock transparent transmission is realized during asynchronous mapping of the embodiment of the present invention.
Fig. 3 is a kind of structural representation of system that clock transparent transmission is realized during asynchronous mapping of the embodiment of the present invention
Figure.
Fig. 4 is relation schematic diagram of the present invention using the corresponding recovered clock of communication unit each in example.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached drawing to the present invention
Embodiment be described in detail.It should be noted that in the absence of conflict, in the embodiment and embodiment in the application
Feature can mutual any combination.
STM16 to ODU1 is being carried out, when the AMP of ODU1 to ODU2 maps, discovery JC value also can be according in GMP mapping process
The mode of similar Cm (t), Cn (t) and CnD (t) realize clock transparent transmission.Multi-service convergence plate can not have to by any outer in this way
Portion's device realizes clock transparent transmission, reduces cost.Wherein, OTUk is optical channel transmission unit (Optical channel
Transport Unit), k indicates speed grade；ODUk is Optical Channel Data Unit-k (Optical channel Data
Unit), k indicates speed grade；STMk is synchronous transfer mode (Synchronous Transfer Module), and k indicates rate
Grade, STM16 are the business that a kind of rate is 155.52*16 (Mbps).
As shown in Figure 1, the method that the embodiment of the invention provides a kind of to realize clock transparent transmission during asynchronous mapping, is answered
For asynchronous mapping process AMP demapping device, this method comprises:
S10, according to the optical channel transmission unit OTU2 of Optical Channel Data Unit-k ODU2 signal and the carrying ODU2 signal
The Rate Relationship of signal is divided to obtain the ODU2 signaling protein14-3-3 to OTU2 signaling protein14-3-3 clock CLK_OTU2_REC
Clock CLK_ODU2_REC；
S20, determined according to the JC value extracted from ODU2 signal overhead be mapped to the ODU1 signal of the ODU2 signal with
The Rate Relationship of the ODU2 signal, according to the Rate Relationship to the ODU2 signaling protein14-3-3 clock CLK_ODU2_REC into
Row frequency dividing obtains the ODU1 signaling protein14-3-3 clock CLK_ODU1_REC；
S30, determined according to the JC value extracted from ODU1 signal overhead be mapped to the STMk signal of the ODU1 signal with
The Rate Relationship of the ODU1 signal, according to the Rate Relationship to the ODU1 signaling protein14-3-3 clock CLK_ODU1_REC into
Row frequency dividing obtains the STMk signaling protein14-3-3 clock CLK_STMk_REC.
Wherein, the OTU2 signaling protein14-3-3 clock CLK_OTU2_REC is directly obtained by the rate of detection OTU2 signal
, AMP demapping device or GMP demapping device in the prior art can directly detect OTU2 signal from route
Then rate obtains OTU2 signaling protein14-3-3 clock.
Wherein, the JC value extracted from ODU2 signal overhead is used to adjust ODU1 signal and ODU2 during asynchronous mapping
The rate variance of signal；The JC value extracted from ODU1 signal overhead be used for during asynchronous mapping adjust STMk signal with
The rate variance of ODU1 signal；
Wherein, according to the Rate Relationship of ODU2 signal and OTU2 signal to OTU2 signaling protein14-3-3 clock CLK_OTU2_REC
It is divided to obtain the ODU2 signaling protein14-3-3 clock CLK_ODU2_REC, comprising:
CLK_ODU2_REC=k1*CLK_OTU2_REC；
Wherein, 239/255 k1.
Wherein, it when the bit wide that the bit wide of ODU1 signal is 16bit and ODU2 signal is 64bit, is closed according to the rate
System divides the ODU2 signaling protein14-3-3 clock CLK_ODU2_REC to obtain the ODU1 signaling protein14-3-3 clock CLK_
ODU1_REC, comprising:
CLK_ODU1_REC=((7616-JC/2)/7648) * CLK_ODU2_REC；
Wherein, the frequency of CLK_ODU1_REC is adjusted by accumulation JC value, comprising: whenever the frame or multiframe received
The cumulative JC of JC value entrained by ODU2 signalAccumulationReach one word of positive adjustment or negative sense adjusts a word, then CLK_ODU1_
The frequency of REC adjusts a unit, then JCAccumulationIt resets, JC value restarts to accumulate after new ODU2 signal frame arrives.
Wherein, when STMk signal is STM16 signal, and the bit wide of ODU1 signal and STM16 signal is all 16bit, root
The ODU1 signaling protein14-3-3 clock CLK_ODU1_REC is divided to obtain the STM16 signal according to the Rate Relationship
Recovered clock CLK_STM16_REC, comprising:
CLK_STM16_REC=((7616-JC/2)/7648) * CLK_ODU1_REC；
Wherein, the frequency of CLK_STM16_REC is adjusted by accumulation JC value, comprising: whenever the frame that receives or more
The cumulative JC of JC value entrained by frame ODU1 signalAccumulationReach one word of positive adjustment or negative sense adjusts a word, then CLK_
The frequency of STM16_REC adjusts a unit, then JCAccumulationIt resets, JC value restarts to accumulate after new ODU1 signal frame arrives
It is tired.
Wherein, the ODU1 signaling protein14-3-3 clock CLK_ODU1_REC is divided to obtain according to the Rate Relationship
After the STMk signaling protein14-3-3 clock CLK_STMk_REC, further includes:
The duty ratio of the STMk signaling protein14-3-3 clock CLK_STMk_REC is adjusted to 50%.
As shown in figure 3, the system that the embodiment of the invention provides a kind of to realize clock transparent transmission during asynchronous mapping, is answered
For asynchronous mapping process AMP demapping device, comprising:
ODU2 recovering clock signals module, for according to Optical Channel Data Unit-k ODU2 signal and the carrying ODU2 signal
The Rate Relationship of optical channel transmission unit OTU2 signal OTU2 signaling protein14-3-3 clock CLK_OTU2_REC divide
To the ODU2 signaling protein14-3-3 clock CLK_ODU2_REC；
ODU1 recovering clock signals module, described in being mapped to according to the JC value extracted from ODU2 signal overhead is determining
The Rate Relationship of the ODU1 signal of ODU2 signal and the ODU2 signal, according to the Rate Relationship to the extensive of the ODU2 signal
Multiple clock CLK_ODU2_REC is divided to obtain the ODU1 signaling protein14-3-3 clock CLK_ODU1_REC；
STMk recovering clock signals module, described in being mapped to according to the JC value extracted from ODU1 signal overhead is determining
The Rate Relationship of the STMk signal of ODU1 signal and the ODU1 signal, according to the Rate Relationship to the extensive of the ODU1 signal
Multiple clock CLK_ODU1_REC is divided to obtain the STMk signaling protein14-3-3 clock CLK_STMk_REC.
Wherein, which further includes OTU2 recovering clock signals module, direct for the rate by detection OTU2 signal
Obtain OTU2 signaling protein14-3-3 clock CLK_OTU2_REC；
Wherein, ODU2 recovering clock signals module, for the Rate Relationship according to ODU2 signal and OTU2 signal to OTU2
Signaling protein14-3-3 clock CLK_OTU2_REC is divided to obtain the ODU2 signaling protein14-3-3 clock CLK_ODU2_REC, packet
It includes:
CLK_ODU2_REC=k1*CLK_OTU2_REC；
Wherein, 239/255 k1.
Wherein, ODU1 recovering clock signals module is the bit wide of 16bit and ODU2 signal for the bit wide when ODU1 signal
When for 64bit, the ODU2 signaling protein14-3-3 clock CLK_ODU2_REC is divided to obtain institute according to the Rate Relationship
State ODU1 signaling protein14-3-3 clock CLK_ODU1_REC, comprising:
CLK_ODU1_REC=((7616-JC/2)/7648) * CLK_ODU2_REC；
Wherein, the frequency of CLK_ODU1_REC is adjusted by accumulation JC value, comprising: whenever the frame or multiframe received
The cumulative JC of JC value entrained by ODU2 signalAccumulationReach one word of positive adjustment or negative sense adjusts a word, then CLK_ODU1_
The frequency of REC adjusts a unit, then JCAccumulationIt resets, JC value restarts to accumulate after new ODU2 signal frame arrives.
Wherein, STMk recovering clock signals module, for working as STMk signal for STM16 signal, and ODU1 signal and STM16
When the bit wide of signal is all 16bit, according to the Rate Relationship to the ODU1 signaling protein14-3-3 clock CLK_ODU1_REC into
Row frequency dividing obtains the STM16 signaling protein14-3-3 clock CLK_STM16_REC, comprising:
CLK_STM16_REC=((7616-JC/2)/7648) * CLK_ODU1_REC；
Wherein, the frequency of CLK_STM16_REC is adjusted by accumulation JC value, comprising: whenever the frame that receives or more
The cumulative JC of JC value entrained by frame ODU1 signalAccumulationReach one word of positive adjustment or negative sense adjusts a word, then CLK_
The frequency of STM16_REC adjusts a unit, then JCAccumulationIt resets, JC value restarts to accumulate after new ODU1 signal frame arrives
It is tired.
Wherein, STMk recovering clock signals module is also used to according to the Rate Relationship to the ODU1 signaling protein14-3-3
Clock CLK_ODU1_REC is divided after obtaining the STMk signaling protein14-3-3 clock CLK_STMk_REC, and the STMk is believed
Number the duty ratio of recovered clock CLK_STMk_REC be adjusted to 50%.
Using example
Upstream transmission equipment (mapping end) by the STM16 business asynchronous mapping of client to ODU1 unit, then by ODU1 unit
Then ODU2 unit is encapsulated into OTU2 unit to ODU2 unit and is transmitted downstream to transmission device by asynchronous mapping.Downstream transmission
Equipment (demapping end) receives OTU2 signal from fibre circuit, obtains OTU2 signaling protein14-3-3 clock CLOCK_OTU2_
REC finally recovers client traffic data (STM16 letter by a series of scaling down processings under OTU2 signaling protein14-3-3 clock domain
Number) clock signal.
As shown in figure 4, specifically including following process:
1, OTU2 signal is received, OTU2 signaling protein14-3-3 clock CLK_OTU2_ is determined according to the actual speed rate of OTU2 signal
REC；
If data bit width is 64 bit wides, the standard speed for the OTU2 that G.709/Y.1331 ITU-T defines can be indicated
For 155.52* (255/237) * 64 (Mbps), it means that the standard clock frequency CLK_OTU2_STA of OTU2 is 155.52*
(255/237)(Mhz)。
Since there are frequency deviations on route, so the rate for the OTU2 that the route optical port of downstream veneer receives can be expressed as
CLK_OTU2_REC*64, CLK_OTU2_REC is known as OTU2 signaling protein14-3-3 clock here, which can be in 155.52* (255/
237) (Mhz) changes up and down, and corresponding is the actual speed rate of OTU2 on route；
OTU2 signaling protein14-3-3 clock CLK_OTU2_REC, the technological means can be directly obtained by detecting OTU2 signal
Belong to the prior art.
2, ODU2 signal is obtained from the OTU2 signal received, according to the Rate Relationship pair of ODU2 signal and OTU2 signal
OTU2 signaling protein14-3-3 clock CLK_OTU2_REC is divided to obtain the ODU2 signaling protein14-3-3 clock CLK_ODU2_REC；
G.709/Y.1331, ITU-T provides, 1-3824 column when OTU2 signaling bearer ODU2 signal, in OTU2 signal frame
For carrying ODU2 signal, wherein OTU2 signal frame structure is: 4080 column * 4 rows (unit is byte).
Therefore, the actual speed rate ratio k1 of the actual speed rate of ODU2 signal and OTU2 signal is indicated are as follows:
If the actual speed rate VEL_ODU2 of ODU2 signal is indicated with ODU2 signaling protein14-3-3 clock CLK_ODU2_REC are as follows:
VEL_ODU2=CLK_ODU2_REC*64；(2-2)
The actual speed rate VEL_OTU2 of OTU2 signal is indicated with OTU2 signaling protein14-3-3 clock CLK_OTU2_REC are as follows:
VEL_OTU2=CLK_OTU2_REC*64；(2-3)
The then pass of ODU2 signaling protein14-3-3 clock CLK_ODU2_REC and OTU2 signaling protein14-3-3 clock CLK_ODU2_REC
System indicates are as follows:
CLK_ODU2_REC=k1*CLK_OTU2_REC；(2-4)
Wherein, k1=239/255.
3, ODU1 signal and the institute for being mapped to the ODU2 signal are determined according to the JC value extracted from ODU2 signal overhead
The Rate Relationship for stating ODU2 signal carries out the ODU2 signaling protein14-3-3 clock CLK_ODU2_REC according to the Rate Relationship
Frequency dividing obtains the ODU1 signaling protein14-3-3 clock CLK_ODU1_REC；
Wherein, ODU1 frame structure is identical as ODU2 frame structure, is 3824 column *, 4 row (unit is byte), G.709 middle rule
The standard speed of fixed ODU1 is 155.52* (239/238) * 16 (Mbps), and the standard speed of ODU2 is 155.52* (239/
237)*64(Mbps)。
AMP regulation, when ODU1 signal is mapped to ODU2 signal, an ODU1 frame is mapped to the one of the payload of 4 ODU2 frames
In a time slot, wherein the payload of ODU2 is -3824 column of the 17th column, and entire payload area is divided into 4 time slots, time slot
Capacity is (3824-16) * 4/4=3808 byte.
Due between ODU1 signal and ODU2 signal there are rate variance, ODU1 signal is adjusted by JC value in AMP
With the rate variance of ODU2 signal, every 4 ODU2 frames could complete the AMP mapping of an ODU1 frame, only have in four ODU2 frames
One ODU2 frame carries out JC adjustment.When specific adjustment, JC adjustment is divided into PJO1 (1 byte of forward direction adjustment), PJO2 (forward direction adjustment
2 bytes), NJO (negative sense adjust 1 byte).
Therefore, by JC adjustment rate variance principle can push away ODU1 and ODU2 speed ratio k2, be expressed as follows:
If the actual speed rate VEL_ODU1 of ODU1 signal is indicated with ODU1 signaling protein14-3-3 clock CLK_ODU2_REC are as follows:
VEL_ODU1=CLK_ODU1_REC*16；(3-2)
The actual speed rate VEL_ODU2 of ODU2 signal is indicated with ODU2 signaling protein14-3-3 clock CLK_ODU2_REC are as follows:
VEL_ODU2=CLK_ODU2_REC*64；(3-3)
The then pass of ODU1 signaling protein14-3-3 clock CLK_ODU1_REC and ODU2 signaling protein14-3-3 clock CLK_ODU2_REC
System indicates are as follows:
CLK_ODU1_REC=((15232-JC)/15296) * CLK_ODU2_REC；(3-4)
When the bit wide of ODU1 signal is 16bit,
CLK_ODU1_REC=((7616-JC/2)/7648) * CLK_ODU2_REC；(3-5)
That is, needing to accumulate frequency of the JC value to adjust CLK_ODU1_REC in practice, comprising: whenever the frame received
Or the cumulative JC of JC value entrained by multiframe ODU2 signalAccumulationReach one word of positive adjustment or negative sense adjusts a word, then CLK_
The frequency of ODU1_REC adjusts a unit, then JCAccumulationIt resets, JC value restarts to accumulate after new ODU2 signal frame arrives
It is tired；
Wherein, when JC value is cumulative reaches NJO twice, JCAccumulationEqual to -1, and reach 1 PJO2 or two when JC value is cumulative
When secondary PJO1, JCAccumulationEqual to+1.
4, STM16 signal and the institute for being mapped to the ODU1 signal are determined according to the JC value extracted from ODU1 signal overhead
The Rate Relationship for stating ODU1 signal carries out the ODU1 signaling protein14-3-3 clock CLK_ODU1_REC according to the Rate Relationship
Frequency dividing obtains the STM16 signaling protein14-3-3 clock CLK_STM16_REC.
STM16 to ODU1 is AMP mapping, and wherein STM16 occupies in ODU1 17 column to whole spaces of 3824 column, and the two
Between rate variance be adjusted with JC value.
Therefore, by AMP map principle can push away STM16 and ODU1 speed ratio k3, be expressed as follows:
If the actual speed rate VEL_STM16 of STM16 signal is indicated with the recovered clock CLK_STM16_REC of STM16 are as follows:
VEL_STM16=CLK_STM16_REC*16；(4-2)
If the actual speed rate VEL_ODU1 of ODU1 signal is indicated with the recovered clock CLK_ODU1_REC of ODU1 are as follows:
VEL_ODU1=CLK_ODU1_REC*16；(4-3)
Then STM16 signaling protein14-3-3 clock CLK_STM16_REC and ODU1 signaling protein14-3-3 clock CLK_ODU1_REC
Relationship is expressed as:
CLK_STM16_REC=((15232-JC)/15296) * CLK_ODU1_REC；(4-4)
Since CLK_STM16_REC and CLK_ODU1_REC are relative to the recovered clock of 16bit bit wide, so:
CLK_STM16_REC=((7616-JC/2)/7648) * CLK_ODU1_REC；(4-5)
That is, needing to accumulate frequency of the JC value to adjust CLK_STM16_REC in practice, comprising: whenever one received
The cumulative JC of JC value entrained by frame or multiframe ODU1 signalAccumulationReach one word of positive adjustment or negative sense adjusts a word, then
The frequency of CLK_STM16_REC adjusts a unit, then JCAccumulationIt resets, JC value is opened again after new ODU1 signal frame arrives
Begin to accumulate；
Wherein, when JC value is cumulative reaches NJO twice, JCAccumulationEqual to -1, and reach 1 PJO2 or two when JC value is cumulative
When secondary PJO1, JCAccumulationEqual to+1.
Finally, due to which the duty ratio of STM16 signaling protein14-3-3 clock CLK_STM16_REC signal may not be stringent
50%, so, shaping can be carried out by way of first dividing frequency multiplication again to CLK_STM16_REC signal, so that after shaping
The duty ratio of signal is 50%, has just obtained the transmission reference clock i.e. transmission clock of STM16.
A kind of method and system for realizing clock transparent transmission in asynchronous mapping process provided by the above embodiment, is utilized JC
Value carries out clock transparent transmission, and JC value is placed in expense by when mapping to be transmitted, and extracts in demapping direction, so that it may restore
The clock of former business out.The above method can be used as to the supplement for being carried out clock transparent transmission in G.709 based on Cm, under AMP is mapped
Clock transparent transmission and GMP mapping under clock transparent transmission unified.
Those of ordinary skill in the art will appreciate that all or part of the steps in the above method can be instructed by program
Related hardware is completed, and described program can store in computer readable storage medium, such as read-only memory, disk or CD
Deng.Optionally, one or more integrated circuits also can be used to realize, accordingly in all or part of the steps of above-described embodiment
Ground, each module/unit in above-described embodiment can take the form of hardware realization, can also use the shape of software function module
Formula is realized.The present invention is not limited to the combinations of the hardware and software of any particular form.
It should be noted that the invention may also have other embodiments, without departing substantially from spirit of that invention and its essence
In the case of, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these are corresponding
Change and modification all should fall within the scope of protection of the appended claims of the present invention.
Claims (6)
1. a kind of method that clock transparent transmission is realized during asynchronous mapping, is applied to asynchronous mapping process AMP demapping device,
This method comprises:
According to the speed of Optical Channel Data Unit-k ODU2 signal and the optical channel transmission unit OTU2 signal for carrying the ODU2 signal
Rate relationship divides OTU2 signaling protein14-3-3 clock CLK_OTU2_REC to obtain the ODU2 signaling protein14-3-3 clock CLK_
ODU2_REC；
The ODU1 signal and the ODU2 for being mapped to the ODU2 signal are determined according to the JC value extracted from ODU2 signal overhead
The Rate Relationship of signal divide to the ODU2 signaling protein14-3-3 clock CLK_ODU2_REC according to the Rate Relationship
To the ODU1 signaling protein14-3-3 clock CLK_ODU1_REC；
The STMk signal and the ODU1 for being mapped to the ODU1 signal are determined according to the JC value extracted from ODU1 signal overhead
The Rate Relationship of signal divide to the ODU1 signaling protein14-3-3 clock CLK_ODU1_REC according to the Rate Relationship
To the STMk signaling protein14-3-3 clock CLK_STMk_REC；
When the bit wide that the bit wide of ODU1 signal is 16bit and ODU2 signal is 64bit, according to the Rate Relationship to described
ODU2 signaling protein14-3-3 clock CLK_ODU2_REC is divided to obtain the ODU1 signaling protein14-3-3 clock CLK_ODU1_REC,
Include:
CLK_ODU1_REC=((7616-JC/2)/7648) * CLK_ODU2_REC；
Wherein, the frequency of CLK_ODU1_REC is adjusted by accumulation JC value, comprising: whenever the frame or multiframe ODU2 received
The cumulative JC of JC value entrained by signalAccumulationReach one word of positive adjustment or negative sense adjusts a word, then CLK_ODU1_REC
Frequency adjusts a unit, then JCAccumulationIt resets, JC value restarts to accumulate after new ODU2 signal frame arrives；
When STMk signal is STM16 signal, and the bit wide of ODU1 signal and STM16 signal is all 16bit, according to the rate
Relationship is divided to obtain the STM16 signaling protein14-3-3 clock to the ODU1 signaling protein14-3-3 clock CLK_ODU1_REC
CLK_STM16_REC, comprising:
CLK_STM16_REC=((7616-JC/2)/7648) * CLK_ODU1_REC；
Wherein, the frequency of CLK_STM16_REC is adjusted by accumulation JC value, comprising: whenever the frame or multiframe received
The cumulative JC of JC value entrained by ODU1 signalAccumulationReach one word of positive adjustment or negative sense adjusts a word, then CLK_STM16_
The frequency of REC adjusts a unit, then JCAccumulationIt resets, JC value restarts to accumulate after new ODU1 signal frame arrives.
2. the method as described in claim 1, it is characterised in that:
OTU2 signaling protein14-3-3 clock CLK_OTU2_REC is divided according to ODU2 signal and the Rate Relationship of OTU2 signal
Obtain the ODU2 signaling protein14-3-3 clock CLK_ODU2_REC, comprising:
CLK_ODU2_REC=k1*CLK_OTU2_REC；
Wherein, 239/255 k1.
3. the method as described in claim 1, it is characterised in that:
The ODU1 signaling protein14-3-3 clock CLK_ODU1_REC is divided to obtain the STMk according to the Rate Relationship
After signaling protein14-3-3 clock CLK_STMk_REC, further includes:
The duty ratio of the STMk signaling protein14-3-3 clock CLK_STMk_REC is adjusted to 50%.
4. a kind of system that clock transparent transmission is realized during asynchronous mapping, is applied to asynchronous mapping process AMP demapping device,
Include:
ODU2 recovering clock signals module, for the light according to Optical Channel Data Unit-k ODU2 signal and the carrying ODU2 signal
The Rate Relationship of channel transmission element OTU2 signal is divided to obtain institute to OTU2 signaling protein14-3-3 clock CLK_OTU2_REC
State ODU2 signaling protein14-3-3 clock CLK_ODU2_REC；
ODU1 recovering clock signals module, for being mapped to the ODU2 according to the JC value determination extracted from ODU2 signal overhead
The Rate Relationship of the ODU1 signal of signal and the ODU2 signal, when according to the Rate Relationship to the ODU2 signaling protein14-3-3
Clock CLK_ODU2_REC is divided to obtain the ODU1 signaling protein14-3-3 clock CLK_ODU1_REC；
STMk recovering clock signals module, for being mapped to the ODU1 according to the JC value determination extracted from ODU1 signal overhead
The Rate Relationship of the STMk signal of signal and the ODU1 signal, when according to the Rate Relationship to the ODU1 signaling protein14-3-3
Clock CLK_ODU1_REC is divided to obtain the STMk signaling protein14-3-3 clock CLK_STMk_REC；
The ODU1 recovering clock signals module, being also used to the bit wide that the bit wide when ODU1 signal is 16bit and ODU2 signal is
When 64bit, the ODU2 signaling protein14-3-3 clock CLK_ODU2_REC is divided to obtain according to the Rate Relationship described
ODU1 signaling protein14-3-3 clock CLK_ODU1_REC, comprising:
CLK_ODU1_REC=((7616-JC/2)/7648) * CLK_ODU2_REC；
Wherein, the frequency of CLK_ODU1_REC is adjusted by accumulation JC value, comprising: whenever the frame or multiframe ODU2 received
The cumulative JC of JC value entrained by signalAccumulationReach one word of positive adjustment or negative sense adjusts a word, then CLK_ODU1_REC
Frequency adjusts a unit, then JCAccumulationIt resets, JC value restarts to accumulate after new ODU2 signal frame arrives；
The STMk recovering clock signals module is also used to when STMk signal be STM16 signal, and ODU1 signal and STM16 believe
Number bit wide when being all 16bit, the ODU1 signaling protein14-3-3 clock CLK_ODU1_REC is carried out according to the Rate Relationship
Frequency dividing obtains the STM16 signaling protein14-3-3 clock CLK_STM16_REC, comprising:
CLK_STM16_REC=((7616-JC/2)/7648) * CLK_ODU1_REC；
Wherein, the frequency of CLK_STM16_REC is adjusted by accumulation JC value, comprising: whenever the frame or multiframe received
The cumulative JC of JC value entrained by ODU1 signalAccumulationReach one word of positive adjustment or negative sense adjusts a word, then CLK_STM16_
The frequency of REC adjusts a unit, then JCAccumulationIt resets, JC value restarts to accumulate after new ODU1 signal frame arrives.
5. system as claimed in claim 4, it is characterised in that:
ODU2 recovering clock signals module, for the Rate Relationship according to ODU2 signal and OTU2 signal to OTU2 signaling protein14-3-3
Clock CLK_OTU2_REC is divided to obtain the ODU2 signaling protein14-3-3 clock CLK_ODU2_REC, comprising:
CLK_ODU2_REC=k1*CLK_OTU2_REC；
Wherein, 239/255 k1.
6. system as claimed in claim 4, it is characterised in that:
STMk recovering clock signals module is also used to according to the Rate Relationship to the ODU1 signaling protein14-3-3 clock CLK_
ODU1_REC is divided after obtaining the STMk signaling protein14-3-3 clock CLK_STMk_REC, by the STMk signaling protein14-3-3
The duty ratio of clock CLK_STMk_REC is adjusted to 50%.
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| PCT/CN2015/074526 WO2016058328A1 (en) | 2014-10-17 | 2015-03-18 | Method and system for realizing clock passthrough |
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| CN1983888A (en) * | 2006-06-07 | 2007-06-20 | 华为技术有限公司 | Device and method for restoring clock |
| CN101378399A (en) * | 2008-09-28 | 2009-03-04 | 华为技术有限公司 | Method and apparatus for mapping and de-mapping business data |
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