CN106684121A - Base structure of hetero-junction bipolar transistor and making method thereof - Google Patents
Base structure of hetero-junction bipolar transistor and making method thereof Download PDFInfo
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- CN106684121A CN106684121A CN201611107889.9A CN201611107889A CN106684121A CN 106684121 A CN106684121 A CN 106684121A CN 201611107889 A CN201611107889 A CN 201611107889A CN 106684121 A CN106684121 A CN 106684121A
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- base
- bipolar transistor
- layer
- heterojunction bipolar
- upper metal
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- 238000000034 method Methods 0.000 title claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 42
- 229910052751 metal Inorganic materials 0.000 claims abstract description 42
- 238000009792 diffusion process Methods 0.000 claims abstract description 35
- 239000004065 semiconductor Substances 0.000 claims abstract description 32
- 230000004888 barrier function Effects 0.000 claims abstract description 10
- 239000010953 base metal Substances 0.000 claims abstract description 8
- 230000008021 deposition Effects 0.000 claims description 19
- 230000008020 evaporation Effects 0.000 claims description 11
- 238000001704 evaporation Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 238000011161 development Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 66
- 238000000151 deposition Methods 0.000 description 14
- 239000010931 gold Substances 0.000 description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 7
- 229910052737 gold Inorganic materials 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910000510 noble metal Inorganic materials 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- SECXISVLQFMRJM-UHFFFAOYSA-N N-Methylpyrrolidone Chemical compound CN1CCCC1=O SECXISVLQFMRJM-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000005496 tempering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66242—Heterojunction transistors [HBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
Abstract
The invention discloses a base structure of a hetero-junction bipolar transistor. The base structure comprises a base semiconductor layer and base metal arranged on the base semiconductor layer. The base metal includes a diffusion barrier layer and an upper metal layer which are stacked in turn. The diffusion barrier layer separates the upper metal layer and the base semiconductor layer from each other to stop the upper metal layer from diffusing into the base semiconductor layer. The edge of the upper metal layer is retracted inwards by 0.05-0.1 microns relative to the edge of the diffusion barrier layer. The invention further discloses a making method of the structure. The upper metal layer and the diffusion barrier layer are made into different widths through two photo-mask processes. Metal at the edge of the upper metal layer can be effectively prevented from diffusing into the base semiconductor layer from the edge of the diffusion barrier layer. The leakage problem is solved. The reliability of devices is increased.
Description
Technical field
The present invention relates to semiconductor technology, the base structure of more particularly to a kind of heterojunction bipolar transistor and its making
Method.
Background technology
In the manufacturing process of heterojunction bipolar transistor, the metal procedure of electrode is an important link.It is existing
Base structure, is that the base semiconductor layer surface of presumptive area in device comes out, then deposition electric conductivity is good thereon
Noble metal (such as gold) formed.Make as base semiconductor layer is typically iii v compound semiconductor, gold easily spreads
The problems such as causing electric leakage within quasiconductor.For this purpose, improved technology is first deposit diffusion barriers redeposition layer gold, pass through
Diffusion impervious layer between base semiconductor layer and layer gold come prevent gold diffusion enter base semiconductor within.
However, as the noble metals such as gold have stronger diffusional flow, still easily by the edge of diffusion impervious layer
Diffused within base semiconductor layer downwards and affect the overall performance of transistor, above-mentioned electrical leakage problems still cannot be solved
Certainly, the reliability of device is difficult to ensure that.
The content of the invention
The invention provides a kind of base structure of heterojunction bipolar transistor and preparation method thereof, which overcomes existing skill
Weak point existing for art.
The technical solution adopted for the present invention to solve the technical problems is：
A kind of base structure of heterojunction bipolar transistor, including base semiconductor layer and located at base semiconductor layer it
On base metal, the base metal includes the diffusion impervious layer for stacking gradually and upper metal level, and the diffusion impervious layer will
The upper metal level and the base semiconductor layer separate to stop that the upper metal level diffuses into the base semiconductor layer,
The edge of the relatively described diffusion impervious layer in edge of wherein described upper metal level inside contracts 0.05~0.1 μm.
Preferably, the base semiconductor layer is GaAs.
Preferably, the diffusion impervious layer is Pt and/or Ti.
Preferably, the diffusion impervious layer includes what is stacked gradually from the bottom to top：Thickness is a Pt layers of 3~8nm, thickness
Spend the Ti layers and the 2nd Pt layers that thickness is 40~60nm for 40~60nm.
Preferably, the upper metal level is the Au layers that thickness is 70~90nm.
A kind of manufacture method of the base structure of above-mentioned heterojunction bipolar transistor, comprises the following steps：
1) surface region exposed for forming the base semiconductor layer of heterojunction bipolar transistor is provided；
2) covered in by first light and formed in the surface region the first deposition window, deposited metal deposits window in first
Diffusion impervious layer is formed within mouthful；
3) covered in by second light and formed on the diffusion impervious layer the second deposition window, the second deposition window phase
0.05~0.1 μm is inside contracted to the first deposition window edge, deposited metal forms upper metal level within the second deposition window.
Preferably, step 2) in, the formation of the diffusion impervious layer includes following sub-step：By evaporation or sputter shape
Into the Pt layers that thickness is 3~8nm, and it is tempered；The Ti layers that thickness is 40~60nm are formed by evaporation or sputter；Pass through
Evaporation or sputter form the 2nd Pt layers that thickness is 40~60nm.
Preferably, step 3) in, the upper metal level is formed by evaporation or sputter Au, and thickness is 70~90nm.
Preferably, the first deposition window and the second deposition window are by coating photoresistance, exposure, development formation respectively
's；Step 2) and step 3) in remaining photoresistance is peeled off also after deposited metal.
It is compared to prior art, of the invention by the upper metal level constriction of easy diffusional flow so as to which that width is less than diffusion barrier
Layer, the border of upper metal level are 0.05~0.1 μm with the frontier distance of diffusion impervious layer, can effectively prevent metal level edge
Metal solves electrical leakage problems by diffusion impervious layer edge-diffusion to base semiconductor layer, increased the reliability of device.
Description of the drawings
Fig. 1 is the structural representation of the present invention；
Fig. 2 is the corresponding structural representation of each step in manufacture method flow process of the present invention.
Specific embodiment
The present invention is described in further detail below in conjunction with drawings and Examples.Each accompanying drawing of the present invention only illustrate with
The present invention is easier to understand, its concrete ratio can be adjusted according to design requirement.Opposed member in figure described in text
Upper and lower relation, for the relative position for referring to component is will be understood that in those skilled in the art, therefore can all overturn and be in
Existing identical component, this should all belong to the scope disclosed by this specification together.Additionally, the number of element and structure shown in figure,
The thickness contrast of the thickness and interlayer of layer, it is merely illustrative, do not limited with this, actually can be adjusted according to design requirement
It is whole.
With reference to Fig. 1, a kind of base structure of heterojunction bipolar transistor includes base semiconductor layer 1 and located at base stage half
Base metal on conductor layer 1, the base metal include the diffusion impervious layer 2 for stacking gradually and upper metal level 3, the expansion
The upper metal level 3 and the base semiconductor layer 1 are separated to stop that the upper metal level 3 diffuses into institute by scattered barrier layer 2
Base semiconductor layer 1 is stated, wherein the edge of the edge of the upper metal level 3 diffusion impervious layer 2 relatively inside contracts 0.05~0.1
μm.Base semiconductor layer 1 can be III-V compound, such as GaAs；Diffusion impervious layer 2 can be Pt and/or Ti；Upper metal
Layer 3 can be Au.
Further, in the present embodiment, diffusion impervious layer 2 includes what is stacked gradually from the bottom to top：Thickness is 3~8nm (examples
Such as 5nm) a Pt layers 21, thickness for 40~60nm (such as 50nm) Ti layers 22 and thickness be 40~60nm (for example
The 2nd Pt layers 23 50nm).On the 2nd Pt layers 23, thickness is 70~90nm (such as 80nm) to upper metal level 3.
With reference to Fig. 2, the manufacture method of the base structure of the heterojunction bipolar transistor of above-described embodiment, including following step
Suddenly：
1) refer to 2a, there is provided the exposed surface region of base semiconductor layer 1 for forming heterojunction bipolar transistor.
In the processing procedure of heterojunction bipolar transistor, the exposed surface region of the base semiconductor 1 specifically can be removed by photoetching process
The emitter semiconductor layer and dielectric layer of presumptive area is realizing.
2) 2b is referred to, by first light shield technique, photoresistance is coated and is formed photoresist layer 4, expose, be developed in the surface district
First is formed on domain and deposits window 41.
3) with reference to Fig. 2 c, by way of evaporation or sputter, deposited metal Pt forms first within the first deposition window 41
Pt layers 21 are simultaneously tempered, and tempering can be specifically the heat treatment 2min at 360 DEG C.
4) with reference to Fig. 2 d, metal Ti is sequentially depositing by way of evaporation or sputter and is deposited first within window 41 in first
Ti layers 22 are formed on Pt layers 21, deposited metal Pt is deposited in first and formed on Ti layers 22 within window 41 the 2nd Pt layers 23,
First Pt layers 21, Ti layers 22 and the 2nd Pt layers 23 are built up diffusion impervious layer 2.
5) with reference to Fig. 2 e, remaining photoresist layer is peeled off by chemical liquids such as N-Methyl pyrrolidone.
6) with reference to Fig. 2 f, by second light shield technique, coat photoresistance and form photoresist layer 5, expose, be developed in diffusion barrier
Second is formed on layer 2 and deposits window 51, less than the first deposition window 41, edge is with respect to the first deposition window for the second deposition window 51
Edge inside contracts 0.05~0.1 μm.
7) with reference to Fig. 2 g, by way of evaporation or sputter, deposited metal Au forms upper gold within the second deposition window 51
Category layer 3.
8) with reference to Fig. 2 h, remaining photoresistance is peeled off, the base structure of the heterojunction bipolar transistor is formed.
Above-described embodiment only be used for further illustrate the present invention a kind of heterojunction bipolar transistor base structure and its
Manufacture method, but embodiment is the invention is not limited in, what every technical spirit according to the present invention was made to above example
Any simple modification, equivalent variations and modification, each fall within the protection domain of technical solution of the present invention.
Claims (9)
1. a kind of base structure of heterojunction bipolar transistor, including base semiconductor layer and on the base semiconductor layer
Base metal, it is characterised in that：The base metal includes the diffusion impervious layer for stacking gradually and upper metal level, the diffusion
The upper metal level and the base semiconductor layer are separated to stop that the upper metal level diffuses into the base stage by barrier layer
Semiconductor layer, wherein the edge of the relatively described diffusion impervious layer in the edge of the upper metal level inside contracts 0.05~0.1 μm.
2. the base structure of heterojunction bipolar transistor according to claim 1, it is characterised in that：The base semiconductor
Layer is GaAs.
3. the base structure of heterojunction bipolar transistor according to claim 1, it is characterised in that：The diffusion impervious layer
It is Pt and/or Ti.
4. the base structure of heterojunction bipolar transistor according to claim 3, it is characterised in that：The diffusion impervious layer
Including what is stacked gradually from the bottom to top：Thickness is that a Pt layers, the Ti layers that thickness is 40~60nm and the thickness of 3~8nm are
The 2nd Pt layers of 40~60nm.
5. the base structure of the heterojunction bipolar transistor according to claim 1 or 4, it is characterised in that：The upper metal
Layer is the Au layers that thickness is 70~90nm.
6. the manufacture method of the base structure of heterojunction bipolar transistor described in a kind of any one of Claims 1 to 5, its feature exist
In comprising the following steps：
1) surface region exposed for forming the base semiconductor layer of heterojunction bipolar transistor is provided；
2) covered in by first light and formed in the surface region first and deposit window, deposited metal in the first deposition window it
Interior formation diffusion impervious layer；
3) covered in by second light and formed on the diffusion impervious layer second and deposit window, the second deposition window is with respect to the
One deposition window edge inside contracts 0.05~0.1 μm, and deposited metal forms upper metal level within the second deposition window.
7. the manufacture method of the base structure of heterojunction bipolar transistor according to claim 6, it is characterised in that：Step
2), in, the formation of the diffusion impervious layer includes following sub-step：
The Pt layers that thickness is 3~8nm are formed by evaporation or sputter, and is tempered；
The Ti layers that thickness is 40~60nm are formed by evaporation or sputter；
The 2nd Pt layers that thickness is 40~60nm are formed by evaporation or sputter.
8. the manufacture method of the base structure of heterojunction bipolar transistor according to claim 6, it is characterised in that：Step
3) in, the upper metal level is formed by evaporation or sputter Au, and thickness is 70~90nm.
9. the manufacture method of the base structure of heterojunction bipolar transistor according to claim 6, it is characterised in that：It is described
First deposition window and the second deposition window are by coating photoresistance, exposure, development formation respectively；Step 2) and step 3) in
Remaining photoresistance is peeled off also after deposited metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611107889.9A CN106684121A (en) | 2016-12-06 | 2016-12-06 | Base structure of hetero-junction bipolar transistor and making method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611107889.9A CN106684121A (en) | 2016-12-06 | 2016-12-06 | Base structure of hetero-junction bipolar transistor and making method thereof |
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| Publication Number | Publication Date |
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| CN106684121A true CN106684121A (en) | 2017-05-17 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611107889.9A Pending CN106684121A (en) | 2016-12-06 | 2016-12-06 | Base structure of hetero-junction bipolar transistor and making method thereof |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101409306A (en) * | 2007-08-30 | 2009-04-15 | 英飞凌科技股份公司 | Thyristor with improved conduction performance, thyristor device and method for producing the same |
| CN103956647A (en) * | 2014-05-16 | 2014-07-30 | 深圳清华大学研究院 | Semiconductor laser chip and manufacturing method thereof |
| CN104217968A (en) * | 2013-05-28 | 2014-12-17 | 英飞凌科技股份有限公司 | Method for processing a semiconductor workpiece |
| US20160343667A1 (en) * | 2012-02-24 | 2016-11-24 | Skyworks Solutions, Inc. | Methods related to a sputtered titanium tungsten layer formed over a copper interconnect stack structure |
-
2016
- 2016-12-06 CN CN201611107889.9A patent/CN106684121A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101409306A (en) * | 2007-08-30 | 2009-04-15 | 英飞凌科技股份公司 | Thyristor with improved conduction performance, thyristor device and method for producing the same |
| US20160343667A1 (en) * | 2012-02-24 | 2016-11-24 | Skyworks Solutions, Inc. | Methods related to a sputtered titanium tungsten layer formed over a copper interconnect stack structure |
| CN104217968A (en) * | 2013-05-28 | 2014-12-17 | 英飞凌科技股份有限公司 | Method for processing a semiconductor workpiece |
| CN103956647A (en) * | 2014-05-16 | 2014-07-30 | 深圳清华大学研究院 | Semiconductor laser chip and manufacturing method thereof |
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Application publication date: 20170517 |