CN106653853B - I shape grid field effect transistor is folded without knot with low current leakage - Google Patents
I shape grid field effect transistor is folded without knot with low current leakage Download PDFInfo
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- 230000005669 field effect Effects 0.000 title claims abstract description 44
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- 239000010703 silicon Substances 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 7
- 229910021419 crystalline silicon Inorganic materials 0.000 claims abstract description 3
- 238000002347 injection Methods 0.000 claims abstract description 3
- 239000007924 injection Substances 0.000 claims abstract description 3
- 239000000203 mixture Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 19
- 230000000694 effects Effects 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000005611 electricity Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005422 blasting Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
- H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L2029/7857—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET of the accumulation type
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Abstract
The present invention relates to a kind of to fold I shape grid field effect transistor without knot with low current leakage, silicon substrate including SOI wafer, it is the insulating layer of SOI wafer above the silicon substrate of SOI wafer, it is monocrystalline silicon above the insulating layer of SOI wafer, has gate medium insulating layer on the surface of monocrystalline silicon, gate medium surface of insulating layer is close to gate medium insulating layer with I shape gate electrode, gate electrode is folded；The both ends of monocrystalline silicon upper surface are respectively source electrode and drain electrode, are kept apart between adjacent single crystalline silicon and between source electrode and drain electrode by insulating medium layer；Injection metal in the through-hole formed after insulating medium layer of the monocrystalline silicon upper surface by two close end etches away will be attached to and generate source electrode and drain electrode respectively.In the case where keeping forward characteristic to be barely affected with the characteristic of low reverse leakage current, thus the power consumption of device is reduced, is suitble to promote and apply.
Description
Technical field
The invention belongs to super large-scale integration manufacturing fields, and in particular to one kind is suitable for low power consumption integrated circuit system
That makes folds I shape grid field effect transistor structure without knot with low current leakage.
Background technique
The basic unit MOSFET of integrated circuit can become smaller and smaller according to the requirement of Moore's Law, size, therewith
What is come is not only that difficulty in manufacturing process is deepened, various ill effects also highlighting more.On the one hand, size equal proportion
It reduces, channel is shorter and shorter, and the decrease of grid control ability is so that device is difficult to work normally and turn off.On the other hand, nanometer
It is high to heat treatment process requirement that precipitous PN junction conjunction is formed under scale.FinFETs structure based on multiple-grid technology and without knot
Type field effect transistor can effectively solve the above problems, and be widely used at present.Though the FinFETs structure based on multiple-grid technology
Grid so is enhanced to the static control ability of carrier, and effectively inhibits short-channel effect, however can't resolve grid leak
Crossover region and source and drain crossover region the Tunneling leakage current problem as caused by tunnel-effect.This is because FinFETs structure is simultaneously
Do not solve the problems, such as that Tunneling leakage current can constantly increase due to the reduction of distance between gate electrode and source electrode.Therefore base
With further decreasing for size the quiescent dissipation of device can be continued to increase in the device of FinFETs structure.To solve
The above problem, need to design one kind not only has good grid-control ability under deep nanoscale, but also with low current leakage characteristic
Field effect transistor.
Summary of the invention
Goal of the invention
It is let out to guarantee that nanoscale short channel grid-control field effect transistor significantly reduces tunnelling while guaranteeing grid-control ability
Leakage current, the present invention provide it is a kind of with low current leakage without knot fold I shape grid field effect transistor.
Technical solution
The present invention is achieved through the following technical solutions:
It is a kind of to fold I shape grid field effect transistor, the silicon substrate including SOI wafer, SOI without knot with low current leakage
It is the insulating layer of SOI wafer above the silicon substrate of wafer；It is monocrystalline silicon above SOI wafer insulating layer, the surface of monocrystalline silicon has
Gate medium insulating layer, gate medium surface of insulating layer are close to gate medium insulating layer with I shape gate electrode, gate electrode is folded；Monocrystalline silicon
The both ends of upper surface are respectively source electrode and drain electrode, are situated between adjacent single crystalline silicon and by insulation between source electrode and drain electrode
Matter is kept apart；Injection metal difference in the through-hole formed after dielectric of the monocrystalline silicon upper surface by two close end etches away will be attached to
Generate source electrode and drain electrode.
With common gate electrode in each position FinFETs device consistent in length the difference is that provided by the present invention
It is a kind of with low current leakage without knot fold I shape grid field effect transistor, the silicon substrate for being parallel to SOI wafer and along from
In source electrode to the rectilinear direction of drain electrode, folds I shape gate electrode and be located at the length of monocrystalline silicon upper section less than folding I shape grid
Electrode is located at the length of monocrystalline silicon two side portions, and the entire I shape gate electrode that folds shows English capitalization " I " shape being folded
Shape, i.e., folding I shape gate electrode is located at the part that monocrystalline silicon upper section constitutes the centre " perpendicular " of alphabetical " I ", and folds I shape grid electricity
Pole is located at two " cross " up and down that monocrystalline silicon two side portions then respectively constitute alphabetical " I ".Fold I shape gate electrode two " cross " difference up and down
Two perpendicular end surfaces composed by both ends with " perpendicular " are in the shape of a " convex ".This construction significantly increases gate electrode and is located at monocrystalline
Silicon upper section and the distance between source electrode or drain electrode, so that tunnel-effect significantly reduces, to effectively inhibit tunnel
Wear leakage current.At the same time, the retained part for being located at monocrystalline silicon upper section and constituting the centre " perpendicular " of alphabetical " I ", with
Two " cross " up and down for constituting alphabetical " I " positioned at monocrystalline silicon two sides partially together constitute folding I shape grid electricity proposed by the invention
Pole has with FinFETs device identical grid-control ability.
It is insulated from each other by gate medium insulating layer between monocrystalline silicon and folding I shape gate electrode；Gate medium insulating layer and folding I
Shape on the inside of shape gate electrode is adapted, and gate medium insulating layer also shows English capitalization " I " shape that both ends are folded,
It is located at the part that monocrystalline silicon upper section constitutes the centre " perpendicular " of alphabetical " I ", is located at monocrystalline silicon two side portions and then distinguishes structure
At two " cross " up and down of alphabetical " I "；Upper and lower two " cross " are in respectively " convex " with two perpendicular end surfaces composed by the both ends of " perpendicular "
Font；The part of " perpendicular " of protrusion is maked somebody a mere figurehead among it, and lower section penetrates monocrystalline silicon.
Folding I shape grid field effect transistor proposed by the invention is guaranteeing device with common FinFETs device phase
With grid-control ability while, significantly reduce leakage current.
Advantage and effect
The invention has the following advantages and beneficial effects:
1. low current leakage: since the present invention is shorter than in wafer segment grid perpendicular to wafer segment grid using horizontal
Length depression angle present I shape gate electrode: good grid-control ability can be kept perpendicular to the grid of wafer segment,
Weakened part short-channel effect；Level in wafer segment grid with a distance from source-drain electrode farther out, effectively reduce tunnelling and let out
Leakage current reduces quiescent dissipation.
2. effective inhibition of short-channel effect: the present invention uses channel portion of the monocrystalline silicon without knot as device, is more
Subconductivity had both reduced manufacturing process complexity, and had reduced manufacturing cost；Length of effective channel is also increased, is further subtracted
Small short-channel effect, improves Sub-Threshold Characteristic.
Detailed description of the invention
Fig. 1 is that the present invention has being formed on soi substrates without knot folding I shape grid field effect transistor for low current leakage
Three dimensional structure diagram.
Fig. 2 is that the present invention has being formed on soi substrates without knot folding I shape grid field effect transistor for low current leakage
Top view.
Fig. 3 has removing without knot folding I shape grid field effect transistor positioned at device for low current leakage for the present invention
Three dimensional structure diagram after the insulating medium layer of upper surface portion.
Fig. 4 has removing without knot folding I shape grid field effect transistor positioned at device for low current leakage for the present invention
Top view after the insulating medium layer of upper surface portion.
Fig. 5 has removing without knot folding I shape grid field effect transistor positioned at device for low current leakage for the present invention
The sectional view that cross section A is cut along Fig. 3 after the insulating medium layer of upper surface portion.
Fig. 6 has removing without knot folding I shape grid field effect transistor positioned at device for low current leakage for the present invention
The sectional view that cross section B is cut along Fig. 3 after the insulating medium layer of upper surface portion.
Fig. 7 is that the present invention has removing on the basis Fig. 3 without knot folding I shape grid field effect transistor for low current leakage
Three dimensional structure diagram after I shape gate electrode.
Fig. 8 is that the present invention has removing on the basis Fig. 3 without knot folding I shape grid field effect transistor for low current leakage
Top view after I shape gate electrode.
Fig. 9 is that the present invention has removing on the basis Fig. 7 without knot folding I shape grid field effect transistor for low current leakage
Three dimensional structure diagram after source electrode and drain electrode.
Figure 10 is that the present invention has shelling on the basis Fig. 7 without knot folding I shape grid field effect transistor for low current leakage
From the top view after source electrode and drain electrode.
Figure 11 is that the present invention has shelling on the basis Fig. 9 without knot folding I shape grid field effect transistor for low current leakage
From the three dimensional structure diagram after gate medium insulating layer.
Figure 12 is that the present invention has shelling on the basis Fig. 9 without knot folding I shape grid field effect transistor for low current leakage
From the top view after gate medium insulating layer.
Figure 13 to Figure 26 folds I shape grid field effect transistor structural unit system without knot with low current leakage for the present invention
The process flow chart of one specific example of Preparation Method.Wherein,
Figure 13 is step 1 schematic diagram,
Figure 14 is step 1 top view,
Figure 15 is step 2 schematic diagram,
Figure 16 is step 2 top view,
Figure 17 is step 3 schematic diagram,
Figure 18 is step 3 top view,
Figure 19 is step 4 schematic diagram,
Figure 20 is step 4 top view,
Figure 21 is step 5 schematic diagram,
Figure 22 is step 5 top view,
Figure 23 is step 6 schematic diagram,
Figure 24 is step 6 top view,
Figure 25 is step 7 schematic diagram,
Figure 26 is step 7 top view.
Appended drawing reference is said:
1, source electrode；2, drain electrode；3, insulating medium layer；4, gate electrode；5, gate medium insulating layer；6, monocrystalline silicon；7,SOI
The insulating layer of wafer；8, the silicon substrate of SOI wafer.
Specific embodiment
Following further describes the present invention with reference to the drawings:
The present invention provide it is a kind of fold I shape grid field effect transistor without knot with low current leakage, pass through the grid of I shape electricity
Low current leakage property is realized to the control of Carrier Profile in monocrystalline silicon in pole 4.It is in device gate electrode 4 plus positive voltage
On state.It folds I shape gate electrode 4 and is located at the portion that 6 two side portions of monocrystalline silicon then respectively constitute two " cross " up and down of alphabetical " I "
Point, length is longer, plays main control action to the Carrier Profile in monocrystalline silicon；And it folds I shape gate electrode 4 and is located at list
6 upper section of crystal silicon constitutes the part of the centre " perpendicular " of alphabetical " I ", and length is shorter, and is located at the central location of monocrystalline silicon 6,
Using such structure feature, on the one hand guarantee to fold between I shape gate electrode 4 and source electrode 1 and drain electrode 2 have distance compared with
Greatly, so that the electric field for overlapping place between electrode is obviously reduced, and then keep the leakage current generated by tunnel-effect significant
Reduce.On the other hand, since when device work is under sub-threshold status, it is attached that the potential extreme value of monocrystalline silicon appears in intermediate region
Closely, it is the key that Sub-Threshold Characteristic superiority and inferiority to the power of potential extreme point gate control ability, therefore only retains to close on and be located at list
Gate electrode part above 6 middle section of crystal silicon and remove the gate electrode part closed on positioned at 6 both ends upper of monocrystalline silicon, i.e.,
The control ability of gate electrode will not be reduced using 4 structure of folding I shape gate electrode proposed by the invention.This is allowed for using folding
It is same with FinFETs device can both to have guaranteed that device had for the grid-control field effect transistor of this structure of I shape gate electrode 4
Grid-control ability, and leakage current can be significantly reduced.
To reach device function of the present invention, this folding without knot with low current leakage proposed by the invention
I shape grid field effect transistor, nuclear structure feature are as follows:
1. being parallel to wafer substrate and along on from source electrode 1 to the rectilinear direction of drain electrode 2, I shape gate electrode is folded
4 length for being located at 6 upper section of monocrystalline silicon, which are less than, folds the length that I shape gate electrode 4 is located at 6 two side portions of monocrystalline silicon, entire to roll over
Folded I shape gate electrode 4 shows English capitalization " I " shape being folded, i.e., folding I shape gate electrode 4 is located at 6 top of monocrystalline silicon
Part constitutes the part of the centre " perpendicular " of alphabetical " I ", and folds I shape gate electrode 4 and be located at 6 two side portions of monocrystalline silicon and then respectively constitute
Two " cross " up and down of alphabetical " I ".It is vertical with two composed by the both ends of " perpendicular " respectively to fold I shape gate electrode about 4 two " cross "
End face is in the shape of a " convex ".
2. insulated from each other by gate medium insulating layer 5 between monocrystalline silicon 6 and folding I shape gate electrode 4, gate medium insulating layer 5
It is adapted with the shape for folding 4 inside of I shape gate electrode, gate medium insulating layer 5 also shows the English capitalization word that both ends are folded
Female " I " shape.Gate medium insulating layer 5 is located at the part that 6 upper section of monocrystalline silicon constitutes the centre " perpendicular " of alphabetical " I ", is located at
6 two side portions of monocrystalline silicon then respectively constitute two " cross " up and down of alphabetical " I "；Both ends of upper and lower two " cross " respectively with " perpendicular " are formed
Two perpendicular end surfaces it is in the shape of a " convex "；The part of " perpendicular " of protrusion is maked somebody a mere figurehead among it, and lower section penetrates monocrystalline silicon 6.
3. being located between the gate electrode 4 and source electrode 1 and drain electrode 2 of 6 upper surface of monocrystalline silicon through the exhausted of low-k
Edge layer is isolated from each other.
4. the present invention uses channel portion of N-type (or p-type) monocrystalline silicon 6 as device, entire channel is impuritiess of the same race
Type doping, the technology difficulty encountered when avoiding the PN junction in forming routine MOSFET.
Following further describes the present invention with reference to the drawings:
I shape grid field effect transistor is folded on soi substrates without knot with low current leakage if Fig. 1 is that the present invention is a kind of
The three dimensional structure diagram of formation；Fig. 2 is to fold I shape grid field effect transistor in SOI substrate without knot with low current leakage
The top view of upper formation；Fig. 3 is to fold I shape grid field effect transistor without knot with low current leakage with low current leakage
Three dimensional structure diagram after having removed the insulating medium layer 3 of device upper surface and surrounding；Fig. 4 is with low leakage electricity
Stream folds I shape grid field effect transistor bowing after having removed the insulating medium layer 3 of device upper surface and surrounding without knot
View；Fig. 5 is to remove device upper surface and surrounding without knot folding I shape grid field effect transistor with low current leakage
Insulating medium layer 3 after the sectional view that is cut along section A of three dimensional structure diagram；Fig. 6 is the nothing with low current leakage
Knot folds three-dimensional structure of the I shape grid field effect transistor after having removed the insulating medium layer 3 of device upper surface and surrounding
The sectional view that schematic diagram is cut along section B；The silicon substrate 8 of SOI wafer is specifically included, is SOI above the silicon substrate 8 of SOI wafer
The insulating layer 7 of wafer；It is monocrystalline silicon 6 above the insulating layer 7 of SOI wafer, the central location on the surface of monocrystalline silicon 6 has gate medium
Insulating layer 5 is isolated between adjacent monocrystalline silicon 6 by insulating medium layer 3；Have gate electrode 4, grid in 5 surface of gate medium insulating layer
4 top of electrode and surrounding have insulating medium layer 3, finally and etch away 6 both ends upper surface of monocrystalline silicon by etching technics
Insulating medium layer 3, and inject metal in the through-hole etched away and be generated as source electrode 1 and drain electrode 2 respectively；As Fig. 7 be with
Low current leakage without knot fold I shape grid field effect transistor the insulating medium layer 3 for having removed device upper surface and surrounding,
Three dimensional structure diagram after gate electrode 4；Fig. 8 is existing without knot folding I shape grid field effect transistor with low current leakage
The top view after the insulating medium layer 3 of device upper surface and surrounding, gate electrode 4 is removed；Fig. 9 is with low current leakage
Without knot fold I shape grid field effect transistor in insulating medium layer 3, the gate electrode 4, source for having removed device upper surface and surrounding
Three dimensional structure diagram after electrode 1, drain electrode 2；Figure 10 is to fold I shape gate field-effect crystalline substance without knot with low current leakage
Vertical view of the body pipe after having removed the insulating medium layer 3 of device upper surface and surrounding, gate electrode 4, source electrode 1, drain electrode 2
Figure；Figure 11 is to remove device upper surface and surrounding without knot folding I shape grid field effect transistor with low current leakage
Insulating medium layer 3, gate electrode 4, source electrode 1, drain electrode 2, the three dimensional structure diagram after gate medium insulating layer 5；Figure 12
To fold I shape grid field effect transistor in insulation Jie for having removed device upper surface and surrounding without knot with low current leakage
Top view after matter layer 3, gate electrode 4, source electrode 1, drain electrode 2, gate medium insulating layer 5；To enhance 4 pairs of lists of I shape gate electrode
The control ability of 6 internal electric field of crystal silicon, potential and Carrier Profile, gate insulating layer 5 can be the insulation with high dielectric constant
Material medium layer is also possible to common earth silicon material.
This unit and battle array that I shape grid field effect transistor is folded without knot with low current leakage proposed by the invention
The specific manufacturing technology steps of column are as follows:
Step 1: providing a SOI wafer adulterated, the lower section of SOI wafer is the silicon substrate 8 of SOI wafer, and SOI is brilliant
Circle top is the monocrystalline silicon thin film for being used to form monocrystalline silicon 6, is therebetween the insulating layer 7 of SOI wafer, passes through photoetching, etching
Etc. techniques a series of cuboids as shown in figs. 13 and 14 are formed on the insulating layer 7 of provided SOI wafer is monocrystalline silicon
6；
Step 2: after SOI wafer left-right parts are by deposit insulating medium layer, throwing flat surface as shown in Figure 15, Figure 16
Insulating medium layer 3 is formed, is used as being isolated between device cell；
Step 3: as shown in Figure 17, Figure 18, by depositing technics, Gao Jie will be deposited on the monocrystalline silicon thin film of rectangular-shape
The insulator of electric constant is processed by shot blasting as gate dielectric material, and to it；
Step 4:, by etching technics, the gate dielectric layer that previous step is deposited etches one as shown in Figure 19, Figure 20
It is a in terms of depression angle such as the shape of capital I, gate medium insulating layer 5 is generated with this；
Step 5: as shown in Figure 21, Figure 22, on the basis of the above-described procedure by deposit etching oxidation on gate dielectric layer 5
Object deposits metal again, forms gate electrode 4, polished surface；
Step 6: generating insulating layer for unit device by depositing technics on the basis of the above-described procedure as shown in Figure 23, Figure 24
Part is kept apart, surface polishing；
Step 7: as shown in Figure 25, Figure 26, in the both ends position of 3 upper surface of insulating medium layer on the basis of above-mentioned steps
Set by etching technics etch away the insulating medium layer 3 of 6 both ends upper surface of monocrystalline silicon with generation source, leakage through-hole, and respectively source,
It leaks and injects metal in through-hole to generate source electrode 1 and drain electrode 2, ultimately generate one kind proposed by the invention through the above steps
I shape grid field effect transistor is folded without knot with low current leakage.
Claims (3)
1. it is a kind of with low current leakage without knot fold I shape grid field effect transistor, the silicon substrate (8) including SOI wafer,
It is characterized in that: being the insulating layer (7) of SOI wafer above the silicon substrate (8) of SOI wafer, be above the insulating layer (7) of SOI wafer
Monocrystalline silicon (6) has gate medium insulating layer (5) on the surface of monocrystalline silicon (6), and gate medium insulating layer (5) surface is with folding I shape
Gate electrode (4), metal gate electrode are close to gate medium insulating layer (5)；The both ends of monocrystalline silicon (6) upper surface are respectively source electrode (1)
With drain electrode (2), it is isolated between adjacent single crystalline silicon (6) and by insulating medium layer (3) between source electrode (1) and drain electrode (2)
It opens；Injection metal point in the through-hole formed after insulating medium layer (3) of monocrystalline silicon (6) upper surface by two close end etches away will be attached to
It Sheng Cheng not source electrode (1) and drain electrode (2).
2. according to claim 1 fold I shape grid field effect transistor without knot with low current leakage, feature exists
In: in the silicon substrate for being parallel to SOI wafer and along in the rectilinear direction from source electrode (1) to drain electrode (2), fold I shape grid
The length that electrode (4) is located at monocrystalline silicon (6) upper section is less than folding I shape gate electrode (4) and is located at monocrystalline silicon (6) two side portions
Length, entire fold I shape gate electrode (4) show English capitalization " I " shape being folded, i.e. folding I shape gate electrode (4)
The part of the centre " perpendicular " of alphabetical " I " is constituted positioned at monocrystalline silicon (6) upper section, and is folded I shape gate electrode (4) and be located at monocrystalline silicon
(6) two side portions then respectively constitute two " cross " up and down of alphabetical " I "；Fold I shape gate electrode (4) up and down two " cross " respectively with " perpendicular "
Both ends composed by two perpendicular end surfaces it is in the shape of a " convex ".
3. according to claim 1 fold I shape grid field effect transistor without knot with low current leakage, feature exists
In: it is insulated from each other to pass through gate medium insulating layer (5) between monocrystalline silicon (6) and folding I shape gate electrode (4)；Gate medium insulating layer (5)
It is adapted with the shape folded on the inside of I shape gate electrode (4), it is big that gate medium insulating layer (5) also shows the English that both ends are folded
Female " I " shape of writing is located at monocrystalline silicon positioned at the part of the centre " perpendicular " of monocrystalline silicon (6) upper section composition alphabetical " I "
(6) two side portions then respectively constitute two " cross " up and down of alphabetical " I "；Upper and lower two " cross " are respectively and two composed by the both ends of " perpendicular "
A perpendicular end surface is in the shape of a " convex "；The part of " perpendicular " of protrusion is maked somebody a mere figurehead among it, and lower section penetrates monocrystalline silicon (6).
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103367442A (en) * | 2012-03-28 | 2013-10-23 | 台湾积体电路制造股份有限公司 | Gate stack of fin field effect transistor |
| CN103730505A (en) * | 2012-10-15 | 2014-04-16 | 德州仪器公司 | I-shaped gate electrode for improved sub-threshold MOSFET performance |
| CN104485354A (en) * | 2014-12-08 | 2015-04-01 | 沈阳工业大学 | SOI (Silicon on Insulator) substrate folding grid insulating tunneling enhanced transistor and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103367442A (en) * | 2012-03-28 | 2013-10-23 | 台湾积体电路制造股份有限公司 | Gate stack of fin field effect transistor |
| CN103730505A (en) * | 2012-10-15 | 2014-04-16 | 德州仪器公司 | I-shaped gate electrode for improved sub-threshold MOSFET performance |
| CN104485354A (en) * | 2014-12-08 | 2015-04-01 | 沈阳工业大学 | SOI (Silicon on Insulator) substrate folding grid insulating tunneling enhanced transistor and manufacturing method thereof |
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Effective date of registration: 20201228 Address after: Susong Xinqu Photoelectric Technology Co., Ltd., Jiumiao village, Qianling Township, Susong County, Anqing City, Anhui Province Patentee after: Susong Xinqu Photoelectric Technology Co., Ltd Address before: 110870 No. 111 Shenyang West Road, Shenyang economic and Technological Development Zone, Liaoning Patentee before: SHENYANG University OF TECHNOLOGY |