CN106653746A - Array substrate and display device - Google Patents
Array substrate and display device Download PDFInfo
- Publication number
- CN106653746A CN106653746A CN201611158777.6A CN201611158777A CN106653746A CN 106653746 A CN106653746 A CN 106653746A CN 201611158777 A CN201611158777 A CN 201611158777A CN 106653746 A CN106653746 A CN 106653746A
- Authority
- CN
- China
- Prior art keywords
- metal
- cylindrical hole
- base palte
- array base
- contact wires
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 109
- 229910052751 metal Inorganic materials 0.000 claims abstract description 109
- 238000000034 method Methods 0.000 claims abstract description 29
- 230000002093 peripheral effect Effects 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 8
- 230000004888 barrier function Effects 0.000 claims description 16
- 239000011521 glass Substances 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 238000009413 insulation Methods 0.000 claims 1
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 9
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 230000003068 static effect Effects 0.000 abstract description 5
- 230000005611 electricity Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 8
- 239000010409 thin film Substances 0.000 description 4
- -1 GND metals Chemical class 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000003472 neutralizing effect Effects 0.000 description 1
- 239000011513 prestressed concrete Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
The invention relates to the field of manufacturing of an In-Cell touch control panels. The array substrate provided by the invention comprises a data line layer and GND metal wiring arranged along the peripheral edge of the array substrate, wherein each two adjacent data lines in the data line layer is connected through a first metal connection line; the data line located at the outermost side is connected with the GND metal wiring through a second metal connection line; and thus, static electricity generated during the array substrate process can be quickly spread along the data line metal net and flow to the ground through the GND metal wiring, harms generated by the static electricity can be eliminated, and the product yield during the process can be improved to a certain degree. During the subsequent array substrate process, the first metal connection line and the second metal connection line can be completely cut off through an etching technology, and normal display of a liquid crystal panel can be ensured. The invention also provides a display device comprising the array substrate.
Description
Technical field
The present invention relates to In-Cell contact panels manufacture field, more particularly to a kind of array base palte and display device.
Background technology
In liquid crystal display manufacture process, such as all can in drying, etching, alignment film friction, cutting and carrying technique
Cause the generation of electrostatic.Static discharge may puncture insulating barrier causes double layer of metal directly to turn on, so as to directly affect
The yield of production liquid crystal panel.Static discharge is a kind of accumulation of static electricity, the phenomenon of electrostatic charge transfer release between different objects.
The time of Electro-static Driven Comb is very short, typically only nano-scale.Electrostatic discharges within the so short time can produce very big wink
Between electric current, so high electric current causes circuit cisco unity malfunction by burning device during integrated circuit.Therefore, exist
The generation of minimizing electrostatic can be gone with some such as ion blower equipment in semiconductor manufacturing, or be arranged in the fabrication process
Electrostatic discharge protection circuit, so as to be conducive to the diffusion of electrostatic, prevents the problem that electrostatic be wound, and then improves product yield.
The making technology of In-Cell contact panels is complicated and yields is relatively low, and in In-Cell contact panels array is included
Substrate, the gate line and data wire of the ground configuration definition pixel region that intersects in array base palte, configures in each pixel region
Pixel electrode and thin film transistor (TFT).Traditional array base palte manufacture is reached using the Electro-static Driven Comb ring design method of thin film transistor (TFT)
To the effect for destaticing, this neutralizing method must could be realized after thin film transistor (TFT) is molded completely, and in film crystal
Electrostatic can not be still removed in the formation processing procedure of pipe, causes in the processing procedure electric charge on substrate to add up, be wound with other layer of electrostatic, be reduced
The yields of processing procedure.
The content of the invention
In order to solve the problems, such as that array base palte thin film transistor (TFT) forms the electrostatic hazard in processing procedure, the present invention proposes a kind of array
Substrate.
Array base palte proposed by the present invention, be disposed with glass substrate, gate line layer, the first insulating barrier, data line layer,
Second insulating barrier, the 3rd insulating barrier, the 3rd metal level.
The array base palte includes that pixel region, outer peripheral areas and the GND metals along the setting of array substrate peripheral edge are walked
Line, wherein, the outer peripheral areas include the region between the outward flange of the pixel region and GND metal routings.
A plurality of data lines is provided with the data line layer, the pixel region is both passed through per data wire described in bar, per bar
The two ends of the data wire are respectively positioned in the outer peripheral areas, and in the outer peripheral areas, two adjacent data wires lead to
Cross the first metal contact wires to be connected, first metal contact wires are arranged in the data line layer.
Because adjacent data line is connected by the first metal contact wires so that all of data wire is linked as a wire netting,
When there is electrostatic to produce in processing procedure, electrostatic can prevent electrostatic charge from adding up to cause by the data wire metal net quick release
Harm.
As to further improvement of the present invention, in the outer peripheral areas, positioned at outermost two data wires
Two ends be connected with GND metal routings by the second metal contact wires respectively, second metal contact wires are arranged at institute
In stating data line layer.
Data wire metal net is further connected with GND metal routings, the online electrostatic of data wire metal can be passed through into GND
Metal routing is discharged into the earth, eliminates electrostatic hazard
In one embodiment, second metal contact wires connect respectively positioned at outermost two data line and with institute
The GND metal routing line segments of the opposing parallel setting of data wire are stated, this structure can ensure that the second metal contact wires linearly connect
Connect, it is to avoid electrostatic charge is accumulated around the corner so that electrostatic charge is quickly through GND metal routings flow direction the earth.
Due to when liquid crystal panel normally shows, between data wire can not short circuit, data wire can not be with GND metal routings
Short circuit, so in array base palte processing procedure, when making the second insulating barrier, the top of first metal contact wires, described the
The first cylindrical hole is provided with above two metal contact wires, when three insulating barriers is made, in the upper of first cylindrical hole
Side is provided with the second cylindrical hole, the center overlapping of axles of the central shaft of first cylindrical hole and second cylindrical hole, and described
The aperture of the second cylindrical hole is equal to the aperture of the first cylindrical hole.Here, it is desirable to the central shaft of the second cylindrical hole and the first cylinder
The center overlapping of axles in hole and the aperture of the second cylindrical hole are equal to the aperture of the first cylindrical hole, when three metal levels is made, can be square
Just the 3rd metal level is made to connect with the first metal contact wires or the second metal contact wires.
As the aperture to further improvement of the present invention, the aperture of the first cylindrical hole or the second cylindrical hole more than described the
The trace width of one metal contact wires, and the aperture of the aperture of the first cylindrical hole or the second cylindrical hole is more than second metal
The trace width of connecting line.
When three metal levels is made, the 3rd metal level is connected by the second cylindrical hole and the first cylindrical hole with the first metal
Line or the second metal contact wires connect, then by etching technique that the metal at the second cylindrical hole and below the second cylindrical hole is complete
Etch away entirely, until the first metal contact wires, the second metal contact wires are fully disconnected, so as to ensure the normal aobvious of liquid crystal panel
Show.
The invention allows for a kind of display device, the display device includes above-described array base palte.
Array base palte proposed by the present invention, in the processing procedure of array base palte, the electrostatic that pixel region is formed can be by connection
Data wire for wire netting quickly spreads, and prevents electrostatic charge from adding up, and the electrostatic charge for spreading apart is further by array base palte outside
The GND metal routings flow direction the earth of edge, eliminates the electrostatic in array base palte processing procedure, and the good of product is improve to a certain extent
Rate, due to when liquid crystal panel normally shows, between data wire can not short circuit, data wire can not with the short circuit of GND metal routings,
So in the successive process of array base palte processing procedure, using etching technique by the metal contact wires between data wire, data wire with
Metal contact wires between GND metal routings are fully disconnected, it is ensured that the normal display of liquid crystal panel.
Description of the drawings
Hereinafter the present invention will be described in more detail based on embodiment and refer to the attached drawing.Wherein：
Fig. 1 is the section partial schematic diagram (making before third layer metal) of array base palte in the present invention；
Fig. 2 is the section partial schematic diagram (before third layer metal etch) of array base palte in the present invention；
Fig. 3 is the section partial schematic diagram (after third layer metal etch) of array base palte in the present invention；
Fig. 4 is that the schematic top plan view that array base palte is observed along normal direction in the present invention is (main to show making third layer gold
Category previous gate line layer, data line layer, the connection diagram of GND metal routings)；
Fig. 5 is that the schematic top plan view that array base palte is observed along normal direction in the present invention is (main to show the erosion of third layer metal
Carve post tensioned unbonded prestressed concrete line layer, data line layer, the connection diagram of GND metal routings)；
In the accompanying drawings, identical part uses identical reference.Accompanying drawing is not according to actual ratio.
Specific embodiment
Describe the specific embodiment of the present invention in detail below in conjunction with drawings and Examples.
Depending on upper and lower, left and right, top, bottom, left part, right part hereinafter is both with respect to figure direction, should not constitute
Limitation of the present invention.
Fig. 1 show array base palte of the present invention make third layer metal before partial cutaway schematic, from bottom to top according to
It is secondary including glass substrate 1, gate line layer 2, the first insulating barrier 3, data line layer 4, the second insulating barrier 5, the 3rd insulating barrier 6, wherein,
Comprising some data lines 40 and positioned at outermost data wire 401 and data wire 402 in data line layer 4, wrap in gate line layer 2
Containing some gate lines 20 and positioned at outermost data wire 201 and data wire 202.Normal direction along array base palte is observed,
If Fig. 4 is the schematic diagram of the direction, Fig. 4 mainly shows making third layer metal previous gate line layer, data line layer, GND metals
The connection diagram of cabling, the array base palte includes pixel region 4020, outer peripheral areas 4008 and along array substrate peripheral edge
The GND metal routings of setting, in the diagram, GND metal routings include line segment 8, line segment 81 and line segment 82, pixel region 4020 by
Outermost data wire 401, outermost data wire 402, outermost gate line 201, outermost gate line 202 are surrounded
Form, outer peripheral areas 4008 include the region between the outward flange of pixel region 4020 and GND metal routings.It is equal per data line 40
Through pixel region 4020, the upper area and lower area in peripherally located region 4008 are distinguished in the two ends of data wire 40.
In outer peripheral areas 4008, two adjacent data lines are connected by the first metal routing 411, it is preferable that
The upper area and lower area of outer peripheral areas 4008 is provided with the first metal routing 411, it is preferable that the first metal routing
411 are arranged in data line layer 4, so as to the top and bottom per two adjacent data lines pass through the first metal routing 411
It is connected, forms a data wire wire netting, the electrostatic produced in array base palte processing procedure can be fast by the data wire metal net
Speed diffusion, prevents electrostatic charge from adding up to work the mischief.
In this embodiment, it is preferred that, distinguish positioned at the top and bottom of outermost data wire 401 and data wire 402
It is connected with GND metal routings by the second metal routing 412, the second metal routing 412 preferably connection data wire in left side
401 and it is opposing parallel with data wire 401 and near data wire 401 GND metal routings line segment 81, second metal routing on right side
412 preferably connect data wire 402 and GND metal routing line segments opposing parallel with data wire 402 and near data wire 402
82, the second metal routing 412 is preferably linearly connection, and the second metal routing 412 is preferably located in data line layer 4.It is this
Set-up mode so that data wire metal net is connected with GND metal routings, can be such that the electrostatic on data wire walks by GND metals
Line flow direction the earth, so as to eliminate array base palte processing procedure in produce electrostatic.
Due to when liquid crystal panel normally shows, between data wire can not short circuit, data wire can not be with GND metal routings
Short circuit, so in the processing procedure of array base palte, such as Fig. 1 after the data line layer that completes 4, makes the second insulating barrier 5, is making
After second insulating barrier 5, in the surface of the surface of the first metal routing 411 and the second metal routing 412 by etching skill
Art etches the first cylindrical hole 51, the 3rd insulating barrier 6 is then made, again by etching technique just going up in the first cylindrical hole 51
Side etches and the second cylindrical hole of aperture identical 61 of the first cylindrical hole 51, it is preferable that the central shaft of the second cylindrical hole 61 and the
The center overlapping of axles of one cylindrical hole 51.Then the 3rd metal level 7 is made, the 3rd metal level 7 is justified by the second cylindrical hole 61, first
Post holes 51 connects respectively with the first metal routing 411 or the second metal routing 412, as shown in Fig. 2 in actual production technique,
For the spreadability of the 3rd metal level 7 of needs and raising of technique, the first cylindrical hole 51, the second cylindrical hole 61 are made into successively
The bellmouth for gradually increasing from bottom to top of stacking, is so advantageous for the 3rd metal level completely by the first cylindrical hole 51 and second
Cylindrical hole 61 is completely covered, and then by etching technique, metal at the second cylindrical hole 61 and below is fully etched, such as
Shown in Fig. 3, so as to completely disconnect the first metal routing 411, while the second metal routing 412 is disconnected completely so that adjacent
Data wire disconnect, data wire 401 is disconnected with GND metal routings line segment 81, data wire 402 and GND metal routings
Line segment 82 is disconnected, and obtains effect as shown in Figure 5, this ensures that theres the normal display of liquid crystal panel.
Display device proposed by the present invention, including array base palte proposed by the present invention.
Finally illustrate, above example is merely to illustrate technical scheme and unrestricted, although with reference to compared with
Good embodiment has been described in detail to the present invention, it will be understood by those within the art that, can be to the skill of the present invention
Art scheme is modified or equivalent, and without deviating from the objective and scope of technical solution of the present invention, it all should cover at this
In the middle of the right of invention.
Claims (9)
1. a kind of array base palte, is disposed with glass substrate, gate line layer, the first insulating barrier, data line layer, the second insulation
Layer, the 3rd insulating barrier, the 3rd metal level,
The GND metal routings that the array base palte includes pixel region, outer peripheral areas and arranges along array substrate peripheral edge, its
In,
The outer peripheral areas include the region between the outward flange of pixel region and GND metal routings,
A plurality of data lines is provided with the data line layer, the pixel region is both passed through per data wire described in bar, per described in bar
The two ends of data wire are respectively positioned in the outer peripheral areas,
In the outer peripheral areas, two adjacent data wires are connected by the first metal contact wires.
2. array base palte according to claim 1, it is characterised in that first metal contact wires are arranged at the data
In line layer.
3. array base palte according to claim 2, it is characterised in that in the outer peripheral areas, positioned at outermost two
Two ends of data wire described in bar are connected respectively by the second metal contact wires with GND metal routings.
4. array base palte according to claim 3, it is characterised in that second metal contact wires are arranged at the data
In line layer.
5. array base palte according to claim 4, it is characterised in that second metal contact wires connect the data wire
And the GND metal routing line segments with the opposing parallel setting of the data wire.
6. the array base palte according to any one of Claims 1 to 4, it is characterised in that in array base palte processing procedure, makes the
During two insulating barriers, is provided with directly over the surface of first metal contact wires, second metal contact wires
One cylindrical hole, when three insulating barriers is made, in second cylindrical hole that is arranged above of first cylindrical hole, described second
The center overlapping of axles of the central shaft of cylindrical hole and first cylindrical hole, the aperture of second cylindrical hole and first cylinder
The aperture in hole is equal.
7. array base palte according to claim 6, it is characterised in that the aperture of first cylindrical hole or second circle
The aperture of post holes is more than the trace width of first metal contact wires, the aperture of first cylindrical hole or second cylinder
Trace width of the aperture in hole more than second metal contact wires.
8. array base palte according to claim 7, it is characterised in that when three metal levels is made, the 3rd metal level leads to
Cross the second cylindrical hole and the first cylindrical hole connects with the first metal contact wires or the second metal contact wires, then by etching technique
Metal at second cylindrical hole and below second cylindrical hole is fully etched, until the first metal contact wires, the second gold medal
Category connecting line is fully disconnected.
9. a kind of display device, it is characterised in that comprising the array base palte described in any one of claim 1～8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611158777.6A CN106653746B (en) | 2016-12-15 | 2016-12-15 | A kind of array substrate and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611158777.6A CN106653746B (en) | 2016-12-15 | 2016-12-15 | A kind of array substrate and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106653746A true CN106653746A (en) | 2017-05-10 |
| CN106653746B CN106653746B (en) | 2019-09-06 |
Family
ID=58823628
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611158777.6A Active CN106653746B (en) | 2016-12-15 | 2016-12-15 | A kind of array substrate and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106653746B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107275328A (en) * | 2017-07-25 | 2017-10-20 | 武汉华星光电技术有限公司 | A kind of array base palte and a kind of display device |
| CN108508664A (en) * | 2018-03-28 | 2018-09-07 | 深圳市华星光电技术有限公司 | The production method of array substrate |
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| CN104297967A (en) * | 2014-10-16 | 2015-01-21 | 昆山龙腾光电有限公司 | Arrayed mother substrate and heating device thereof |
| CN104900589A (en) * | 2015-06-16 | 2015-09-09 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof, and display device |
| CN104965369A (en) * | 2015-07-28 | 2015-10-07 | 深圳市华星光电技术有限公司 | Array substrate, display panel and display device |
| CN105097847A (en) * | 2015-09-15 | 2015-11-25 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
-
2016
- 2016-12-15 CN CN201611158777.6A patent/CN106653746B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104297967A (en) * | 2014-10-16 | 2015-01-21 | 昆山龙腾光电有限公司 | Arrayed mother substrate and heating device thereof |
| CN104900589A (en) * | 2015-06-16 | 2015-09-09 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof, and display device |
| CN104965369A (en) * | 2015-07-28 | 2015-10-07 | 深圳市华星光电技术有限公司 | Array substrate, display panel and display device |
| CN105097847A (en) * | 2015-09-15 | 2015-11-25 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107275328A (en) * | 2017-07-25 | 2017-10-20 | 武汉华星光电技术有限公司 | A kind of array base palte and a kind of display device |
| WO2019019437A1 (en) * | 2017-07-25 | 2019-01-31 | 武汉华星光电技术有限公司 | Array substrate and display device |
| CN107275328B (en) * | 2017-07-25 | 2020-07-31 | 武汉华星光电技术有限公司 | Array substrate and display device |
| CN108508664A (en) * | 2018-03-28 | 2018-09-07 | 深圳市华星光电技术有限公司 | The production method of array substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106653746B (en) | 2019-09-06 |
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