CN106652881B - A kind of display module and its driving method - Google Patents
A kind of display module and its driving method Download PDFInfo
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- CN106652881B CN106652881B CN201710150191.3A CN201710150191A CN106652881B CN 106652881 B CN106652881 B CN 106652881B CN 201710150191 A CN201710150191 A CN 201710150191A CN 106652881 B CN106652881 B CN 106652881B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The present invention provides a kind of display module and its driving method, the display module includes control printed circuit board, data drive circuit, first grid driving circuit and second grid driving circuit, it is provided with detection unit in second grid driving circuit, whether the gating transistor for detecting close second grid driving circuit side is normally-open.The described method comprises the following steps: in the first gating period t1, first grid driving circuit exports open signal V1 to grid line part；Whether the gating transistor that the detection unit of second grid driving circuit is detected close to second grid driving circuit side is normally-open；If normally-open, in the second gating period t2, first grid driving circuit continues offer open signal V1 and is driven；If abnormal unlatching, in the second gating period t2, first grid driving circuit stops providing open signal, while second grid driving circuit provides open signal V2 and driven, with normally-open gating transistor.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of display module and its driving methods.
Background technique
Display module basic functional principle is: be provided with criss-cross grid line and data line in array substrate, grid line and
Data line surrounds pixel, and gating transistor and pixel electrode are provided in pixel, and a grid line controls a line gating transistor
It opens, and then whether determination data line charges to the pixel electrode of the row pixel, therefore, in order to drive display device, battle array
It needs that gate driving circuit and source electrode drive circuit is arranged on column substrate, wherein gate driving circuit drives to grid line output grid
Dynamic signal, source electrode drive circuit is to data line outputting data signals.
Currently, display device just develops towards the direction of large scale, high-res, the gating that a grid line needs to control is brilliant
Body pipe is more and more, in order to avoid the cut-in voltage apart from the farther away gating transistor of gate driving circuit is insufficient, such as discloses
Number be CN101202024A patent application, as shown in Figure 1, display device include be located at grid line both ends two grids drive
Dynamic circuit, two gate driving circuits export identical gate drive signal from two sides to a grid line simultaneously, and then ensure that
The grid line control all gating transistors it is normally-open.
But for large scale, the display device of high-res, the resistance such as grid line, data line and public electrode wire compared with
Greatly, the coupled capacitor and between grid line, data line and public electrode is larger, when two gate driving circuits drive a grid simultaneously
When line, a line gating transistor is opened simultaneously, and one-row pixels electrode charges simultaneously, can largely pull public electrode
Voltage, and then the virtual voltage being applied in pixel is influenced, it is bad to be easy to appear image retention, crosstalk etc..
To solve the above problems, the patent application of Publication No. CN104318890A provides a kind of array substrate, such as Fig. 2 institute
Show, a plurality of grid line is provided in the array substrate, and the grid line both ends are separately connected first grid driving circuit and second gate
Pole driving circuit, which is characterized in that every grid line is divided into the first grid line portion connecting with the first grid driving circuit
The the second grid line part divided and connect with the second grid driving circuit, first grid line part and second grid line portion
/ it is provided with switch element.The gating transistor for avoiding same grid line from controlling is synchronous to open, and then reduces to common electrical
The pulling of pole tension, meanwhile, the route of single-sided gate driving circuit driving is unlikely to too long.
But above-mentioned patent application has problems in that due to being provided between the first grid line part and the second grid line part
Switch element also increases array basic volume and cost so that display area wiring is more complicated.
Another needs the problem of paying close attention to be, due to display module itself temperature can with continuing for working time and
It changes, so that the power supply unit output voltage signal in display module inevitably drifts about, and also will affect
To the normally-open of gating transistor, to reduce display quality.
Summary of the invention
In order to solve the above technical problems, the present invention provides a kind of display module comprising control printed circuit board, data are driven
Circuit, first grid driving circuit and second grid driving circuit are moved, is provided with detection in the second grid driving circuit
Unit, whether there is or not normally-open for the gating transistor for detecting close second grid drive circuit module side.
Be equipped on the control printed circuit board sequence controller, the first level converter and second electrical level converter,
And power supply unit, when the first grid driving circuit and second grid driving circuit are connected to by data drive circuit
Sequence controller and power supply unit, or sequence controller and power supply unit are directly connected to by flexible printed circuit board.
First level converter and second electrical level converter pass through data drive circuit and the pulse of generation are supplied to first
Gate driving circuit and second grid driving circuit, first grid driving circuit export first grid pulse CKV1, second grid
Driving circuit exports second grid pulse CKV2, and first grid pulse CKV1 has the open signal V1 that gating transistor is connected
There is the open signal V2 and cut-off signals V0 that gating transistor is connected with cut-off signals V0, second grid pulse CKV2,
In, V2 is greater than or equal to V1.
In the first gating period t1 of gating period T, first grid driving circuit 130 exports first grid pulse CKV1
Open signal V1 to grid line part；The detection unit of second grid driving circuit 140 is detected close to second grid driving circuit
Whether the gating transistor of 140 sides is normally-open；If normally-open, in the second gating period t2 of gating period T,
First grid driving circuit 130 continues offer open signal V1 and is driven, otherwise, in the second gating period of gating period T
In t2, first grid driving circuit 130 stops providing open signal, while second grid driving circuit 140 provides second grid
The open signal V2 of pulse CKV2 is driven.
First gating period t1 and the second gating period t2 is equal or the second gating period t2 is than the first gating period t1
Greatly.
Voltage regulator circuit is set in the power supply unit, comprising: bipolar junction transistor Q1, Q2, Q3；PMOS transistor M30,
M31,M32,M33；NMOS transistor M40, M41；Resistance R1, R2, R3, R4, R41；Operational amplifier A1, buffer B1, B2；Electricity
Hold Cc；
Wherein, the source electrode of PMOS transistor M30, M31, M32, M33 connects supply voltage VDD, the grid of PMOS transistor M30
Pole connects the grid of PMOS transistor M31, M32, M33, the emitter and resistance of the drain electrode connection transistor Q1 of transistor M30
One end of R1, one end of the other end connection resistance R2 of resistance R1 and the input terminal of buffer B1, the output end of buffer B1
Connect the base stage of transistor Q1, Q2, the other end of resistance R2 and the grounded collector of transistor Q1；
The emitter of the drain electrode connection transistor Q2 of PMOS transistor M31 and the inverting input terminal of operational amplifier A1,
The grounded collector of transistor Q2；The grid of the output end connection transistor M31 of operational amplifier A1, operational amplifier A1 is just
The grid of phase input terminal connection NMOS transistor M41；
The grid of the drain electrode connection transistor M32 of NMOS transistor M40, the grid connection resistance R41's of transistor M40 is another
The drain electrode of one end and transistor M41, the source electrode ground connection of transistor M40；The transmitting of the drain electrode connection transistor Q3 of transistor M32
Pole, the output end of the base stage connection buffer B2 of transistor Q3, the grounded collector of transistor Q3；One end of resistance R41 connects
Supply voltage VDD, the other end connect the drain electrode of transistor M41, the source electrode ground connection of transistor M41；
One end of capacitor Cc connects supply voltage VDD, and the other end connects the grid of transistor M33, the source electrode of transistor M33
Connect supply voltage VDD, one end of drain electrode connection resistance R3, and the output end as voltage regulator circuit；The other end of resistance R3 connects
Connect the input terminal of buffer B2 and one end of resistance R4, the other end ground connection of resistance R4.
Buffer B1, B2 be low output impedance unity gain buffer, buffer circuits include PMOS transistor M1, M2,
M5,M7；NMOS transistor M3, M4, M6, M8, Ms1；Resistance R8, capacitor Cc1；
Wherein one end of the source electrode of transistor M5, M7 and resistance R8 connect supply voltage VDD, and the grid of transistor M5 connects
The grid of transistor M7, the source electrode of drain electrode connection transistor M1, M2 of transistor M5 are connect, the grid of transistor M1 connects transistor
The grid of Ms1 and the other end of resistance R8, and the output end as buffer；The drain electrode connection transistor M3's of transistor M1
Drain electrode and grid, the grid of the grid connection transistor M4 of transistor M3, the source electrode ground connection of transistor M3, M4；
Transistor M2 grid connects the source electrode of transistor Ms1, and the input terminal as buffer, and the drain electrode of transistor M2 connects
Connect the drain electrode of transistor M4 and the grid of transistor M6, M8；
The grid of transistor M7 connects its drain electrode, the drain electrode of the drain electrode connection transistor Ms1 of transistor M7 and transistor
The drain electrode of M6, one end of the grid connection capacitor Cc1 of transistor M6, the other end of capacitor Cc1 and the source electrode of transistor M6 connect
Ground；The source electrode of transistor M8 is grounded, the other end of drain electrode connection resistance R8 and the grid of transistor Ms1.
The present invention also provides a kind of driving method of display module, the display module includes control printed circuit board, number
According to driving circuit, first grid driving circuit and second grid driving circuit, it is characterised in that: the second grid driving
Detection unit is provided in circuit, whether there is or not normal for the gating transistor for detecting close second grid drive circuit module side
It opens, first grid driving circuit exports first grid pulse CKV1, and second grid driving circuit exports second grid pulse
CKV2, first grid pulse CKV1 have the open signal V1 and cut-off signals V0 that gating transistor is connected, second grid arteries and veins
Rushing CKV2 has the open signal V2 and cut-off signals V0 that gating transistor is connected, and the described method comprises the following steps:
S101: in the first gating period t1 of gating period T, first grid driving circuit 130 exports first grid arteries and veins
The open signal V1 of CKV1 is rushed to grid line part；
S102: the detection unit of second grid driving circuit detects the gating crystal close to second grid driving circuit side
It whether normally-open manages；If normally-open, S103 is turned to, otherwise, turns to S104；
S103: in the second gating period t2 of gating period T, first grid driving circuit continues to provide open signal V1
It is driven；
S104: in the second gating period t2 of gating period T, first grid driving circuit stops providing open signal,
The open signal V2 that second grid driving circuit provides second grid pulse CKV2 simultaneously is driven, brilliant with normally-open gating
Body pipe.
V2 is greater than or equal to V1.
First gating period t1 and the second gating period t2 is equal or the second gating period t2 is than the first gating period t1
Greatly.
Driving mould group provided by the present invention detects gating crystalline substance by the way that detection unit is arranged in second grid driving circuit
Whether body pipe is normally-open, to decide whether to provide open signal from second grid driving circuit to grid line.In second grid
When driving circuit provides open signal to grid line, due to the progressive attenuating of open signal V1, so that open signal V2's opens
The ability of opening is enhanced, to improve the unlatching effect of gating transistor under the premise of not increasing display area circuit burden.
In addition, the effect of the voltage regulator circuit due to power supply unit, the voltage signal that power supply unit is exported is not by temperature change
Interference, to reduce the influence opened to transistor.
Detailed description of the invention
Fig. 1 is 1 display module schematic diagram of the prior art；
Fig. 2 is 2 display module schematic diagram of the prior art；
Fig. 3 is that the invention shows mould group schematic diagrames；
Fig. 4 is that the invention shows module unit driving method flow charts；
Fig. 5 is that the invention shows mould group power supply unit voltage regulator circuit figures；
Fig. 6 is that the invention shows mould group power supply unit voltage regulator circuit buffer circuits figures.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are some of the embodiments of the present invention, instead of all the embodiments.Based on this hair
Embodiment in bright, every other implementation obtained by those of ordinary skill in the art without making creative efforts
Example, shall fall within the protection scope of the present invention.
Embodiment one
Embodiment one provides a kind of display module and its driving method, can reduce under the premise of not increasing hardware burden
Pulling to public electrode voltages simultaneously guarantees the normally-open of gating transistor.
As shown in figure 3, the display module includes control printed circuit board 104, data drive circuit 120, first grid drive
Dynamic circuit 130 and second grid driving circuit 140.
Sequence controller 170, the first level converter 150 and second electrical level converter 160, power supply unit 180 are mounted
On control printed circuit board 104.The control printed circuit board 104 is connected to TFT base through flexible printed circuit board 102
Bottom.The first grid driving circuit 130 and second grid driving circuit 140 for being set to LCD panel 110 are by data-driven electricity
Road 120 is connected to sequence controller 170 and power supply unit 180, or can be connected directly by flexible printed circuit board 102
To sequence controller 170 and power supply unit 180.
Sequence controller 170 is supplied to enable signal OE, gate clock signal CVP and grid initial signal STV is exported
Each of first level converter 150 and second electrical level converter 160.Moreover, sequence controller 170 adjusts load signal
(TP) timing is then provided to data drive circuit 120.Meanwhile by power supply unit 180 to the first level converter
150 and second electrical level converter 160 gate-on voltage V as grid line driving voltage is providedONAnd grid cut-off voltage
VOFF, and sequence controller 170 is also provided to the first level converter 150 and second electrical level converter 160 and is controlled as grid
Output enable signal OE, the gate clock signal CPV and gated sweep initial signal STV of signal.First level converter, 150 He
Second electrical level converter 160 generates the corresponding initial pulse converted between gate-on voltage and the level of grid cut-off voltage
STVP, first grid pulse CKV1 and second grid pulse CKV2.Then, the first level converter 150 and second electrical level transformation
The pulse of generation is supplied to first grid driving circuit 130 by data drive circuit 120 for device 160 and second grid drives electricity
Road 140.
Grid initial signal STV is the signal for indicating the starting of a frame.Initial pulse STVP is for making gate driving
Circuit 130 or 140 generates the signal of first gate driving signal in a frame.First grid pulse CKV1, which has, can make gating brilliant
The open signal V1 and cut-off signals V0 of body pipe conducting, second grid pulse CKV2 have the unlatching that gating transistor can be made to be connected
Signal V2 and cut-off signals V0, wherein V1 can be equal with V2.
In addition, detection unit is integrated in second grid drive circuit module, for detecting close to second grid driving electricity
Whether there is or not normally-open for the gating transistor of road module side.
The driving method of the display module is as follows:
S101: in the first gating period t1 of gating period T, first grid driving circuit 130 exports first grid arteries and veins
The open signal V1 of CKV1 is rushed to grid line part；
S102: the detection unit of second grid driving circuit 140 detects the choosing close to 140 side of second grid driving circuit
Whether logical transistor is normally-open；If normally-open, S103 is turned to, otherwise, turns to S104；
S103: in the second gating period t2 of gating period T, first grid driving circuit 130, which continues to provide, opens letter
Number V1 is driven；
S104: in the second gating period t2 of gating period T, first grid driving circuit 130, which stops providing, opens letter
Number, while the open signal V2 of the offer of second grid driving circuit 140 second grid pulse CKV2 is driven, with normally-open
Gating transistor.
In the driving method of the display module, when first grid driving circuit 130 being capable of normally-open display area
When all gating transistors, second grid drive circuit works are not needed, only when detection unit is detected close to second
The gating transistor of 140 side of gate driving circuit is just mentioned by second grid driving circuit 140 there are in the case where abnormal unlatching
For second grid pulse CKV2.While second grid driving circuit 140 works, stop first grid driving circuit 130
Work.When first grid driving circuit 130 stops providing first grid pulse CKV1 to grid line, due to gating transistor itself
Parasitic capacitance provided so that signal will not decay to cut-off signals immediately at this point, being equivalent to for second grid pulse CKV2
Precharge enhances the ability that second grid pulse CKV2 opens gating transistor, enables gating transistor normally-open.
Gating period T is referred in a frame, in order to open the gating transistor on certain grid line, and by gate driving
Circuit provides the period of open signal, and in the present embodiment, T is made of t1 and t2, and t1 and t2 is continuous time period, is shown
Meaning property, the first gating period t1 and the second gating period t2 can respectively account for the half or the second gating period of gating period T
T2 is bigger than the first gating period t1, for example t2 is 0.6T, t1 0.4T.
It will be apparent to those skilled in the art that V2 can also be greater than V1, to be further ensured that the just normally opened of gating transistor
It opens.
Wherein detection unit can be means whether any detectable gating transistor in this field is opened, itself structure
It is not emphasis of the present invention, does not describe excessively.
Further, the open signal of gating transistor and the size of cut-off signals can be according to the V-I of gating transistor
Characteristic is selected.In addition, showing thin film transistor (TFT) due to being provided with display thin film transistor (TFT) in the pixel in array substrate
Open signal and cut-off signals is needed to be switched on and off to control it, in order to simplify the driving method of array substrate, the present invention is real
It is identical as the open signal of gating transistor and cut-off signals to apply the open signal of preferred gating transistor and cut-off signals in example.
In addition, the display device includes the above display module the embodiment of the invention also provides a kind of display device.Specifically
Ground, the display device can be liquid crystal display panel, Electronic Paper, organic light emitting display panel, mobile phone, tablet computer, television set, display
Any products or components having a display function such as device, laptop, Digital Frame, navigator.
Embodiment two
Embodiment two provides a kind of voltage regulator circuit for power supply unit, gives voltage signal bring shadow to eliminate temperature change
It rings, to further influence the unlatching of gating transistor.Illustratively, it is V that two voltage regulator circuit of the present embodiment, which provides voltage,REF。
Referring to Figures 5 and 6, the voltage regulator circuit of the present embodiment 2 includes: bipolar junction transistor Q1, Q2, Q3；PMOS transistor
M30,M31,M32,M33；NMOS transistor M40, M41；Resistance R1, R2, R3, R4, R41；Operational amplifier A1, buffer B1,
B2；Capacitor Cc.
Fig. 5 is that the invention shows mould group power supply unit voltage regulator circuit figures.Wherein, PMOS transistor M30, M31, M32, M33
Source electrode connect supply voltage VDD, PMOS transistor M30 grid connection PMOS transistor M31, M32, M33 grid, crystal
The emitter of the drain electrode connection transistor Q1 of pipe M30 and one end of resistance R1, the one of the other end connection resistance R2 of resistance R1
The input terminal of end and buffer B1, the base stage of output end connection transistor Q1, Q2 of buffer B1, the other end of resistance R2 with
And the grounded collector of transistor Q1；
The emitter of the drain electrode connection transistor Q2 of PMOS transistor M31 and the inverting input terminal of operational amplifier A1,
The grounded collector of transistor Q2；The grid of the output end connection transistor M31 of operational amplifier A1, operational amplifier A1 is just
The grid of phase input terminal connection NMOS transistor M41；
The grid of the drain electrode connection transistor M32 of NMOS transistor M40, the grid connection resistance R41's of transistor M40 is another
The drain electrode of one end and transistor M41, the source electrode ground connection of transistor M40；The transmitting of the drain electrode connection transistor Q3 of transistor M32
Pole, the output end of the base stage connection buffer B2 of transistor Q3, the grounded collector of transistor Q3；One end of resistance R41 connects
Supply voltage VDD, the other end connect the drain electrode of transistor M41, the source electrode ground connection of transistor M41；
One end of capacitor Cc connects supply voltage VDD, and the other end connects the grid of transistor M33, the source electrode of transistor M33
Connect supply voltage VDD, one end of drain electrode connection resistance R3, and the output end as voltage regulator circuit；The other end of resistance R3 connects
Connect the input terminal of buffer B2 and one end of resistance R4, the other end ground connection of resistance R4.
Fig. 6 is that the invention shows mould group power supply unit voltage regulator circuit buffer circuits figures.As shown in fig. 6, buffer B1, B2
For low output impedance unity gain buffer, buffer circuits include PMOS transistor M1, M2, M5, M7；NMOS transistor M3,
M4,M6,M8,Ms1；Resistance R8, capacitor Cc1；
Wherein one end of the source electrode of transistor M5, M7 and resistance R8 connect supply voltage VDD, and the grid of transistor M5 connects
The grid of transistor M7, the source electrode of drain electrode connection transistor M1, M2 of transistor M5 are connect, the grid of transistor M1 connects transistor
The grid of Ms1 and the other end of resistance R8, and the output end as buffer；The drain electrode connection transistor M3's of transistor M1
Drain electrode and grid, the grid of the grid connection transistor M4 of transistor M3, the source electrode ground connection of transistor M3, M4；
Transistor M2 grid connects the source electrode of transistor Ms1, and the input terminal as buffer, and the drain electrode of transistor M2 connects
Connect the drain electrode of transistor M4 and the grid of transistor M6, M8；
The grid of transistor M7 connects its drain electrode, the drain electrode of the drain electrode connection transistor Ms1 of transistor M7 and transistor
The drain electrode of M6, one end of the grid connection capacitor Cc1 of transistor M6, the other end of capacitor Cc1 and the source electrode of transistor M6 connect
Ground；The source electrode of transistor M8 is grounded, the other end of drain electrode connection resistance R8 and the grid of transistor Ms1.
Wherein, the breadth length ratio of transistor M31 is N times of transistor M30, M32 and M33, and N is the positive integer greater than 1；It is brilliant
The emitter area of body pipe Q3 is n times of the emitter area of transistor Q2, and n is the positive integer greater than 1, to make transistor Q3
It is different with the Collector Current Density of Q2；When circuit works normally, the voltage at the both ends resistance R1 is exactly bipolar junction transistor Q1
Emitter base voltage VEB1If the ratio of resistance R1 and R2 are m, the voltage at the both ends R2 is equal to VEB1/ m, therefore
And the voltage of the reverse side input terminal of operational amplifier A1 are as follows:
VIN=VEB1/m+VEB2
If operational amplifier is ideal operational amplificr, two input terminal voltage VINWith VIPIt is equal, therefore, electricity
Hinder the voltage at the both ends R4 are as follows:
VR4=VIP-VEB3=VEB1/m+VEB2-VEB3,
Since the Collector Current Density of transistor Q2 and Q3 is different, VEB2-VEB3=Δ VEBIt is a PTAT voltage,
The appropriate value for choosing m, so that it may obtain a temperature independent burning voltage VR4, at this time:
VREF=VR4(1+R3/R4)；
Therefore, the value for suitably choosing resistance R1, R2, R3, R4, can obtain a temperature independent burning voltage VREF。
Through the above description of the embodiments, invention is mainly reflected in three parts to the contribution of the prior art: first is that
The invention shows mould groups by detection unit being arranged in second grid circuit 140 to detect the choosing close to second grid circuit side
Whether logical transistor is normally-open；Second is that the invention shows the driving methods of mould group；Third is that the present invention passes through in power supply unit
Voltage regulator circuit is set, so that output voltage is not influenced by variation of ambient temperature.Those skilled in the art can be clearly
Recognize, the present invention can add the mode of required common hardware to realize by software.
Although the present invention can be real it should be understood by those skilled in the art that the present invention is disclosed as above with preferred embodiment
Other particular forms are applied into, without departing from its spirit or inner characteristic.Above-described embodiment all will be understood as one that only in all respects
Be merely exemplary with it is unrestricted.Therefore, protection scope of the present invention by appended claims rather than front
Specification limits.Change in the meaning and scope of fallen with claims equivalent will all be included in claims
Within the scope of.
Claims (7)
1. a kind of display module comprising control printed circuit board, data drive circuit, first grid driving circuit, Yi Ji
Two gate driving circuits, it is characterised in that:
It is provided with detection unit in the second grid driving circuit, for detecting the choosing close to second grid driving circuit side
Whether logical transistor is normally-open, and sequence controller, the first level converter and are equipped on the control printed circuit board
Two level converters and power supply unit, the first grid driving circuit and second grid driving circuit pass through data-driven
Circuit is connected to sequence controller and power supply unit, or is directly connected to sequence controller by flexible printed circuit board
And the pulse of generation is supplied to the by data drive circuit by power supply unit, the first level converter and second electrical level converter
One gate driving circuit and second grid driving circuit, first grid driving circuit export first grid pulse CKV1, second gate
Pole driving circuit exports second grid pulse CKV2, and first grid pulse CKV1 has the open signal that gating transistor is connected
V1 and cut-off signals V0, second grid pulse CKV2 have the open signal V2 and cut-off signals V0 that gating transistor is connected,
Wherein, V2 is greater than or equal to V1, and in the first gating period t1 of gating period T, letter is opened in the output of first grid driving circuit
Number V1 is to grid line part；The gating that the detection unit of second grid driving circuit is detected close to second grid driving circuit side is brilliant
Whether body pipe is normally-open；If normally-open, in the second gating period t2 of gating period T, first grid driving electricity
Road is continued offer open signal V1 and is driven, otherwise, in the second gating period t2 of gating period T, first grid driving
Circuit stops providing open signal, while second grid driving circuit provides open signal V2 and driven.
2. display module as described in claim 1, wherein the first gating period t1 and the second gating period t2 are equal, or
Second gating period t2 is bigger than the first gating period t1.
3. display module as claimed in claim 2, wherein voltage regulator circuit is arranged in the power supply unit, comprising: ambipolar crystalline substance
Body pipe Q1, Q2, Q3；PMOS transistor M30, M31, M32, M33；NMOS transistor M40, M41；Resistance R1, R2, R3, R4, R41；
Operational amplifier A1, buffer B1, B2；Capacitor Cc；
Wherein, the source electrode of PMOS transistor M30, M31, M32, M33 connects supply voltage VDD, and the grid of PMOS transistor M30 connects
Connect the grid of PMOS transistor M31, M32, M33, the emitter of the drain electrode connection transistor Q1 of transistor M30 and resistance R1's
One end, one end of the other end connection resistance R2 of resistance R1 and the input terminal of buffer B1, the output end connection of buffer B1
The base stage of transistor Q1, Q2, the other end of resistance R2 and the grounded collector of transistor Q1；
The emitter of the drain electrode connection transistor Q2 of PMOS transistor M31 and the inverting input terminal of operational amplifier A1, crystal
The grounded collector of pipe Q2；The grid of the output end connection transistor M31 of operational amplifier A1, the positive of operational amplifier A1 are defeated
Enter the grid of end connection NMOS transistor M41；
The grid of the drain electrode connection transistor M32 of NMOS transistor M40, the other end of the grid connection resistance R41 of transistor M40
And the drain electrode of transistor M41, the source electrode ground connection of transistor M40；The emitter of the drain electrode connection transistor Q3 of transistor M32,
The output end of the base stage connection buffer B2 of transistor Q3, the grounded collector of transistor Q3；One end of resistance R41 connects power supply
Voltage VDD, the other end connect the drain electrode of transistor M41, the source electrode ground connection of transistor M41；
One end of capacitor Cc connects supply voltage VDD, and the other end connects the grid of transistor M33, the source electrode connection of transistor M33
Supply voltage VDD, one end of drain electrode connection resistance R3, and the output end as voltage regulator circuit；The other end connection of resistance R3 is slow
Rush the input terminal of device B2 and one end of resistance R4, the other end ground connection of resistance R4.
4. display module according to claim 3, which is characterized in that buffer B1, B2 are low output impedance unit gain
Buffer, buffer circuits include PMOS transistor M1, M2, M5, M7；NMOS transistor M3, M4, M6, M8, Ms1；Resistance R8,
Capacitor Cc1；
Wherein one end of the source electrode of transistor M5, M7 and resistance R8 connect supply voltage VDD, and the grid of transistor M5 connects brilliant
The grid of body pipe M7, the source electrode of drain electrode connection transistor M1, M2 of transistor M5, the grid of transistor M1 connect transistor Ms1
Grid and resistance R8 the other end, and the output end as buffer；The leakage of the drain electrode connection transistor M3 of transistor M1
Pole and grid, the grid of the grid connection transistor M4 of transistor M3, the source electrode ground connection of transistor M3, M4；
Transistor M2 grid connects the source electrode of transistor Ms1, and the input terminal as buffer, and the drain electrode of transistor M2 connects brilliant
The drain electrode of body pipe M4 and the grid of transistor M6, M8；
The grid of transistor M7 connects its drain electrode, the drain electrode of the drain electrode connection transistor Ms1 of transistor M7 and transistor M6's
Drain electrode, one end of the grid connection capacitor Cc1 of transistor M6, the other end of capacitor Cc1 and the source electrode ground connection of transistor M6；It is brilliant
The source electrode of body pipe M8 is grounded, the other end of drain electrode connection resistance R8 and the grid of transistor Ms1.
5. a kind of driving method of display module, the display module includes control printed circuit board, data drive circuit, first
Gate driving circuit and second grid driving circuit, it is characterised in that: be provided with detection in the second grid driving circuit
Unit, whether there is or not normally-open, first grid drives for the gating transistor for detecting close second grid drive circuit module side
Dynamic circuit output first grid pulse CKV1, second grid driving circuit export second grid pulse CKV2, first grid pulse
There is CKV1 the open signal V1 and cut-off signals V0 that gating transistor is connected, second grid pulse CKV2, which to have, keeps gating brilliant
The open signal V2 and cut-off signals V0 of body pipe conducting, the described method comprises the following steps:
S101: in the first gating period t1 of gating period T, first grid driving circuit exports first grid pulse CKV1's
Open signal V1 is to grid line part；
S102: the gating transistor that the detection unit of second grid driving circuit is detected close to second grid driving circuit side is
It is no normally-open；If normally-open, S103 is turned to, otherwise, turns to S104；
S103: in the second gating period t2 of gating period T, first grid driving circuit continues to provide open signal V1 progress
Driving；
S104: in the second gating period t2 of gating period T, first grid driving circuit stops providing open signal, simultaneously
Second grid driving circuit provides open signal V2 and is driven, with normally-open gating transistor.
6. driving method as claimed in claim 5, wherein V2 is greater than or equal to V1.
7. such as driving method described in claim 5 or 6, wherein the first gating period t1 and the second gating period t2 are equal, or
Person the second gating period t2 is bigger than the first gating period t1.
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| CN111128084A (en) * | 2018-10-31 | 2020-05-08 | 惠科股份有限公司 | Driving circuit and driving method of display panel and display device |
| CN109710022A (en) * | 2019-01-07 | 2019-05-03 | 上海奥令科电子科技有限公司 | A kind of voltage regulator circuit |
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| CN1333529A (en) * | 2000-07-07 | 2002-01-30 | 索尼公司 | Indicator and driving method thereof |
| CN101226713A (en) * | 2007-01-19 | 2008-07-23 | 三星电子株式会社 | Display apparatus and method of driving the same |
| CN102402933A (en) * | 2010-09-09 | 2012-04-04 | 株式会社半导体能源研究所 | Semiconductor device |
| CN104575361A (en) * | 2015-02-06 | 2015-04-29 | 京东方科技集团股份有限公司 | Compensating circuit and working method thereof as well as display substrate and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5153011B2 (en) * | 2010-07-30 | 2013-02-27 | 株式会社ジャパンディスプレイセントラル | Liquid crystal display |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1333529A (en) * | 2000-07-07 | 2002-01-30 | 索尼公司 | Indicator and driving method thereof |
| CN101226713A (en) * | 2007-01-19 | 2008-07-23 | 三星电子株式会社 | Display apparatus and method of driving the same |
| CN102402933A (en) * | 2010-09-09 | 2012-04-04 | 株式会社半导体能源研究所 | Semiconductor device |
| CN104575361A (en) * | 2015-02-06 | 2015-04-29 | 京东方科技集团股份有限公司 | Compensating circuit and working method thereof as well as display substrate and display device |
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