CN106646204A - FPGA storage resource testing system, method and device - Google Patents
FPGA storage resource testing system, method and device Download PDFInfo
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- CN106646204A CN106646204A CN201611207482.3A CN201611207482A CN106646204A CN 106646204 A CN106646204 A CN 106646204A CN 201611207482 A CN201611207482 A CN 201611207482A CN 106646204 A CN106646204 A CN 106646204A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318516—Test of programmable logic devices [PLDs]
- G01R31/318519—Test of field programmable gate arrays [FPGA]
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Abstract
The invention relates to an FPGA storage resource testing system, method and device. The system comprises a clock management module, a data excitation module, a clock domain crossing data transmission module, a data comparison module, and a result display module. The clock management module is used for providing a first clock signal for the data excitation module and the result display module, and providing a second clock signal for the data comparison module and a to-be-stored resource in the FPGA chip. The time frequency of the second clock signal is higher than the clock frequency of the first clock signal. The clock domain crossing data transmission module is used for achieving the data transmission of the time domain of the first clock signal and the time domain of the second clock signal. The system can improve the test time sequence convergence characteristics.
Description
Technical field
The present invention relates to programmable logic array (FPGA) technical field, more particularly to a kind of FPGA storage resources test
System, method and device.
Background technology
FPGA due to it there is the characteristics such as programmable, flexibility and high-throughput to be widely used in digital signal acquiring, pressure
The fields such as contracting, transmission and process.In order to verify whether FPGA reaches expected technical indicator, need to survey FPGA device
Examination.According to test purpose difference can be divided into target test and altitude touch test, target test be in order to verify FPGA device with
The accordance of technical indicator, and test of touch is then its reflection in order to verify that FPGA device surpasss the expectation the surplus of technical indicator
The actual performance of FPGA device.
When conventional method is tested the piece memory storage resource of FPGA device, it is related to input stimulus module, module to be measured
And output comparison module, in the test of high speed FPGA device, in order to ensure that test system sequential can normally restrain, each mould
Signal interaction between block is particularly important.But for high speed FPGA device, when FPGA piece memory storage resources to be measured
During speed more and more higher, the lifting of test speed of other resource constraints in addition to storage resource module to be measured, therefore exist
Timing closure is relatively difficult to ensure that, limit velocity tests unapproachable problem, it is difficult to ensure test quality.
The content of the invention
Based on this, FPGA storage resource test systems, method and device are embodiments provided, test can be lifted
Timing closure characteristic.
One aspect of the present invention provides a kind of FPGA storage resources test system, including：
Clock management module, data stimuli module, clock-domain crossing data transport module, data comparison module and result show
Show module；
The Clock management module is used to provide the first clock signal to the data stimuli module and result display module,
And provide second clock signal to the storage resource to be measured in the data comparison module and FPGA pieces；The second clock letter
Number clock frequency higher than first clock signal clock frequency；
The data stimuli module is used to produce random data, and the random data is cached into the cross clock domain number
According to transport module；
The storage resource to be measured reads the random data from the clock-domain crossing data transport module, and according to reading
To random data carry out write operation；
The data comparison module is used to read the random data from the clock-domain crossing data transport module, and reads
The data for writing the storage resource to be measured are taken, data is write what is read and is compared with the random data for reading, according to
Comparative result judges whether readwrite tests of the storage resource to be measured under second clock signal be qualified；
The result display module is used to show the readwrite tests result of the storage resource to be measured.
Another aspect of the present invention provides a kind of FPGA storage resources method of testing, including：
The first clock signal is provided to default data stimuli module, while providing to the storage resource to be measured in FPGA pieces
Second clock signal；Clock frequency of the clock frequency of the second clock signal higher than first clock signal；
The random data that the data stimuli module is produced under the first clock signal is read under second clock signal, and
Read the storage resource to be measured and row write is entered according to the random data of data stimuli module generation under second clock signal
What is operated writes data；
Write what is read data and be compared with the random data for reading, described to be measured deposit is judged according to comparative result
Whether readwrite tests of the storage resource under second clock signal be qualified.
Another aspect of the invention provides a kind of FPGA storage resources test device, including：
Clock control cell, for providing the first clock signal to default data stimuli module, while into FPGA pieces
Storage resource to be measured provide second clock signal；The clock frequency of the second clock signal is higher than first clock signal
Clock frequency；
Data capture unit, for the data stimuli module being read under second clock signal under the first clock signal
The random data of generation, and the storage resource to be measured is read under second clock signal according to data stimuli module generation
Random data carry out write operation write data；
Judging unit, for writing what is read data and being compared with the random data for reading, according to comparative result
Judge whether readwrite tests of the storage resource to be measured under second clock signal be qualified.
Based on FPGA storage resource test systems, method and device that above-described embodiment is provided, to the data stimuli mould
Block and result display module provide the first clock signal, and provide to the storage to be measured in the data comparison module and FPGA pieces
Source provides second clock signal；Clock frequency of the clock frequency of the second clock signal higher than first clock signal；
It is used to realize the clock zone of the first clock signal and the clock of second clock signal by the clock-domain crossing data transport module
The data transfer in domain.The speed on storage resource module to be measured thus, it is possible to reduce other resources affects, and lifts test sequence
Convergence property.
Description of the drawings
Fig. 1 is the schematic diagram of the FPGA storage resource test systems of an embodiment；
Fig. 2 is the schematic diagram of the FPGA storage resource test systems of another embodiment；
Fig. 3 is the schematic diagram of the FPGA storage resource test systems of another embodiment；
Fig. 4 is the indicative flowchart of the FPGA storage resource method of testings of an embodiment；
Fig. 5 is the schematic diagram of the FPGA storage resource test devices of an embodiment.
Specific embodiment
In order that the objects, technical solutions and advantages of the present invention become more apparent, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that specific embodiment described herein is only to explain the present invention, and
It is not used in the restriction present invention.
Fig. 1 is the schematic diagram of the FPGA storage resource test systems of an embodiment；As shown in figure 1, the present embodiment
In FPGA storage resource test systems include：Clock management module, data stimuli module, clock-domain crossing data transport module,
Data comparison module and result display module.Wherein each module and it is described as follows based on the test philosophy of the system.
Wherein, the Clock management module is used to provide the first clock to the data stimuli module and result display module
Signal CLK1, and provide second clock signal CLK2 to the storage resource to be measured in the data comparison module and FPGA pieces；
Clock frequency of the clock frequency of the second clock signal CLK2 higher than first clock signal clk 1.In practical application
In, CLK1 can be realized with outside input clock signal same frequency, CLK2 using frequency doubling technology.It is used for driving by low frequency clock domain
Dynamic data stimuli module and result display module, are used for driving storage resource to be measured and data to compare mould by high frequency clock domain
Block, its objective is to ensure that data stimuli module possesses preferable timing closure characteristic with relatively low clock frequency.
It is based on the test philosophy of said system：The data stimuli module is used to produce random data, and by it is described with
Machine data buffer storage is to the clock-domain crossing data transport module.The storage resource to be measured transmits mould from the clock-domain crossing data
Block reads the random data, and carries out write operation according to the random data for reading；The data comparison module is used for from institute
State clock-domain crossing data transport module and read the random data, and read the data for writing the storage resource to be measured, will
What is read writes data and is compared with the random data for reading, and judges the storage resource to be measured according to comparative result
Whether the readwrite tests under two clock signals is qualified, and readwrite tests result is exported to result display module；The result shows
Module is used to show the readwrite tests result of the storage resource to be measured.
Wherein, the clock-domain crossing data transport module is used to realize that the clock zone of the first clock signal is believed with second clock
Number clock zone data transfer；In a preferred embodiment, the clock-domain crossing data transport module adopts dual port RAM
(Random Access Memory) or FIFO (First-Input-First-Output) memory are realized.In actual test
In, can be with the piece memory storage resource as storage resource to be measured using FPGA device.
In a preferred embodiment, in the data comparison module, by read to write data random with what is read
Data are compared, and judge whether readwrite tests of the storage resource to be measured under second clock signal closes according to comparative result
The embodiment of lattice can be：If the data that this is read from the storage resource to be measured are with this from the clock-domain crossing data
The random data that transport module reads is consistent, then this readwrite tests for being judged as the storage resource to be measured passes through, otherwise,
This readwrite tests for being judged as the storage resource to be measured does not pass through.
In a preferred embodiment, RAM, FIFO storage is configurable to during storage resource to be measured is in the FPGA device piece
Device, shift register etc..
In a preferred embodiment, with reference to shown in Fig. 2, the FPGA storage resources test system includes at least two groups data
Excitation module, clock-domain crossing data transport module and data comparison module.At least two groups data stimuli modules, the cross clock domains
Data transmission module and data comparison module export readwrite tests result to the result display module.Also, it is described at least
Two groups of data stimuli modules, clock-domain crossing data transport module and data comparison modules, respectively storage to be measured with least two is provided
Source corresponds.From there through the test realized to extensive storage resource to be measured, testing efficiency is high.
Based on the FPGA storage resource test systems that above-described embodiment is provided, Clock management module is used to swash to the data
Encourage module and result display module and the first clock signal is provided, and deposit to be measured in the data comparison module and FPGA pieces
Storage resource provides second clock signal；Clock frequency of the clock frequency of the second clock signal higher than first clock signal
Rate；The clock-domain crossing data transport module is used to realize the clock zone of the first clock signal and the clock zone of second clock signal
Data transfer.The speed on storage resource module to be measured thus, it is possible to reduce other logical resources affects, when lifting test
Sequence convergence property；And the test of Mass storage resource is can adapt to, test coverage is good, simple to operate, implementation cost is low.
With reference to Fig. 2, the FPGA storage resources test system and its test philosophy of the embodiment of the present invention are done further
Explanation.
As shown in Fig. 2 the FPGA storage resources test system includes that n group data stimuli modules, clock-domain crossing data are passed
Defeated module and data comparison module, are respectively used to test storage resource to be measured 1～storage resource n to be measured.N group data stimuli moulds
Block, clock-domain crossing data transport module and data comparison module provide clock signal by same Clock management module.Specifically
, the test philosophy of the system is as follows：
1. Clock management module (identifies) in Fig. 2：The effect of Clock management module is by being input into an outside source
To export the clock signal of two cross clock domains, low frequency clock domain is used for driving excitation and display module, high frequency clock domain to be used for
Drive storage resource to be measured and data comparison module.In actual applications, CLK1 can with outside input clock signal same frequency,
CLK2 is realized using frequency doubling technology.
2. clock-domain crossing data transport module (identifies) in Fig. 2：The module can be using dual port RAM or FIFO memory reality
It is existing, it is therefore an objective to realize the data transfer of different clock-domains.In actual test, it can be adopted as storage resource to be measured
The piece memory storage resource of FPGA device.
3. low frequency clock domain (identifies) in Fig. 2：CLK1 is low frequency clock domain, its objective is to be protected with relatively low clock frequency
Card data stimuli module possesses preferable timing closure characteristic.
4. high frequency clock domain (identifies) in Fig. 2：CLK2 is high frequency clock domain, in order to realize to FPGA device high-speed chip internal memory
The velocity test of storage resource, needs to carry out reading and writing data test to the piece memory storage resource of FPGA device using high frequency clock domain.
Storage resource flattening to be measured divides (identifying 5. in Fig. 2)：FPGA device piece memory storage resource be divided into n compared with
Little storage resource is tested respectively, and by this kind of mode the address size of storage resource can be reduced, and is conducive to test system
System is converged in a higher operating frequency, it is to avoid other logical resources in addition to storage resource to be measured are on test speed
Restriction.It is by the way that the velocity test to FPGA device inside Mass storage resource can be realized using the division methods and full
Sufficient test system timing closure is required.
Random data excitation module (identifying 6. in Fig. 2)：The module is produced for the random of storage resource readwrite tests to be measured
Data.
Storage resource module (identifying 7. in Fig. 2) to be measured：Storage resource to be measured in the FPGA device piece in be configurable to
RAM, FIFO, shift register etc..
8. data comparison module (identifies) in Fig. 2：The module writes data and expection what is read from storage resource to be measured
Data (i.e. data stimuli module produce random number) be compared, the read-write of storage resource to be measured is judged according to comparative result
Whether operation is correct, and in order to ensure the handling capacity of data and the real-time of process, it is operated in high frequency clock domain.
9. result display module (identifies) in Fig. 2：The module processes the result that different pieces of information comparison module is exported,
And shown by certain mode, to observe result.
In another preferred embodiment, with reference to shown in Fig. 3, different from the FPGA storage resource test systems of Fig. 2, can arrange
Two Clock management modules, are tested with the altitude touch for being more suitable for FPGA device piece memory storage resource speed.Wherein, the first clock pipe
Reason submodule is used to provide the first clock signal to the data stimuli module and result display module；Second clock manages submodule
Block is used to provide the second clock signal to the storage resource to be measured in the data comparison module and FPGA pieces.Lead in Fig. 3
Cross two Clock management modules to drive different clock zones, wherein CLK2 clock zones to be continuously increased outside input clock letter
Number frequency, to realize that the altitude touch to storage resource speed to be measured is tested.
The above embodiment of the present invention proposes the FPGA device piece memory storage resource speed testing system of cross clock domain, for
The time sequence allowance of FPGA device storage resource test system is lifted, flattening Test Strategy is devised, excited modes are reduced as far as possible
The restriction of block, control module and display module to test system speed.And by being designed using cross clock domain, can be test
The data stimuli module of system, result display module are separated with storage resource module to be measured, make the data stimuli mould of periphery
Block and result display module are operated in relatively low clock frequency, it is to avoid peripheral test control signal, pumping signal and display letter
Impact number to high speed storage resource velocity test to be measured, lifts time sequence allowance；And, by can using flattening Test Strategy
To lift test system time sequence allowance, to realize on the premise of test system timing requirements are met to high speed large-scale F PGA
The storage resource of device carries out the test of Full coverage.Additionally, the FPGA storage resource test systems of the above embodiment of the present invention
And method, the item test up to standard of the speed to FPGA device piece memory storage resource and speed altitude touch item test can be covered.
Based on the thought of the FPGA storage resource test systems in above-described embodiment, present invention also offers a kind of FPGA is deposited
The embodiment of storage resource testing method.As shown in figure 4, the FPGA storage resources method of testing of the present embodiment includes step：
S11, provides the first clock signal, while to the storage resource to be measured in FPGA pieces to default data stimuli module
Second clock signal is provided；Clock frequency of the clock frequency of the second clock signal higher than first clock signal；
S12, reads the random number that the data stimuli module is produced under the first clock signal under second clock signal
According to, and read the storage resource to be measured under second clock signal according to the data stimuli module produce random data enter
What row write was operated writes data；
S13, writes what is read data and is compared with the random data for reading, treats according to comparative result judges
Whether qualified survey readwrite tests of the storage resource under second clock signal.
In a preferred embodiment, also include in step S11：There is provided the first clock to default result display module simultaneously
Signal；It is corresponding, step is also included after step s 13：Readwrite tests result is sent to the result display module, is passed through
The result display module shows under the first clock signal to readwrite tests result.
By the FPGA storage resource method of testings of above-described embodiment, by different clock signals by data stimuli module
Separate with storage resource module to be measured, the data stimuli module for making periphery is operated in relatively low clock frequency, it is to avoid outward
Enclose test control signal, pumping signal and show impact of the signal to high speed storage resource velocity test to be measured, sequential can be lifted
Surplus.
It should be noted that for aforesaid each method embodiment, for easy description, it is all expressed as a series of
Combination of actions, but those skilled in the art should know, and the present invention is not limited by described sequence of movement, because according to
According to the present invention, some steps can adopt other orders or while carry out.Additionally, also any group can be carried out to above-described embodiment
Close, obtain other embodiments.
Based on above-described embodiment in FPGA storage resource method of testing identical thoughts, the present invention also provide FPGA deposit
Storage resource testing device, the device can be used to perform above-mentioned FPGA storage resources method of testing.For convenience of description, FPGA storages
In the structural representation of resource testing device embodiment, the part related to the embodiment of the present invention, this area skill are illustrate only
Art personnel are appreciated that the restriction of schematic structure not structure twin installation, can include than illustrating more or less of part, or
Person combines some parts, or different part arrangements.
Fig. 5 is the schematic diagram of the FPGA storage resource test devices of one embodiment of the invention；As shown in figure 5, this
The FPGA storage resource test devices of embodiment include：Clock management module and clock-domain crossing data transport module, also including point
The data stimuli module that is not connected with the Clock management module, clock control cell 510, data capture unit 520 and sentence
Disconnected unit 530.Each module declaration is as follows：
Above-mentioned clock control cell 510, for providing the first clock signal to default data stimuli module, while to
Storage resource to be measured in FPGA pieces provides second clock signal；The clock frequency of the second clock signal is higher than described first
The clock frequency of clock signal；
Above-mentioned data capture unit 520, for the data stimuli module being read under second clock signal at first
The random data produced under clock signal, and the storage resource to be measured is read under second clock signal according to the data stimuli
What the random data that module is produced carried out write operation writes data；
Above-mentioned judging unit 530, for writing what is read data and being compared with the random data for reading, according to than
Relatively result judges whether readwrite tests of the storage resource to be measured under second clock signal be qualified.
It should be noted that in the embodiment of the FPGA storage resource test devices of above-mentioned example, between each module
The contents such as information exchange, implementation procedure, due to being based on same design with preceding method embodiment of the present invention, the technology effect that it brings
Fruit is identical with preceding method embodiment of the present invention, and particular content can be found in the narration in the inventive method embodiment, herein no longer
Repeat.
Additionally, in the embodiment of the FPGA storage resource test devices of above-mentioned example, the logical partitioning of each functional module
It is merely illustrative of, can as needed in practical application, such as the realization of configuration requirement or software for corresponding hardware
Convenient consideration, above-mentioned functions distribution completed by different functional modules, will the FPGA storage resources test device
Internal structure is divided into different functional modules, to complete all or part of function described above.Wherein each function mould was both
Can be realized in the form of hardware, it would however also be possible to employ the form of software function module is realized.
It will appreciated by the skilled person that realizing all or part of flow process in above-described embodiment method, being can
Completed with instructing the hardware of correlation by computer program, described program can be stored in embodied on computer readable storage and be situated between
In matter, as independent production marketing or use.Described program upon execution, can perform as above-mentioned each method embodiment it is complete
Portion or part steps.Wherein, described storage medium can be magnetic disc, CD, read-only memory (Read-Only
Memory, ROM) or random access memory (Random Access Memory, RAM) etc..
In the above-described embodiments, the description to each embodiment all emphasizes particularly on different fields, without the portion described in detail in certain embodiment
Point, may refer to the associated description of other embodiments.
Embodiment described above only expresses the several embodiments of the present invention, it is impossible to be interpreted as to the scope of the claims of the present invention
Restriction.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise,
Some deformations and improvement can also be made, these belong to protection scope of the present invention.Therefore, the protection domain of patent of the present invention
Should be defined by claims.
Claims (10)
1. a kind of FPGA storage resources test system, it is characterised in that include：Clock management module, data stimuli module, across when
Clock numeric field data transport module, data comparison module and result display module；
The Clock management module is used to provide the first clock signal to the data stimuli module and result display module, and
Second clock signal is provided to the storage resource to be measured in the data comparison module and FPGA pieces；The second clock signal
Clock frequency of the clock frequency higher than first clock signal；
The data stimuli module is used to produce random data, and the random data is cached into the clock-domain crossing data biography
Defeated module；
The storage resource to be measured reads the random data from the clock-domain crossing data transport module, and according to reading
Data carry out write operation；
The data comparison module is used to read the random data from the clock-domain crossing data transport module, and reading is write
Enter the data of the storage resource to be measured, write what is read data and be compared with the random data for reading, according to comparing
As a result judge whether readwrite tests of the storage resource to be measured under second clock signal be qualified；
The result display module is used for the readwrite tests result to the storage resource to be measured under second clock signal to be carried out
Show.
2. FPGA storage resources test system according to claim 1, it is characterised in that the clock-domain crossing data transmission
Module is realized using dual port RAM or FIFO memory.
3. FPGA storage resources test system according to claim 1, it is characterised in that the Clock management module is concrete
For：An external input signal is received, the first clock signal with the external signal same frequency is produced, and by frequency multiplication skill
Art produces corresponding second clock signal.
4. FPGA storage resources test system according to claim 1, it is characterised in that including at least two groups data stimulis
Module, clock-domain crossing data transport module and data comparison module；
At least two groups data stimuli modules, clock-domain crossing data transport module and the data comparison modules export readwrite tests
As a result to the result display module；
At least two groups data stimuli modules, clock-domain crossing data transport module and the data comparison modules, respectively with least two
Individual storage resource to be measured is corresponded.
5. FPGA storage resources test system according to claim 1, it is characterised in that the number of the Clock management module
Measure as two；
One of Clock management module is used to provide the first clock signal to the data stimuli module and result display module；
Another Clock management module is used to provide described second to the storage resource to be measured in the data comparison module and FPGA pieces
Clock signal.
6. according to the arbitrary described FPGA storage resource test systems of claim 1 to 5, it is characterised in that the storage to be measured
Resource is RAM, FIFO memory or shift register.
7. according to the arbitrary described FPGA storage resource test systems of claim 1 to 5, it is characterised in that the data compare
Module specifically for：
If this reads with this from the data of writing that the storage resource to be measured reads from the clock-domain crossing data transport module
The random data got is consistent, then this readwrite tests for being judged as the storage resource to be measured passes through, and otherwise, is judged as described
This readwrite tests of storage resource to be measured does not pass through.
8. a kind of FPGA storage resources method of testing, it is characterised in that include：
The first clock signal is provided to default data stimuli module, while providing second to the storage resource to be measured in FPGA pieces
Clock signal；Clock frequency of the clock frequency of the second clock signal higher than first clock signal；
The random data that the data stimuli module is produced under the first clock signal is read under second clock signal, and is read
The random data that the storage resource to be measured is produced under second clock signal according to the data stimuli module carries out write operation
Write data；
Write what is read data and be compared with the random data for reading, the storage money to be measured is judged according to comparative result
Whether readwrite tests of the source under second clock signal be qualified.
9. FPGA storage resources method of testing according to claim 8, it is characterised in that to default data stimuli module
First clock signal is provided, at the same in FPGA pieces storage resource to be measured provide second clock signal the step of, also include：
There is provided the first clock signal to default result display module simultaneously；
It is described that the whether qualified step of readwrite tests of the storage resource to be measured under second clock signal is judged according to comparative result
After rapid, also include：
Readwrite tests result is sent to the result display module, by the result display module under the first clock signal
Readwrite tests result is shown.
10. a kind of FPGA storage resources test device, it is characterised in that include：
Clock control cell, for providing the first clock signal to default data stimuli module, while to treating in FPGA pieces
Survey storage resource and second clock signal is provided；The clock frequency of the second clock signal higher than first clock signal when
Clock frequency；
Data capture unit, produces for reading the data stimuli module under second clock signal under the first clock signal
Random data, and read the storage resource to be measured under second clock signal according to the data stimuli module produce with
What machine data carried out write operation writes data；
Judging unit, for writing what is read data and being compared with the random data for reading, judges according to comparative result
Whether readwrite tests of the storage resource to be measured under second clock signal be qualified.
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| CN109739706A (en) * | 2018-12-29 | 2019-05-10 | 西安智多晶微电子有限公司 | A kind of ram test method and test device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109739706A (en) * | 2018-12-29 | 2019-05-10 | 西安智多晶微电子有限公司 | A kind of ram test method and test device |
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| CN106646204B (en) | 2019-02-19 |
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