CN106605268A

CN106605268A - Magnetic field-assisted memory operation

Info

Publication number: CN106605268A
Application number: CN201580045595.5A
Authority: CN
Inventors: H.奈米; S-L.L.卢; S.托米施马
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2014-09-26
Filing date: 2015-08-26
Publication date: 2017-04-26
Anticipated expiration: 2035-08-26
Also published as: KR20170033383A; KR102240162B1; JP6330970B2; TW201626380A; WO2016048560A1; US9747967B2; US20180025764A1; EP3198603B1; EP3198603A1; CN106605268B; TWI592928B; EP3198603A4; JP2017535907A; US20160093355A1

Abstract

In one embodiment, a magnetoresistance random access memory (MRAM) such as a spin transfer torque (STT) random access memory (RAM), for example, has a subarray of bitcells and an electro-magnet positioned adjacent the subarray. A magnetic field is directed through a ferromagnetic device of bitcells of the first subarray to assist in the changing of states of bitcells of the subarray from a first state to a second state in which the ferromagnetic device of the bitcell is changed from one of parallel and anti-parallel polarization to the other of parallel and anti-parallel polarization. Accordingly, the content of the subarray may be readily preset or erased to one of the parallel or anti-parallel state with assistance from an electro-magnet. During a normal write operation, the bits to the other state are written. Other aspects are described herein.

Description

The storage operation of magnetic field auxiliary

Technical field

Certain embodiments of the present invention generally relate to nonvolatile memory.

Background technology

Spin transfer torque random access memory（STTRAM）It is magnetoresistive RAM（MRAM）Type, its It is non-volatile and is typically used in memory circuitry, such as cache, memorizer, secondary reservoir and other storages Device application.STTRAM memorizeies generally can be operated with the power level for reducing and may not compared with other type of memory It is too expensive.

The problem that STTRAM memorizeies are met with is that the write operation to STTRAM memorizeies may be relatively long, As compared to read operation, so as to negatively affect the performance of STTRAM memorizeies.Reduce for STTRAM memorizeies One scheme of write time has been the persistency for reducing memorizer, that is to say, that each bit location securely maintains it The length of the time of logic state.

Efficiency of other technologies for improvement STTRAM memorizeies.When one such technology for detection unit is switched simultaneously And terminate the write operation for the unit to reduce the excess current for flowing through ferromagnetic device.

Another type of nonvolatile memory is flash memory, and its bit cell includes NAND gate.Flash memory Generally there are two operator schemes, wherein wipe whole subarray erasing mode and wherein then can be as required The Setting pattern of position is set.

Description of the drawings

By way of example rather than by way of limiting embodiment of the disclosure is illustrated in each figure of accompanying drawing, its Middle identical reference number refers to similar element.

Figure 1A depicts the high level block diagram for illustrating the selected aspect according to the system of embodiment of the disclosure.

Figure 1B depicts the basic framework according to the STTRAM memorizeies of embodiment of the disclosure.

Fig. 1 C-1F depict the various polarization of the ferromagnetic layer of the bit location of the STTRAM memorizeies of Figure 1B.

Fig. 2A -2B depict typical one depositor of a transistor（1T1R）The schematic diagram of device, it illustrates bit line （BL）, wordline（WL）With source line（SL）.

Fig. 3 is to depict one depositor of a transistor for Fig. 2A -2B（1T1R）The reading of device and write electricity The chart of pressure.

Fig. 4 A are the sons of the bit location of the STTRAM memorizeies for passing through Figure 1B according to the guiding magnetic field of embodiment of the disclosure The ferromagnetic layer of array schematically shows.In the figure, arrow represents the polarization of " free layer " as explained below.

Fig. 4 B be according to the bit location of the STTRAM memorizeies for being arranged in Figure 1B of embodiment of the disclosure subarray it On schematically showing for the coil that guides magnetic field to pass through the subarray of bit location.

Fig. 5 A are the sons of the bit location of the STTRAM memorizeies for passing through Figure 1B according to the guiding magnetic field of embodiment of the disclosure The alternative embodiment of the ferromagnetic layer of array schematically shows.Similarly, in the figure, arrow represents as explained below The polarization of " free layer ".

Fig. 5 B are schematically showing for the section view of the subarray of the magnetic field of Fig. 5 A and free ferromagnetic.

Fig. 5 C be according to the bit location of the STTRAM memorizeies for being arranged in Figure 1B of embodiment of the disclosure subarray it On schematically show for the alternative embodiment of the coil that guides magnetic field to pass through the subarray of bit location.

Fig. 5 D are schematically showing for the alternative embodiment of the coil of Fig. 5 C.

Fig. 6 A are turned to writing data to prepare to the write of the data of the bit location of the STTRAM memorizeies of Figure 1B That what is changed schematically shows.

Fig. 6 B are the converted write numbers to prepare to the write of the data of the bit location of the STTRAM memorizeies of Figure 1B According to presentation schematically show.

Fig. 6 C are written to schematically showing for the converted write data of the bit location of the STTRAM memorizeies of Figure 1B.

Fig. 7 is depicted according to embodiment of the disclosure for write data to be written to the STTRAM memorizeies of Figure 1B One example of the operation of bit location.

Fig. 8 A and 8B depict the logic of the control circuit according to the STTRAM memorizeies of Figure 1B of embodiment of the disclosure To physical address map logic, it will be remapped to separately for the logical address of memory lines from a memory lines physical address One memory lines physical address.

Specific embodiment

In the description that follows, for identical component identical reference number has been provided, regardless of whether being shown Go out in various embodiments.In order to illustrate the disclosure in clear and succinct mode（One or more）Embodiment, accompanying drawing May be not necessarily to scale and some features may be illustrated with exemplary form to a certain degree.Retouch with regard to one embodiment The feature stated and/or illustrate can in an identical manner or in a similar manner in one or more of the other embodiment and/or Use with the combinations of features of other embodiments or the feature for being alternative in other embodiments.

According to the various embodiments of the disclosure, the mram memory of the magnetic field auxiliary of such as STT memorizeies etc is described. STT is wherein can to change MTJ using spin polarized current（MTJ）The effect of the magnetospheric orientation in device. In the MTJ based on STT, device resistance can be low or high, depending on the side of the magnetic polarization on the both sides of tunnel knot Relative angle difference between.

In one embodiment, the MTJ device of each bit location in the subarray that guiding magnetic field passes through bit location Ferromagnetic layer is promoting each MTJ from first state to the state change of the second state.In one embodiment, first state is There is antiparallel magnetic to be orientated and a low-resistance state is shown for the ferromagnetic layer of each of which MTJ.Conversely, the second state It is that the ferromagnetic layer of each of which MTJ has antiparallel（anti-parallel）Magnetic orientation and show high-resistance one Individual state.Recognize in order that the magnetic auxiliary provided by the magnetic field for being conducted through MTJ can promote from first（Parallel-oriented, Low resistance）State is to second（Antiparallel, high resistance）Change in the state of state.As explained in more detail below, institute Recognize in order that in certain embodiments, such magnetic auxiliary can reduce the write time of STT memorizeies.

For example, under the auxiliary of electromagnet, the content of subarray can by it is easily preset or be erased to it is parallel or One in antiparallel state.During normal write operation, position is written to into another state.

Understand, magnetic field ancillary technique as described herein can apply to the MRAM in addition to STT MRAM cells Equipment, such as giant magnetoresistance（GMR）MRAM, switching（toggle）MRAM and other MRAM cells.According to enforcement described herein Such memory component based on MRAM of example can be used in SAM Stand Alone Memory circuit or logic array, or can be with embedding Enter in microprocessor and/or digital signal processor（DSP）In.Although further, it is noted that herein in illustrated examples Referring especially to the system based on microprocessor come descriptive system and process, but will be appreciated that, in view of disclosure herein, Some aspect, framework and principles of the disclosure are equally applicable to other types of device memory and logical device.

Accompanying drawing is turned to, Figure 1A be a diagram that the senior frame of the selected aspect of the system realized in accordance with an embodiment of the present disclosure Figure.System 10 can represent any one in several electronics and/or computing device, and it can include memory devices.So Electronics and/or computing device can include computing device, such as large scale computer, server, personal computer, work station, phone Equipment, network appliance, virtual equipment, storage control, portable or mobile equipment（Such as kneetop computer, net book, flat Plate computer, personal digital assistant（PDA）, portable electronic device, portable game device, digital camera, mobile electricity Words, smart phone, characteristic phone etc.）Or component（Such as SOC(system on a chip), processor, bridger, Memory Controller, memorizer Deng）.In alternative embodiments, system 10 can include more elements, less element and/or different elements.And And, although system 10 can be depicted as including detached element, it will be appreciated that, such element is desirably integrated into one Platform（Such as SOC(system on a chip)（SoC））On.In illustrated examples, system 10 include microprocessor 20, Memory Controller 30, Memorizer 40 and peripheral assembly 50, it can be suitable including such as Video Controller, input equipment, outut device, bin, network Orchestration etc..Microprocessor 20 includes cache 25, and it can be the part of the memory hierarchy of store instruction and data, and System storage 40 can also be the part of memory hierarchy.Communication between microprocessor 20 and memorizer 40 can be by storing Device controller（Or chipset）30 promoting, the Memory Controller（Or chipset）30 can also promote and peripheral assembly 50 Communication.

The bin of peripheral assembly 50 can be such as non-volatile storage, such as solid-state drive, disc driver, CD drive, tape drive, flash memory etc.）.Bin can include that internal storage device or attached or network can The bin of access.Microprocessor 20 is configured to write data into 40 neutralizations from the reading data of memorizer 40.Storage Program in device is loaded in memorizer and is run by processor.Network controller or adapter make it possible to realize with it is all Such as the communication of the network of Ethernet, fiber channel arbitrated loop or the like.In addition, in certain embodiments, framework can include It is configured to reproduce the Video Controller of information in display monitor, wherein Video Controller can be embodied on video card Or be integrated on the integrated circuit package on being installed on motherboard or other substrates.Input equipment is used to provide user to processor Input, and keyboard, mouse, stylus, mike, touch-sensitive display panel, input pin, socket or as is generally known in the art can be included Any other activation or input mechanism.Outut device can be reproduced from processor or such as display monitor, printer, storage The information of other component transmission of storage, output pin, socket or the like.Network adapter can be embodied in network card（Such as Periphery component interconnection（PCI）Card, quick PCI or certain other I/O card）The upper or collection on motherboard or other substrates are installed on Into on circuit unit.

One or more in the component of equipment 10 can be omitted depending on application-specific.For example, network router can To lack such as Video Controller.

Any one or more in memory devices 25,40, and the miscellaneous equipment 10,30,50 can include according to According to the mram memory that the magnetic of this specification is aided in.Figure 1B is illustrated according to the STT memorizeies of one embodiment of this specification The example of the array 60 of the row and column of 66 bit location 64.STT memorizeies 66 can also include row decoder, timer device and I/O equipment（Or I/O outputs）.The position of the same memory word can in order to efficient I/O design and with it is separated from one another.Multiplexer （MUX）Can be used in READ（Read）Required circuit will be connected to during operation per string.Another MUX can be used for WRITE（Write）Write driver will be connected to during operation per string.Control circuit 68 performs the reading behaviour of bit cell 64 The write operation of work, write operation and magnetic field auxiliary, as explained below.Control circuit 68 is configured to use appropriate hard Part, software or firmware or its various combination are performing described operation.

Each bit location 64 of the array 60 of bit location 64 includes ferromagnetic device 70（Fig. 1 C）, such as Spin Valve, or magnetic Property tunnel knot（MTJ）Device.The ferromagnetic device 70 of each of bit location is included by 76 detached two, intermediate layer ferromagnetic material Layer 72,74a, the intermediate layer 76 is metal level in the case of Spin Valve or is thin electrolyte or exhausted in the case of MTJ Edge layer.In this example, ferromagnetic material layers 72 are electrically contacted layer 78 and contact and fix with the wherein leading direction of magnetization Fixed polarization.Thus, layer 72 is referred to as fixed layer.The leading direction of magnetization of fixed layer 72 has by the section view in Fig. 1 C In point to the direction of magnetization that left arrow 80 is represented from right.

Another ferromagnetic material layers 74a is electrically contacted layer 81 and contacts and be referred to as " free layer ", and it has wherein can select Change to selecting property the changeable polarization of the leading direction of magnetization of free layer.The leading direction of magnetization of free layer 74a is by equally existing Represent from the right arrow 82a for pointing to a left side in the section view of Fig. 1 C.

In the example of Fig. 1 C, free layer and fixed layer 74a, the leading direction of magnetization both 72 are depicted as being identical , that is to say, that in the same direction.If the leading direction of magnetization of two ferromagnetic layers 72,74a is identical, by two layers Polarization is referred to as " parallel ".In parallel polarization, bit location shows low resistance state, and it can be selected to represent that storage is in place One in logic one or logical zero in unit.If the leading direction of magnetization of two ferromagnetic layers is conversely, as by Fig. 1 D Arrow 80（Dextrad is left）And 82b（From left to right）Shown, then the polarization of two layers 72,74b is referred to as " antiparallel ".Anti- In parallel polarization, bit location shows high resistance state, its can be selected to represent the logic one that is stored in bit location or Another in logical zero.

Polarization and thus the logical bit value that is stored in the bit location 64 of STTRAM 66 can be by passing in particular directions Pass spin polarized current and particular state is configured to by the ferromagnetic device 70 of bit location 64.Spin polarized current is wherein electric Charge carrier（Such as electronics）Spin orientation mainly have a type（Spin up or spin downwards）Spin polarization electricity Stream.Therefore, control circuit 68（Figure 1B）It is configured to by transmitting spin polarized current in one direction by bit location 64 Ferromagnetic device 70 and logic one is stored in the bit location 64 of STTRAM 66.As a result, the ferromagnetic device of bit location 64 70 ferromagnetic layer has be parallel or antiparallel in the polarization of, depending on this, polarized state has been selected to represent Logic one.

Conversely, can pass through control circuit 68 transmits in the opposite direction ferromagnetic device of the spin polarized current by bit location Part 70 and logical zero is stored in the bit location 64 of STTRAM 66.As a result, the ferromagnetic device 70 of bit location 64 is ferromagnetic Layer have be parallel or antiparallel in another polarization, depending on this, polarization have been selected to represent logical zero.

Fig. 1 E and 1F depict the alternative embodiment of ferromagnetic device.Here, each position of the array 60 of bit location 64 Unit 64 includes ferromagnetic device 170（Fig. 1 E）, such as Spin Valve or MTJ（MTJ）Device.Each ferrum of bit location Magnetic device 170 includes that the intermediate layer 176 is in Spin Valve by 176 detached two, intermediate layer ferromagnetic material layers 172,174a In the case of be metal level and be thin electrolyte or insulating barrier in the case of MTJ.In this example, ferromagnetic material layers 172 It is electrically contacted the fixed polarization that layer 178 is contacted and fixed with the wherein leading direction of magnetization.The fixed layer is generally than certainly By thickness much.Thus, layer 172 is referred to as into fixed layer.The leading direction of magnetization of fixed layer 172 is by the section view in Fig. 1 E In the arrow 180 that points to the bottom of from representing.

Another ferromagnetic material layers 174a is electrically contacted layer 181 and contacts and be referred to as " free layer ", and it has wherein can be with Selectively change the changeable polarization of the leading direction of magnetization of free layer.The leading direction of magnetization of free layer 174a is by same The arrow 182a that sample is pointed in the section view of Fig. 1 E the bottom of from is representing.

In the example of Fig. 1 E, the leading direction of magnetization of both free layer and fixed layer 174a, 172 is depicted as being identical , that is to say, that in the same direction.If the leading direction of magnetization of two ferromagnetic layers 172,174 is identical, the pole of two layers Change is referred to as " parallel ".In parallel polarization, bit location shows low resistance state, and it can be selected to expression and is stored in One in logic one or logical zero in bit location.If the leading direction of magnetization of two ferromagnetic layers is conversely, as passed through Fig. 1 F In arrow 180（Bottom is upwards）And 182b（Top is downward）Shown, then the polarization of two layers 172,174b is referred to as " anti-flat OK ".In antiparallel polarization, bit location shows high resistance state, and it can be selected to represent and is stored in bit location Another in logic one or logical zero.

Polarization and thus the logical bit value that is stored in the bit location 64 of STTRAM 66 can be arranged by control circuit 68 Particular state, the control circuit 68 is configured to transmit in particular directions spin polarized current by the ferromagnetic of bit location 64 Device 170.Therefore, it can by transmitting spin polarized current in one direction by the ferromagnetic device 170 of bit location 64 Logic one is stored in the bit location 64 of STTRAM 66.As a result, the ferromagnetic layer tool of the ferromagnetic device 170 of bit location 64 It is the polarization of in Parallel and antiparallel to have, and depending on this, polarization has been selected to represent logic one.

On the contrary, can pass through control circuit 68 transmits in the opposite direction spin polarized current by the ferromagnetic of bit location Device 170 and logical zero is stored in the bit location 64 of STTRAM 66.As a result, the ferromagnetic device 170 of bit location 64 Ferromagnetic layer have be parallel or antiparallel in another polarization, depending on this, polarization have been selected to represent logical zero.

STTRAM uses the magnetization switching caused based on spin polarized current（switching）Special writing mechanism.Figure 2A-2B illustrates the schematic diagram of the primary element of typical STTRAM bit locations 64, and the STTRAM bit locations 64 include that switch is brilliant Body pipe 204 and variable resistance transistor unit R_mem（Element 202）.Combinative structure Jing is commonly referred to as 1T1R（One one, transistor Depositor）Unit.The bit line of bit location is more highlightedly shown in fig. 2b（BL, element 210）, wordline（WL, element 206）With source line or selection line（SL, element 208）, it has respectively corresponding voltage V_BL、V_WLAnd V_SL.Transistor 204 serves as choosing Device switch is selected, and resistive element 202 can be MTJ（MTJ）Device, such as device 70（Fig. 1 C, 1D）, it includes leading to Cross 76 detached two soft iron magnetosphere 72,74a of knot layer（Or 74b）, layer 72 has fixes " reference " direction of magnetization 80, and another It is individual with changeable magnetization direction 82a, 82b.Fig. 2 B are illustrated, although only exist a read direction（It is labeled as the arrow of RD）, but Be write operation can be two-way（It is labeled as the double-headed arrow of WR）.Therefore, the 1T1R structures can be described as having list Pole " reading " and the 1T-1STT MTJ memory units of bipolar " write ".

By the way that bit line BL is precharged to into V_RDAnd write line WL is selected to be connected with voltage V to allow it to work as_CCWhen declined by unit Subtract to read bit location 64, as shown in the graph of figure 3, voltage V_CCON switch transistor 204.Consumed simultaneously using reference unit Reference voltage V_BLServe as sensing amplifier reference.With reference to both the BL for being accessed use PMOS current source clampers so that Even maintain constant difference in sensing amplifier input in very long access time.

In this example, logical zero is by variable resistance transistor unit R_mem（Element 202）High resistance state（Antiparallel Polarization（Fig. 1 D, 1F）To represent, the variable resistance transistor unit R_memIt is MTJ（MTJ）Device 70,170.Phase Instead, logic one is in this example by variable resistance transistor unit R_mem（Element 202）Low resistance state（Parallel polarization（Figure 1C、1E）To represent, the variable resistance transistor unit R_memIt is MTJ（MTJ）Device 70,170.Correspondingly, if Pre-charge voltage V_RDRelatively high value is decayed to, then logical zero（High resistance state）It is indicated as being stored in MTJ device 70,170 In.If on the contrary, pre-charge voltage V_RDRelatively low value is decayed to, then logic 1（Low resistance state）It is indicated as being stored in In MTJ device 70,170.（Understand, in other embodiments, logical zero can be by variable resistance transistor unit R_mem（Unit Part 202）Low resistance state（Parallel polarization（Fig. 1 C, 1E））To represent.On the contrary, logic 1 can be by variable resistance transistor Element R_mem（Element 202）High resistance state（Antiparallel polarizes（Fig. 1 D, 1F））To represent）.

In in order to be written to bit location 64, using by control circuit 68（Figure 1B）The two-way writing scheme of control.In order to write Enter wherein variable resistance transistor unit R_mem（Element 202）State from antiparallel state（Fig. 1 D, 1F）Change to parastate （Fig. 1 C, 1D）Logic 1, bit line BL is charged to into V_CCAnd selection line SL is connected to ground so that electric current flow to from bit line BL Selection line SL.Conversely, in order to write wherein variable resistance transistor unit R_mem（Element 202）State from parastate（Figure 1C、1E）Change to antiparallel state（Fig. 1 D, 1F）Logical zero, using have rightabout electric current.Correspondingly, in V_CCPlace Selection line SL and the bit line BL in ground make electric current flow to bit line BL, rightabout from selection line SL.

Understand herein, from a state change to another state be asymmetric by the magnetic polarization of bit location 64 's.More specifically, understand, by the state of bit location 64 from parastate（Fig. 1 C, 1E）Change to antiparallel state（Fig. 1 D, 1F）Write time in some instances can substantially longer than for the write time of reverse situation, that is to say, that by position list The state of unit 64 is from antiparallel state（Fig. 1 D, 1F）Change to parastate（Fig. 1 C, 1E）Write time.For example, at some Can be than being directed to antiparallel to writing that parastate changes for the parallel write time changed to antiparallel state in example The bigger order of magnitude of the order of magnitude of the angle of incidence.

According to the one side of this specification, understand, can be by being conducted through bit location in appropriate reset current Substantially reduced by bit location 64 for flat so that its state is changed to guiding magnetic field during antiparallel state from parastate The write time that row changes to antiparallel state.Fig. 4 A are the subarrays 310 of the bit location 64 of array 60（Figure 1B）MTJ device 70（Fig. 1 C, 1D）The subarray 300 of free ferromagnetic 74a, 74b schematically show.The magnetic for such as being represented by magnetic field line 320 Field is conducted through the subarray 310 of the bit location 64 of array 60（Figure 1B）MTJ device 70（Fig. 1 C, 1D）Free layer 74a, 74b.In the illustrated embodiment, magnetic field 320 and the antiparallel polarization ferromagnetic layer 74b for such as being represented by arrow 82b（Fig. 1 D）'s Direction of magnetization general parallel orientation is aligned.By the alignment of general parallel orientation, it means that the magnetic field of the bit location through subarray 310 Scopes of the differential seat angle A between direction of magnetization 82b of 320 field wire and the free ferromagnetic 74b of antiparallel polarization in 0-90 degree It is interior, such as in one embodiment approximate 45 degree.

Conversely, in the illustrated embodiment, magnetic field 320 and the parallel polarization ferromagnetic layer 74a for such as being represented by arrow 82a （Fig. 1 C）The direction of magnetization substantially anti-parallel alignment.By substantially anti-parallel alignment, it means that through the position list of subarray 310 Differential seat angle B between the field wire in magnetic field 320 and direction of magnetization 82a of parallel-polarized free ferromagnetic 74a of unit is in 90-180 In the range of degree, such as in one embodiment approximate 135 degree.Such arrangement is considered as promoting from parallel polarization（Fig. 1 C）Arrive Antiparallel polarizes（Fig. 1 D）State change so that by polarized state from parallel polarization state change be directed to magnetic field 320 During the anti-parallel polarization state of the MTJ device 70 of each bit location 64 for passing through, reset current can reduce, or during write Between can reduce, or reset current can reduce and the write time can be reduced.

Fig. 4 b illustrate the bit location 64 for being arranged in memory array 60（Figure 1B）Subarray 310 on multiturn electromagnetic wire The example of circle 400.Bit location 64（Figure 1B）Subarray 310 define plane 410, and in this embodiment, coil 400 it is every One circle 420 is located at orthogonal with bit location plane 410 so that the field wire 320 in magnetic field is drawn with the aligned in general of bit location plane 410 Turned on the bit location of subarray 310.By aligned in general, it means that bit location plane 410 with pass through bit location subarray Differential seat angle between the field wire in 310 magnetic field 320 in the range of 45 to -45 degree, such as in one embodiment approximate 0 degree.

Multiturn coil 400 can be made using various technologies.One such technology uses metal layer, through hole and horizontal stroke Multiturn coil is formed to pipeline.Other technologies can use other conductive materials（Such as doped semi-conducting material）Carry out shape Into multiturn coil.In the illustrated embodiment, each circle 420 is formed by the conductive layer being spaced, its conductive through hole with interval Link.Neighbouring circle is linked with the horizontal pipeline at interval.For make multiturn coil another technology can include metallization and Silicon hole（TSV）, it is frequently used for three dimensional integrated circuits stacking.Understand, depending on application-specific, suitable coil can be with Circle with fewer or greater number, can have other shapes and other positions.

In order to generate magnetic field 320, make driving current in the counterclockwise direction through the circle 420 of solenoid 400, such as by arrow Indicated by 430, can be generated contrary through the circle 420 of coil 400 in the clockwise direction by making driving current The magnetic field that side boots up.Driving current can pass through control circuit 68（Figure 1B）Optionally turned on and off, the control Circuit processed 68 is configured to provide appropriate enable signal to switching transistor 440（En、En（Bar））.In shown embodiment In, go to the driving current of coil 400 can be switched on with the bit location of subarray 310 is switched to from parallel polarization state The reset current of anti-parallel polarization state one is shown to provide the magnetic of state change is aided at least in part.

The section view of Fig. 5 A and Fig. 5 B is the subarray 310 of the bit location 64 of array 60（Figure 1B）MTJ device 170 （Fig. 1 E, 1F）The alternative embodiment of subarray 300a of free ferromagnetic 174a, 174b schematically show.Such as by magnetic field The magnetic field that line 320a is represented is conducted through the subarray 310 of the bit location 64 of array 60（Figure 1B）MTJ device 170（Fig. 1 E, 1F）Free layer 174a, 174b.In the illustrated embodiment, magnetic field 320a is generally perpendicular to bit location plane 410（Figure 1B） And with the antiparallel polarization ferromagnetic layer 174b for such as being represented by arrow 182b（Fig. 1 F）The direction of magnetization general parallel orientation alignment.Pass through General parallel orientation is aligned, it means that the freedom of the field wire and antiparallel polarization through the magnetic field 320a of the bit location of subarray 300a Differential seat angle between direction of magnetization 182b of ferromagnetic layer 174b is in one embodiment in the range of 45 to -45 degree.Fig. 5 A, In the embodiment described in 5B, through the free ferrum of the field wire and antiparallel polarization of the magnetic field 320a of the bit location of subarray 310 Differential seat angle between direction of magnetization 182b of magnetosphere 174b generally zero.

Conversely, in the illustrated embodiment, magnetic field 320a and the parallel polarization ferromagnetic layer for such as being represented by arrow 182a 174a（Fig. 1 E）The direction of magnetization substantially anti-parallel alignment.By substantially anti-parallel alignment, it means that the field wire in magnetic field 320 with Differential seat angle between direction of magnetization 182a of parallel-polarized free ferromagnetic 174a is in one embodiment in 135 to 225 degree In the range of.In the embodiment described in figs. 5 a, 5b, through the bit location of subarray 310 magnetic field 320a field wire with it is flat Differential seat angle generally 180 degree between direction of magnetization 182a of the free ferromagnetic 174b of row polarization.Such arrangement is considered as Promote from parallel polarization（Fig. 1 E）To antiparallel polarization（Fig. 1 F）State change so that by polarized state from parallel polarization shape When state changes the anti-parallel polarization state of the MTJ device 170 of each bit location 64 being conducted through to magnetic field 320a, write Electric current can reduce, or the write time can be reduced, or reset current can reduce and the write time can be reduced.

Fig. 5 C illustrate the bit location 64 for being arranged in memory array 60（Figure 1B）Subarray 310 on multiturn electromagnetic wire The example of circle 500.Bit location 64（Figure 1B）Subarray 310 define plane 410, and in this embodiment, coil 500 it is every One circle 520 is located at parallel with bit location plane 410 so that the field wire 320a in magnetic field is conducted through subarray 310 generally normally Bit location bit location plane 410.By generally normal, it means that bit location plane 410 with pass through bit location subarray Differential seat angle between the field wire of 310 magnetic field 320a is more than in one embodiment 45 degree.In another embodiment, bit location is put down Differential seat angle face 410 and the field wire through the magnetic field 320a of bit location subarray 310 is approximate 90 degree.

Multiturn coil 500 can be made using various technologies.One such technology uses metal layer, through hole and horizontal stroke Multiturn coil is formed to pipeline.Other technologies can use other conductive materials（Such as doped semi-conducting material）Carry out shape Into multiturn coil.In the illustrated embodiment, each circle 520 is formed by the conductive layer being spaced, its conductive through hole with interval With the horizontal pipeline link at interval.Neighbouring circle is linked with the through hole at interval.Another technology for making multiturn coil can be with Including metallization and silicon hole（TSV）, it is frequently used for three dimensional integrated circuits stacking.Understand, depending on application-specific, close Suitable coil can have the circle of fewer or greater number, can have other shapes and other positions.

In order to generate magnetic field 320a, make driving current in the clockwise direction through the circle 520 of coil 500, such as by arrow Indicated by 530.Can be generated contrary through the circle 520 of coil 500 in the counterclockwise direction by making driving current 540 The magnetic field 320b that side boots up（Fig. 5 D）.Driving current can pass through control circuit 68（Figure 1B）Optionally connected and closed Disconnected, the control circuit 68 is configured to provide appropriate enable signal to switching transistor 540（En、En（Bar））.Illustrated Embodiment in, go to the driving current of coil 500 can be switched on with by the bit location of subarray 310 from parallel polarization shape State is switched to the reset current of anti-parallel polarization state and one shows and provide the magnetic to state change and aid at least in part.

In example described above, it is possible to use the magnetic auxiliary provided by associated magnetic field 320,320a, 320b By the bit location 64 of whole subarray 310（Figure 1B）Together from parallel polarization state（Fig. 1 C, 1E）It is switched to antiparallel polarization shape State（Fig. 1 D, 1F）.For simplicity, the subarray 310 of Figure 1B is depicted as including that the 3 of bit location takes advantage of 3 subarrays.Understand Arrive, can be using auxiliary magnetic field with disposably by corresponding polarized state from the parallel position list for being switched to antiparallel polarization for it The number of unit can depend on application-specific and change.Because Modern memory generally has many gigabytes of storage（Or it is more） The capacity of data, thus subarray 310 can include a bit location, or can include dozens of, it is hundreds of, thousands of, Tens thousand of or more bit locations, pin is used for magnetic auxiliary as described herein and comes disposable by its corresponding polarized state Antiparallel polarization is switched to from parallel.

In the illustrated embodiment, antiparallel polarization, high resistance state are selected to represent and are stored in bit location Logical zero.Correspondingly, logical zero can be written in each bit location of subarray 310, actually " wiped " and be stored in Any data in subarray 310.Already at antiparallel polarization, high electricity before the erasing operation of subarray 310 is applied to Any bit location in resistance state is maintained at after an erase operation in antiparallel polarization, high resistance state as overall.Control Circuit 68 be configured to by provide magnetic aid in it is appropriate parallel to anti-flat with each bit location by subarray 310 Row state change reset current wiping the whole subarray of bit location, as described above.Once subarray 310 is all Bit location 64 has been wiped free of so that they store logical zero, it is possible to which write data are written to into a part for subarray （Such as word, row or page）In.Due to by wiping subarray logical zero being written in subarray, therefore by data Being written in subarray can be limited to be only written the place value of the write data for being logic one.

In the illustrated embodiment, parallel polarization, low resistance state are selected to represent and are stored in patrolling in bit location Collect one.Thus, in order to logic one to be written to the bit location for being initially at the antiparallel polarization for representing logical zero, high resistance state In, appropriate antiparallel to parastate changes reset current and is driven through specific bit location with by the polarized state of bit location It is switched to from antiparallel parallel.As mentioned before, it is switched to antiparallel pole from parallel with by the polarized state of STT bit locations Change is compared, and the polarized state of STT bit locations is switched to from antiparallel and parallel typically requires that substantially less write time And power.Correspondingly, in one embodiment, it is flat so that the polarized state of bit location to be switched to from antiparallel in write logic one Auxiliary magnetic field can be omitted during row.Understand, in other embodiments, appropriate auxiliary magnetic field can be conducted through position list Unit for two state changes, that is to say, that otherwise from it is parallel to antiparallel polarization and.Further appreciate that, at other In embodiment, antiparallel polarization, high resistance state can be selected to represent the logic one being stored in bit location, and parallel Polarization, low resistance state can be selected to represent the logical zero being stored in bit location.

Fig. 6 A illustrate that length is eight and comprising the sequence of logic one and zero（In this example " 10011010 "）Write Enter the example of data row.Control circuit 68（Figure 1B）It is configured to only logic one is written to into bit location 64a, the Jing of 64b ... 64h The row of erasing（Fig. 6 B）.Correspondingly, control circuit 68 is further configured to for the logical zero of the row of write data to be considered as " holding " value, As represented by alphabetical " H " so that polarized state and thus bit location 64a, 64b ... 64h（Fig. 6 B）Erased row The place value of correspondence bit location is maintained, that is to say, that keep constant.Therefore, data sequence " 10011010 " is write by control electricity Road 68 is efficiently converted into write sequence " 1HH11H1H ", as shown in FIG, wherein only logic one will be written to bit location The erased row of 64a, 64b ... 64h, as depicted in figure 6b.

Control circuit 68 is configured to for each value of logic one of write sequence " 1HH11H1H " to be written to corresponding position In unit, as shown in by bit location 64a, 64d, 64e and 64g of Fig. 6 C.In this example, by the shape by bit location is corresponded to State changes to low resistance, parallel polarization state to write logic one from high resistance, anti-parallel polarization state.Conversely, by write sequence Each in the retention value that the alphabetical H of row " 1HH11H1H " is represented keeps control circuit 68 or maintenance state and thus guarantor The place value for storing before of the logical zero in each in correspondence bit location 64b, 64c, 64f and 64h is held or maintains, it is described right Answer and wiped by the erasing function that first magnetic field aids in before bit location.In this example, logical zero is in this example by height Resistance, antiparallel state are represented.

Fig. 7 depicts the behaviour of the MRAM aided according to the magnetic field of such as STTRAM etc of one embodiment of this specification The example of work.In this example, control circuit 68 is configured to perform described operation.

In the first operation, reception will be written to corresponding to memorizer（Such as subarray 310）In bit location The write data of the logical address of the first physical address（Block 710）.Conversion write data（Block 714）So that the logic of write data Zero is considered " holding " value, as described by combining such as Fig. 6 A.In this way, changing write data causes all zero to be kept State replaces.In this example, logical zero is represented by the high resistance of bit location of STTRAM, anti-parallel polarization state.Understand Arrive, in other embodiments, logic one can be represented by the high resistance of the bit location of STTRAM, anti-parallel polarization state. In such embodiment, by conversion write data（Block 714）So that the logic one rather than logical zero of write data are considered " to protect Hold " value.

In this example, the physical cord of STTRAM is distributed to logic line.Mark（Block 720）With the logical address of write data The associated physical address of destination and make whether " clean with regard to the bit location of the physical address（clean）”（Namely Say, be erased to all logical zeros）Determination（Block 724）.If it is, can be with the similar side with description in Fig. 6 C Formula will write the write of logic one of data in the case where remaining of holding zero value is not changed（Block 730）To the physical address Corresponding bit location.Correspondingly, be considered the logical zero of the write data of retention value make the corresponding bit location of the physical address with It is retained in the logic zero state with the similar mode described in Fig. 6 C.

On the contrary, if it is determined that（Block 724）The bit location of the physical address is not " clean ", that is to say, that comprising one or Multiple logics one are worth, then the first physical address is deactivated（Block 732）.

Make with regard to clean physical address（That is, wherein all bit locations have been erased to all logics Zero physical address）The whether available determination in subarray（Block 740）.If it is, to the logical address of write data Destination distributes（Block 744）Clean physical address.Fig. 8 A and 8B depict the magnetic field auxiliary of the array 60 for bit location 64 Memorizer control circuit 68 logic to physical address map logic 810 example, its will for memory lines logically Location is from memory lines 814a for subarray 310（Fig. 8 A）The first physical address be remapped to for subarray 310 not With the second physical address of memory lines 814b（Fig. 8 B）.

Furthermore, it is possible to so that the write of logic one of data will be write with the similar mode described in Fig. 6 C（Block 730）Arrive The corresponding bit location of the second physical address.Correspondingly, be considered the logical zero of the write data of retention value with Fig. 6 C in describe Similar mode make the corresponding bit location of the second physical address be retained in the logic zero state.

On the contrary, if it is determined that（Block 740）Clean physical address（That is, wherein all bit locations are wiped Except the physical address into all logical zeros）It is unavailable in subarray, then select（Block 750）Can use and blank（It is i.e. clean） Bit location the second subarray, and all valid data in original, the first subarray are transferred to into second, selected submatrix Row.With the similar mode that describes with combined block 730 by the way that the logic one of effective transfer data to be written to the mesh of the second array Physical addresses shifting data.After effective transfer data have been shifted to the second subarray, can be auxiliary in magnetic field The first subarray of lower erasing is helped, as described herein.

Additionally, to received write data（Block 710）Logical address destination distribution（Block 744）Second subarray The 3rd, clean, physical address and can with the similar mode described in Fig. 6 C by received write number According to logic one write（Block 730）To the corresponding bit location of the 3rd physical address of the second subarray.Correspondingly, it is considered to keep The logical zero of the received write data of value makes the 3rd thing of the second subarray with the similar mode with description in Fig. 6 C The corresponding bit location of reason address is retained in the logic zero state.

Example

The example below is with regard to further embodiment.

Example 1 is a kind of device, including：The magnetic resistance of the first subarray with MRAM bit locations（MRAM）The battle array of bit location Row, each of which bit location includes the ferromagnetic device with polarization, and the polarization is in a first state Parallel and antiparallel One in polarization and be in the second state another in Parallel and antiparallel polarization；Control circuit, it is configured to By the state change of the bit location of the first subarray in first state into the second state so that the position list of the first subarray The ferromagnetic device of unit has the polarization shown by the bit location in the second state；And electromagnet, it is located at neighbouring the One subarray passes through the ferromagnetic device of the bit location of the first subarray to aid in the array of the bit location of MRAM to guide magnetic field The first subarray bit location state from first state change to the second state.

In example 2, example 1-10（Exclude this example）Theme can alternatively include, wherein the MRAM bit locations It is spin transfer torque（STT）Random access memory（RAM）Bit location, the control circuit is configured to guide spin polarization Electric current is by the ferromagnetic device of the bit location of the first subarray with the bit location of the first subarray that will be in first state State change is into the second state so that the ferromagnetic device of the bit location of the first subarray has by the position list in the second state The polarization that unit shows；The control circuit is further configured to selected by guiding spin polarized current passes through the first subarray first The ferromagnetic device of bit location with by the way that bit location selected by the first of the first subarray is returned to into first state from the second state change, So that one be changed back in the logic one and logical zero of each the first selected bits cell list registration evidence of first state In to write data into those bit locations selected by first of the first subarray, and wherein described control circuit is further configured to The state of bit location selected by the second of the first subarray is maintained in the second state so that be maintained in the second state is every Another in the logic one and logical zero of one the second selected bits cell list registration evidence.

In example 3, example 1-10（Exclude this example）Theme can alternatively include, wherein the control circuit is also The data of the bit location for being configured to wipe the first subarray, the state of the bit location of the erasing including the first subarray is from the The change of the magnetic field auxiliary of one state to the second state so that all bit locations of the first subarray show to represent logic One and logical zero in another second state.

In example 4, example 1-10（Exclude this example）Theme can alternatively include, wherein the electromagnet includes It is adjacent to the coil of the first subarray arrangement.

In example 5, example 1-10（Exclude this example）Theme can alternatively include that the first of its bit cell is sub Array is arranged in the planes, wherein each ferromagnetic device of each bit location of the first subarray has ferromagnetic layer, institute State ferromagnetic layer and there is the direction of magnetization being in the plane of the first subarray of bit location, wherein the coil includes multiple circles, Each of which circle is generally normal to the plane of the first subarray of bit location to be orientated, and wherein described electromagnet is positioned in It is in substantially parallel relationship on the direction of the direction of magnetization of the ferromagnetic layer of the ferromagnetic device of the bit location of the plane and the first subarray and draws Magnetic conduction field.

In example 6, example 1-10（Exclude this example）Theme can alternatively include that the first of its bit cell is sub Array is arranged in the planes, wherein each ferromagnetic device of each bit location of the first subarray has ferromagnetic layer, institute The direction of magnetization that ferromagnetic layer has the plane of the first subarray for being generally normal to bit location is stated, wherein the coil is including multiple Circle, each of which circle is in substantially parallel relationship to the plane of the first subarray of bit location to be orientated, and wherein described electromagnet is determined Position into be generally normal to the plane and be in substantially parallel relationship to the first subarray bit location ferromagnetic device ferromagnetic layer The side of the direction of magnetization boots up magnetic field.

In example 7, example 1-10（Exclude this example）Theme can alternatively include, wherein the control circuit is also It is configured to：Receive for the logical address that is associated with the first physical memory address in the first subarray of bit location Write data；Whether the bit location for determining the first physical memory address all changes over the second state so that the first physical store All bit locations of device address show to represent logic one and another second state in logical zero；And if really The bit location of fixed first physical memory address all changes over the second state, then guide spin polarized current to pass through the first submatrix Row first selected by bit location ferromagnetic device with by by bit location selected by the first of physical memory address from the second state First state is changed back to so that being changed back to represent patrolling for write data to each first selected bits unit of first state Volume one and logical zero in it is one to write data into the first physical memory address first selected by bit location, and And the state of bit location selected by the second of the first physical memory address of maintenance causes to maintain the second shape in the second state Each in state the second selected bits unit represent write data logic one and logical zero in it is described another.

In example 8, example 1-10（Exclude this example）Theme can alternatively include, wherein the control circuit is also It is configured to：If it is determined that at least some in the bit location of the first physical memory address is changed to first state, then really Whether the bit location of available second physical memory address of the first subarray of positioning unit all changes over the second state makes The all bit locations for obtaining the second physical memory address show to represent logic one and another second in logical zero State；And if it is determined that the second state can all be changed over the bit location of the second physical memory address, then make the first thing The bit location of reason storage address is invalid, and to the logical storage address of write data the second physical memory address is distributed, and And the ferromagnetic device of bit location selected by guide that spin polarized current passes through the second physical memory address first is with by by the Bit location selected by the first of two physical memory address returns to first state so that being changed back to first from the second state change Each first selected bits unit of state is represented in the logic one and logical zero of write data and one will write number According to be written to the second physical memory address first selected by bit location, and maintain the second of the second physical memory address The state of selected bit location causes to be maintained each second selected bits cell list in the second state in the second state Show write data logic one and logical zero in it is described another.

In example 9, example 1-10（Exclude this example）Theme can alternatively include, wherein the control circuit is also It is configured to：If it is determined that all bit locations that there is no wherein available physical memory address are changed to the position of the second state Available second physical memory address of the first subarray of unit, then select available second subarray of bit location, its middle position All bit locations of the second subarray of unit show to represent logic one and another second state in logical zero； And distribute the 3rd physical memory address of the second subarray to the logical storage address of write data, and by by the Bit location selected by the first of three physical memory address returns to first state so that being changed back to first from the second state change Each first selected bits unit of state represent write data logic one and logical zero in it is one and by dimension The state for holding bit location selected by the second of the 3rd physical memory address is in the second state so that being maintained at the second state In each second selected bits unit represent write data logic one and logical zero in described another will write number According to being written in the bit location of the 3rd physical memory address.

In example 10, example 1-10（Exclude this example）Theme can alternatively include, wherein the control circuit It is further configured to：Will be stored in all valid data in the first subarray to be transferred to the second subarray of bit location and wipe The data of the bit location of the first subarray, the state of the bit location of the erasing including the first subarray is from first state to second The change of the magnetic field auxiliary of state causes all bit locations of the first subarray to show to represent in logic one and logical zero Another second state.

Example 11 is directed to a kind of computing system used for display, including：Memorizer；Processor, it is configured to Data are write in memorizer and from memory read data；And Video Controller, it is display configured to by memorizer The information that data are represented；Wherein memorizer includes magnetoresistive RAM（MRAM）, it includes：With MRAM bit locations The array of the MRAM bit locations of the first subarray, each of which bit location includes the ferromagnetic device with polarization, the polarization In a first state in Parallel and antiparallel polarization and in the second state in Parallel and antiparallel polarization Another；Control circuit, its be configured to guide spin polarized current by the ferromagnetic device of the bit location of the first subarray with By the state change of the bit location of the first subarray in first state into the second state so that the position list of the first subarray The ferromagnetic device of unit has the polarization shown by the bit location in the second state；And electromagnet, it is located at neighbouring the One subarray passes through the ferromagnetic device of the bit location of the first subarray to aid in the bit location of STT MRAM to guide magnetic field The state of the bit location of the first subarray of array changes to the second state from first state.

In example 12, example 11-20（Exclude this example）Theme can alternatively include, wherein MRAM positions list Unit is spin transfer torque（STT）Random access memory（RAM）Bit location, the control circuit is configured to guiding spin pole The bit location of first subarray of the ferromagnetic device of the bit location that galvanic current passes through the first subarray being in first state State change into the second state so that the ferromagnetic device of the bit location of the first subarray has by the position in the second state The polarization that unit shows；The control circuit is further configured to guide first institute of the spin polarized current by the first subarray The ferromagnetic device of bit selecting unit from the second state change by bit location selected by the first of the first subarray with by returning to the first shape State causes the institute being changed back in the logic one and logical zero of each the first selected bits cell list registration evidence of first state During one is stated to write data into those bit locations selected by first of the first subarray, and wherein described control circuit also by The state for being configured to bit location selected by the second of the first subarray of maintenance is in the second state so that being maintained at the second state In each the second selected bits cell list registration evidence logic one and logical zero in it is described another.

In example 13, example 11-20（Exclude this example）Theme can alternatively include, wherein the control circuit The data of the bit location for being further configured to wipe the first subarray, the state of the bit location of the erasing including the first subarray from The change that first state is aided in the magnetic field of the second state so that all bit locations of the first subarray show expression and patrol Collect one and another second state in logical zero.

In example 14, example 11-20（Exclude this example）Theme can alternatively include, wherein the electromagnet bag Include and be arranged the coil for being adjacent to the first subarray.

In example 15, example 11-20（Exclude this example）Theme can alternatively include, the first of its bit cell Subarray is arranged in the planes, wherein each ferromagnetic device of each bit location of the first subarray has ferromagnetic layer, The ferromagnetic layer has the direction of magnetization in the plane in the first subarray of bit location, wherein the coil is including multiple Circle, each of which circle is generally normal to the plane of the first subarray of bit location to be orientated, and wherein described electromagnet is determined Side of the position into the direction of magnetization of the ferromagnetic layer of the ferromagnetic device in the bit location for being in substantially parallel relationship to the plane and the first subarray Boot up magnetic field.

In example 16, example 11-20（Exclude this example）Theme can alternatively include, the first of its bit cell Subarray is arranged in the planes, wherein each ferromagnetic device of each bit location of the first subarray has ferromagnetic layer, The ferromagnetic layer has the direction of magnetization of the plane of the first subarray for being generally normal to bit location, wherein the coil is including more Individual circle, each of which circle is in substantially parallel relationship to the plane of the first subarray of bit location to be orientated, and wherein described electromagnet quilt It is positioned in the ferromagnetic layer of the ferromagnetic device of the bit location for being generally normal to the plane and being in substantially parallel relationship to the first subarray The side of the direction of magnetization boot up magnetic field.

In example 17, example 11-20（Exclude this example）Theme can alternatively include, wherein the control circuit It is further configured to：Receive the logical address for being associated with the first physical memory address in the first subarray of bit location Write data；Whether the bit location for determining the first physical memory address all changes over the second state so that the first physics is deposited All bit locations of memory address show to represent logic one and another second state in logical zero；And if The bit location for determining the first physical memory address all changes over the second state, then guide spin polarized current by first The ferromagnetic device of bit location selected by the first of array with by by bit location selected by the first of physical memory address from the second shape State changes back to first state so that being changed back to represent write data to each first selected bits unit of first state One in logic one and logical zero to write data into the first physical memory address first selected by bit location, And the state for maintaining bit location selected by the second of the first physical memory address is in the second state so that maintaining second Each in state the second selected bits unit represent write data logic one and logical zero in it is described another.

In example 18, example 11-20（Exclude this example）Theme can alternatively include, wherein the control circuit It is further configured to：If it is determined that at least some in the bit location of the first physical memory address is changed to first state, then Whether the bit location for determining available second physical memory address of the first subarray of bit location all changes over the second state So that all bit locations of the second physical memory address show to represent another the in logic one and logical zero Two-state；And if it is determined that the second state can all be changed over the bit location of the second physical memory address, then make first The bit location of physical memory address is invalid, and the second physical memory address is distributed in the logical storage address to write data, And guide spin polarized current pass through the second physical memory address first selected by bit location ferromagnetic device with pass through general Bit location selected by the first of second physical memory address returns to first state so that being changed back to from the second state change Each first selected bits unit of one state represents one will write in the logic one and logical zero of write data Data be written to the second physical memory address first selected by bit location, and maintain the of the second physical memory address The state of bit location selected by two causes to be maintained each bit location selected by second in the second state in the second state Represent write data logic one and logical zero in it is described another.

In example 19, example 11-20（Exclude this example）Theme can alternatively include, wherein the control circuit It is further configured to：If it is determined that all bit locations that there is no wherein available physical memory address are changed to the second state Available second physical memory address of the first subarray of bit location, then select available second subarray of bit location, wherein All bit locations of the second subarray of bit location show to represent logic one and another second shape in logical zero State；And distribute the 3rd physical memory address of the second subarray to the logical storage address of write data, and pass through Bit location selected by the first of 3rd physical memory address is returned to into first state from the second state change so that be changed back to Each first selected bits unit of first state represents one and logical in the logic one and logical zero of write data The state for crossing bit location selected by the second of the 3rd physical memory address of maintenance is in the second state so that being maintained at second Each in state the second selected bits unit represents that described another in the logic one and logical zero of write data will be write Enter data to be written in the bit location of the 3rd physical memory address.

In example 20, example 11-20（Exclude this example）Theme can alternatively include, wherein the control circuit It is further configured to：Will be stored in all valid data in the first subarray to be transferred to the second subarray of bit location and wipe The data of the bit location of the first subarray, the state of the bit location of the erasing including the first subarray is from first state to second The change of the magnetic field auxiliary of state causes all bit locations of the first subarray to show to represent in logic one and logical zero Another second state.

Example 21 is for a kind of operation magnetoresistive RAM（MRAM）Method, including：The bit location of MRAM The state of the bit location of the first subarray of array is from first state to the change of the magnetic field of the second state auxiliary so that first is sub The bit location of the altered state of array shows the second state, and wherein first state represents in logic one and logical zero And another in the second state representation logic one and logical zero, each of which bit location includes the ferromagnetic device with polarization Part, the polarization in Parallel and antiparallel polarization and is in a first state in the second state parallel and anti-flat Another in row polarization, and changes of wherein magnetic field auxiliary includes ferrum of the guiding magnetic field by the bit location of the first subarray Magnetic device is aiding in changing the state of the bit location of the first subarray of the array of the bit location of MRAM to the from first state Two-state.

In example 22, example 21-30（Exclude this example）Theme can alternatively include, wherein the MRAM be from Rotation moves torque（STT）The change of MRAM and magnetic field auxiliary also includes position of the guiding spin polarized current by the first subarray The ferromagnetic device of unit with will be in first state in the first subarray bit location state change into the second state so that The ferromagnetic device of the bit location of the first subarray has the polarization shown by the bit location in the second state, methods described Also include：

By bit location selected by the first of the first subarray is returned to into first state from the second state change so that be changed back to One in the logic one and logical zero of each the first selected bits cell list registration evidence of first state and by dimension The state of bit location selected by the second of the first subarray is held in the second state so that be maintained in the second state is each In the logic one and logical zero of individual second selected bits cell list registration evidence it is described another writing data into the first submatrix In the bit location of row.

In example 23, example 21-30（Exclude this example）Theme can alternatively include, wipe first subarray The data of bit location, the erasing includes the magnetic of the state of the bit location of the first subarray from first state to the second state The change of auxiliary so that all bit locations of the first subarray show to represent in logic one and logical zero it is described another The second state.

In example 24, example 21-30（Exclude this example）Theme can alternatively include, wherein the introduction by magnetic field The coil for being adjacent to the first subarray generation magnetic field is arranged including using.

In example 25, example 21-30（Exclude this example）Theme can alternatively include, the first of its bit cell Subarray is arranged in the planes, wherein each ferromagnetic device of each bit location of the first subarray has ferromagnetic layer, The ferromagnetic layer has the direction of magnetization in the plane in the first subarray of bit location, wherein the coil is including multiple Circle, each of which circle is generally normal to the plane of the first subarray of bit location to be orientated, and wherein described introduction by magnetic field bag Include the direction of the direction of magnetization of the ferromagnetic layer of ferromagnetic device in the bit location for being in substantially parallel relationship to the plane and the first subarray Upper guiding magnetic field.

In example 26, example 21-30（Exclude this example）Theme can alternatively include, the first of its bit cell Subarray is arranged in the planes, wherein each ferromagnetic device of each bit location of the first subarray has ferromagnetic layer, The ferromagnetic layer has the direction of magnetization of the plane of the first subarray for being generally normal to bit location, wherein the coil is including more Individual circle, each of which circle is in substantially parallel relationship to the plane of the first subarray of bit location to be orientated, and wherein described introduction by magnetic field It is included in the ferromagnetic layer of the ferromagnetic device of the bit location for being generally normal to the plane and being in substantially parallel relationship to the first subarray The side of the direction of magnetization boots up magnetic field.

In example 27, example 21-30（Exclude this example）Theme can alternatively include, receive be directed to and bit location The first subarray in the associated logical address of the first physical memory address write data；Determine the first physical store The bit location of device address whether all changes over the second state so that all bit locations of the first physical memory address show Represent logic one and another second state in logical zero；And if it is determined that the position of the first physical memory address Unit all changes over the second state, then by the way that bit location selected by the first of physical memory address is returned from the second state change To first state so that being changed back to each first selected bits unit of first state represent the He of logic one of write data One in logical zero, the change includes guiding first institute of the spin polarized current by the first physical memory address The ferromagnetic device of bit selecting unit, and pass through to maintain the first physical memory address second selected by bit location state in the Cause to maintain each second selected bits unit in the second state to represent the logic one and logic for writing data in two-state Described another in zero is written to write data in the bit location of the first physical memory address.

In example 28, example 21-30（Exclude this example）Theme can alternatively include, if it is determined that the first physics At least some in the bit location of storage address is changed to first state, it is determined that the first subarray of bit location it is available The bit location of the second physical memory address whether all change over the second state so that the second physical memory address it is all Bit location shows to represent logic one and another second state in logical zero；And if it is determined that the second thing can be used The bit location of reason storage address all changes over the second state, then make the bit location of the first physical memory address invalid, to The second physical memory address is distributed in the logical storage address of write data, and by by the second physical memory address Bit location selected by first returns to first state from the second state change so that each first institute being changed back to first state Bit selecting unit represents one in the logic one and logical zero of write data, and the change includes guiding spin polarized current By the ferromagnetic device of bit location selected by the first of the second physical memory address, and by maintaining the second physical storage ground The state of bit location selected by the second of location causes to be maintained in the second state each in the second state selected by second Bit location represents that write data are written to the second physics and are deposited by described another in the logic one and logical zero of write data In the bit location of memory address.

In example 29, example 21-30（Exclude this example）Theme can alternatively include, if it is determined that there is no it All bit locations of middle available physical memory address are changed to available the of the first subarray of the bit location of the second state Two physical memory address, then select available second subarray of bit location, the institute of available second subarray of its bit cell There is bit location to show to represent logic one and another second state in logical zero；And to the logic of write data 3rd physical memory address of the subarray of memory allocation second, and by by the of the 3rd physical memory address Bit location selected by one return to first state from the second state change so that be changed back to first state each selected by first Bit location represent write data logic one and logical zero in it is one and by maintain the 3rd physical memory address Second selected by the state of bit location cause in the second state to be maintained each second selected bits in the second state Unit represents that write data are written to the 3rd physical store by described another in the logic one and logical zero of write data In the bit location of device address.

In example 30, example 21-30（Exclude this example）Theme can alternatively include, will be stored in the first submatrix All valid data in row are transferred to the second subarray of subelement and wipe the data of the bit location of the first subarray, institute Stating the change of magnetic field auxiliary of the state for wiping the bit location for including the first subarray from first state to the second state makes The all bit locations for obtaining the first subarray show to represent logic one and another second state in logical zero.

Example 31 is for a kind of including the device for performing the part such as the method described in any aforementioned exemplary.

Described operation can by using standard program and/or engineering technology with produce software, firmware, hardware or its Any combinations and be embodied as method, device or computer program.Described operation can be implemented as being maintained in " computer Computer program code in readable storage medium storing program for executing ", wherein processor can from Computer Storage computer-readable recording medium read code and Operation code.Computer-readable recording medium includes at least one of the following：Electronic circuit, storage material, inorganic material, have Machine material, biomaterial, shell, housing, coating and hardware.Computer-readable recording medium can including but not limited to, magnetic Storage medium（Such as hard disk drive, floppy disk, tape etc.）, optical storage device（CD-ROM, DVD, CD etc.）, volatibility and non- Volatile memory devices（Such as EEPROM, ROM, PROM, RAM, DRAM, SRAM, flash memory, firmware, FPGA Deng）, solid condition apparatus（SSD）Deng.Realize that the code of described operation can be to realize with hardware logic, the hardware logic Realize in hardware device（Such as IC chip, programmable gate array（PGA）, special IC（ASIC）Deng）In.Again Further, realizing the code of described operation can realize in " transmission signal ", and wherein transmission signal can be by sky Between or propagated by the transmission medium of such as optical fiber, copper cash or the like.Code or logic are coded in transmission signal therein Wireless signal, satellite transmission, radio wave, infrared signal, bluetooth etc. can also be included.It is embedded in computer-readable recording medium On program code can be transferred to receiving station or computer from transfer station or computer as transmission signal.Computer-readable is deposited Storage media not only includes transmission signal.It would be recognized by those skilled in the art that can be in the scope without departing from this specification In the case of make many modifications to the configuration, and manufacture can include Jie of suitable carrying information as known in the art Matter.Certainly, it would be recognized by those skilled in the art that can make to the configuration in the case of the scope without departing from this specification Many modifications, and manufacture can include the medium of any tangible carrying information as known in the art.

In some applications, can embody in computer systems according to the equipment of this specification, the computer system Including reproduction information be coupled on the monitor of computer system or other display show Video Controller, equipment drive Dynamic device and network controller, including desktop computer, work station, server, large scale computer, kneetop computer, handheld computer etc. Computer system.Alternatively, apparatus embodiments can be embodied in not including the computing device of such as Video Controller（Such as Switch, router etc.）Or for example not including in the computing device of network controller.

The illustrated logic of figure may illustrate some events for occurring in some order.In alternative embodiments, Some operations can be performed in a different order, be changed or removed.And, operation can be added to logic described above And still defer to described embodiment.In addition, operate as described herein can sequentially occur or some operations can With parallel processing.Yet further, operation can be performed by single processing unit or by distributed processing unit.

The described above of various embodiments has been presented for the purpose of illustration and description.It is not intended to be detailed Or it is limited to exact form disclosed.In view of many modifications of teachings above and modification are possible.

Claims

1. a kind of device, including：

The magnetic resistance of the first subarray with MRAM bit locations（MRAM）The array of bit location, each of which bit location includes tool There is the ferromagnetic device of polarization, the polarization is in a first state in Parallel and antiparallel polarization and in the second state In for Parallel and antiparallel polarization in another；

Control circuit, it is configured to the state change of the bit location of the first subarray in first state into the second shape State so that the ferromagnetic device of the bit location of the first subarray has the polarization shown by the bit location in the second state； And

Electromagnet, it is located at neighbouring first subarray to guide magnetic field to pass through the ferromagnetic device of the bit location of the first subarray with auxiliary Help and change the state of the bit location of the first subarray of the array of the bit location of MRAM to the second state from first state.

2. device according to claim 1, wherein the MRAM bit locations are spin transfer torques（STT）Random access memory is deposited Reservoir（RAM）Bit location, the control circuit is configured to the bit location for guiding spin polarized current to pass through the first subarray Ferromagnetic device with will be in first state in the first subarray bit location state change into the second state so that first is sub The ferromagnetic device of the bit location of array has the polarization shown by the bit location in the second state；The control circuit is also The ferromagnetic device of bit location is with by by first selected by be configured to guide spin polarized current to pass through the first subarray first Bit location returns to first state so that being changed back to each of first state from the second state change selected by the first of subarray One in the logic one and logical zero of individual first selected bits cell list registration evidence come write data into the first subarray that In bit location selected by a little first, and wherein described control circuit is further configured to maintain the second selected bits list of the first subarray The state of unit is in the second state so that being maintained each the second selected bits cell list registration evidence in the second state Another in logic one and logical zero.

3. device according to claim 1, wherein the control circuit is further configured to wipe the position list of the first subarray The data of unit, the erasing includes that the magnetic field of the state of the bit location of the first subarray from first state to the second state is auxiliary The change for helping so that all bit locations of the first subarray show to represent another the in logic one and logical zero Two-state.

4. the device according to any one of claim 1-3, wherein the electromagnet includes being arranged, to be adjacent to first sub The coil of array.

5. device according to claim 4, the first subarray of its bit cell is arranged in the planes, wherein first is sub Each ferromagnetic device of each bit location of array has ferromagnetic layer, and the ferromagnetic layer is sub with first in bit location The direction of magnetization in the plane of array, wherein the coil includes multiple circles, each of which circle is generally normal to the of bit location The plane of one subarray is being orientated, and wherein described electromagnet is positioned at and is in substantially parallel relationship to the plane and the first submatrix The side of the direction of magnetization of the ferromagnetic layer of the ferromagnetic device of the bit location of row boots up magnetic field.

6. device according to claim 4, the first subarray of its bit cell is arranged in the planes, wherein first is sub Each ferromagnetic device of each bit location of array has a ferromagnetic layer, and the ferromagnetic layer has and is generally normal to bit location The direction of magnetization of the plane of the first subarray, wherein the coil includes multiple circles, each of which circle is in substantially parallel relationship to bit location The first subarray plane being orientated, and wherein described electromagnet is positioned at and is generally normal to the plane and big Body boots up magnetic field parallel to the side of the direction of magnetization of the ferromagnetic layer of the ferromagnetic device of the bit location of the first subarray.

7. device according to claim 2, wherein the control circuit is further configured to：

Receive the write of the logical address for being associated with the first physical memory address in the first subarray of bit location Data；

Whether the bit location for determining the first physical memory address all changes over the second state so that the first physical storage ground All bit locations of location show to represent logic one and another second state in logical zero；And

If it is determined that the bit location of the first physical memory address all changes over the second state, then spin polarized current is guided to lead to The ferromagnetic device of bit location selected by the first of the first subarray is crossed with by by bit location selected by the first of physical memory address First state is returned to from the second state change write so that being changed back to each first selected bits unit of first state represent Enter one in the logic one and logical zero of data to write data into the first physical memory address first selected by In bit location, and maintain the first physical memory address second selected by the state of bit location dimension is caused in the second state Each the second selected bits unit held in the second state represents described another in the logic one and logical zero of write data It is individual.

8. device according to claim 7, wherein the control circuit is further configured to：

If it is determined that at least some in the bit location of the first physical memory address is changed to first state, it is determined that position list Whether the bit location of available second physical memory address of the first subarray of unit all changes over the second state so that second All bit locations of physical memory address show to represent logic one and another second state in logical zero；With And

If it is determined that the second state can all be changed over the bit location of the second physical memory address, then the first physical store is made The bit location of device address is invalid, and the second physical memory address is distributed in the logical storage address to write data, and guides Spin polarized current pass through the second physical memory address first selected by bit location ferromagnetic device with by by the second physics Bit location returns to first state so that being changed back to first state from the second state change selected by the first of storage address Each first selected bits unit represents one by write data write in the logic one and logical zero of write data To the second physical memory address first selected by bit location, and maintain the second selected bits of the second physical memory address The state of unit causes each the second selected bits unit being maintained in the second state to represent write in the second state In the logic one of data and logical zero it is described another.

9. device according to claim 8, wherein the control circuit is further configured to：

If it is determined that all bit locations that there is no wherein available physical memory address are changed to the bit location of the second state The first subarray available second physical memory address, then select available second subarray of bit location, its bit cell All bit locations of the second subarray show to represent another second state in logic one and logical zero；And

Distribute the 3rd physical memory address of the second subarray to the logical storage address of write data, and by by the Bit location selected by the first of three physical memory address returns to first state so that being changed back to first from the second state change Each first selected bits unit of state represent write data logic one and logical zero in it is one and by dimension The state for holding bit location selected by the second of the 3rd physical memory address is in the second state so that being maintained at the second state In each second selected bits unit represent write data logic one and logical zero in described another will write number According to being written in the bit location of the 3rd physical memory address.

10. device according to claim 9, wherein the control circuit is further configured to：

Will be stored in that all valid data in the first subarray are transferred to the second subarray of bit location and to wipe first sub The data of the bit location of array, the erasing includes the state of the bit location of the first subarray from first state to the second state The change of the magnetic field auxiliary so that all bit locations of the first subarray show to represent described in logic one and logical zero Another the second state.

A kind of 11. computing systems used for display, including：

Memorizer；

Processor, it is configured to write data in memory and from memory read data；And

Video Controller, it is display configured to the information represented by the data in memorizer；

Wherein memorizer includes magnetoresistive RAM（MRAM）, it includes：

The array of the MRAM bit locations of the first subarray with MRAM bit locations, each of which bit location includes thering is polarization Ferromagnetic device, the polarization in a first state for Parallel and antiparallel polarization in one and be in the second state flat Row and antiparallel polarization in another；

Control circuit, it is configured to the ferromagnetic device of the bit location for guiding spin polarized current to pass through the first subarray locating The state change of the bit location of the first subarray in first state is into the second state so that the bit location of the first subarray Ferromagnetic device has the polarization shown by the bit location in the second state；And

Electromagnet, it is located at neighbouring first subarray to guide magnetic field to pass through the ferromagnetic device of the bit location of the first subarray with auxiliary Help and change the state of the bit location of the first subarray of the array of the bit location of STT MRAM to the second state from first state.

12. systems according to claim 11, wherein the MRAM bit locations are spin transfer torques（STT）Random access memory Memorizer（RAM）Bit location, the control circuit is configured to guide bit location of the spin polarized current by the first subarray Ferromagnetic device with will be in first state in the first subarray bit location state change into the second state so that first The ferromagnetic device of the bit location of subarray has the polarization shown by the bit location in the second state；The control circuit The ferromagnetic device of bit location selected by be further configured to guide spin polarized current to pass through the first subarray first is with by by the Bit location returns to first state so that being changed back to the every of first state from the second state change selected by the first of one subarray One in the logic one and logical zero of one the first selected bits cell list registration evidence is writing data into the first subarray In those bit locations selected by first, and wherein described control circuit is further configured to maintain the second selected bits of the first subarray The state of unit causes to be maintained each second selected bits cell list registration evidence in the second state in the second state Logic one and logical zero in another.

13. systems according to claim 11, wherein the control circuit is further configured to wipe the position of the first subarray The data of unit, the erasing includes the magnetic field of the state of the bit location of the first subarray from first state to the second state The change of auxiliary so that all bit locations of the first subarray show to represent in logic one and logical zero it is described another Second state.

14. systems according to any one of claim 11-13, wherein the electromagnet includes being arranged being adjacent to first The coil of subarray.

15. systems according to claim 14, the first subarray of its bit cell is arranged in the planes, wherein first Each ferromagnetic device of each bit location of subarray has ferromagnetic layer, and the ferromagnetic layer has first in bit location The direction of magnetization in the plane of subarray, wherein the coil includes multiple circles, each of which circle is generally normal to bit location The plane of the first subarray is being orientated, and wherein described electromagnet is positioned at and is in substantially parallel relationship to the plane and first sub The side of the direction of magnetization of the ferromagnetic layer of the ferromagnetic device of the bit location of array boots up magnetic field.

16. systems according to claim 14, the first subarray of its bit cell is arranged in the planes, wherein first Each ferromagnetic device of each bit location of subarray has a ferromagnetic layer, and the ferromagnetic layer has and is generally normal to bit location The first subarray plane the direction of magnetization, wherein the coil includes multiple circles, each of which circle is in substantially parallel relationship to position list The plane of the first subarray of unit being orientated, and wherein described electromagnet be positioned at be generally normal to the plane and The side for being in substantially parallel relationship to the direction of magnetization of the ferromagnetic layer of the ferromagnetic device of the bit location of the first subarray boots up magnetic field.

17. systems according to any one of claim 12, wherein the control circuit is further configured to：

18. systems according to claim 17, wherein the control circuit is further configured to：

19. systems according to claim 18, wherein the control circuit is further configured to：

20. systems according to claim 19, wherein the control circuit is further configured to：

A kind of 21. operation magnetoresistive RAMs（MRAM）Method, including：

The state of the bit location of the first subarray of the array of the bit location of MRAM is auxiliary to the magnetic field of the second state from first state The change for helping so that the bit location of the altered state of the first subarray shows the second state, wherein first state is represented and patrolled Volume one and logical zero in one and the second state representation logic one and logical zero in another, each of which bit location Including the ferromagnetic device with polarization, the polarization is in a first state in Parallel and antiparallel polarization and the It is another in Parallel and antiparallel polarization in two-state, and the change of wherein magnetic field auxiliary includes guiding magnetic field by the The ferromagnetic device of the bit location of one subarray is aiding in the shape of the bit location of the first subarray of the array of the bit location of MRAM State changes to the second state from first state.

22. methods according to claim 21, wherein the MRAM is spin transfer torque（STT）MRAM and magnetic field is auxiliary Changing of helping also include guiding spin polarized current by the ferromagnetic device of the bit location of the first subarray with will be in the first shape The state change of the bit location of the first subarray in state is into the second state so that the ferromagnetic device of the bit location of the first subarray With the polarization shown by the bit location in the second state, methods described also includes：

23. methods according to any one of claim 21-22, wherein the introduction by magnetic field include using be arranged it is neighbouring Magnetic field is generated in the coil of the first subarray,

First subarray of its bit cell is arranged in the planes, wherein each of each bit location of the first subarray Ferromagnetic device has ferromagnetic layer, and the ferromagnetic layer has the direction of magnetization in the plane in the first subarray of bit location, its Described in coil include multiple circles, each of which circle be orientated to it is following in one：

The plane of the first subarray of bit location is generally normal to, wherein the introduction by magnetic field is included in is in substantially parallel relationship to described putting down The side of the direction of magnetization of the ferromagnetic layer of the ferromagnetic device of the bit location of face and the first subarray boots up magnetic field；

The plane of the first subarray of bit location is in substantially parallel relationship to, wherein the introduction by magnetic field is included in is generally normal to described putting down The side of the direction of magnetization of ferromagnetic layer of ferromagnetic device of face and the bit location for being in substantially parallel relationship to the first subarray boots up magnetic .

24. methods according to claim 22, also include：

If it is determined that the bit location of the first physical memory address all changes over the second state, then spin polarized current is guided to lead to The ferromagnetic device of bit location selected by the first of the first subarray is crossed with by by bit location selected by the first of physical memory address First state is returned to from the second state change write so that being changed back to each first selected bits unit of first state represent Enter one and by the first physical memory address of maintenance the second selected bits in the logic one and logical zero of data The state of unit causes to maintain each second selected bits unit in the second state to represent write number in the second state According to logic one and logical zero in described in another write data are written to into the bit location of the first physical memory address In；

If it is determined that the second state can all be changed over the bit location of the second physical memory address, then the first physical store is made The bit location of device address is invalid, and the second physical memory address is distributed in the logical storage address to write data, and passes through Bit location selected by the first of second physical memory address is returned to into first state from the second state change so that be changed back to Each first selected bits unit of first state represents one in the logic one and logical zero of write data, described to change Become the ferromagnetic device of bit location selected by include guiding spin polarized current to pass through the second physical memory address first, and lead to The state for crossing bit location selected by the second of the second physical memory address of maintenance is in the second state so that being maintained at second Each in state the second selected bits unit represents that described another in the logic one and logical zero of write data will be write Enter data be written to the second physical memory address first selected by bit location；

If it is determined that all bit locations that there is no wherein available physical memory address are changed to the bit location of the second state The first subarray available second physical memory address, then select available second subarray of bit location, its bit cell All bit locations of available second subarray show to represent logic one and another second state in logical zero； And

25. methods according to claim 24, methods described also includes：