CN106601877A - Manufacture method of LED chip of vertical structure - Google Patents
Manufacture method of LED chip of vertical structure Download PDFInfo
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- CN106601877A CN106601877A CN201610981926.2A CN201610981926A CN106601877A CN 106601877 A CN106601877 A CN 106601877A CN 201610981926 A CN201610981926 A CN 201610981926A CN 106601877 A CN106601877 A CN 106601877A
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- layer
- led chip
- ray structure
- metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
- H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
Abstract
Provided is a manufacture method of an LED chip of a vertical structure. Only two photoetching technologies are used to complete manufacture of the LED chip of the vertical structure, the manufacture technology of the LED chip of the vertical structure is simplified greatly, the manufacture difficulty and cost of the LED chip of the vertical structure are reduced effectively, and the LED chip of the vertical structure can be produced in a batch manner industrially.
Description
Technical field
The present invention relates to semiconductor photoelectric device and semiconductor lighting manufacture field, more particularly, to a kind of vertical stratification
The manufacture method of LED chip.
Background technology
LED（Light Emitting Diode, light emitting diode）It is the shape that releases energy when one kind utilizes Carrier recombination
Into luminous semiconductor device, LED chip has that power consumption is low, colourity is pure, life-span length, small volume, response time are fast, energy-conserving and environment-protective
Deng many advantages.In recent years, with deepening continuously for studying to LED chip, what the luminous efficiency of LED chip was obtained greatly carries
Height, has been widely used in the every field such as display at present.
Light emitting diode (LED) chip with vertical structure is compared with horizontal structure LED chip, with homogeneous current distribution, good heat dissipation, voltage it is low,
The advantages of efficiency high.Therefore, after light emitting diode (LED) chip with vertical structure is suggested, is widely paid close attention to rapidly, and achieved a series of
Progress.But, to compare with horizontal structure LED chip, the technique overall flow of thin-film LED is complex, photoetching process step
It is rapid many（Typically no less than 7 times, such as：Chip size defines photoetching, the illuminator photoetching of P faces, the channel protective layer photoetching of P faces, U-GaN
Etching protection photoetching, N electrode current barrier layer photoetching, N electrode photoetching, passivation protection layer photoetching）, technology controlling and process hardly possible, so as to shadow
Ring the yield and stability of light emitting diode (LED) chip with vertical structure, it is difficult to realize scale of mass production.
The content of the invention
In view of this, the invention provides a kind of manufacture method of light emitting diode (LED) chip with vertical structure, the manufacture method is only with 2
Secondary photoetching process, greatly reduces process complexity and cost, is conducive to light emitting diode (LED) chip with vertical structure to realize scale of mass production.
For achieving the above object, the technical scheme that the present invention is provided is as follows：
A kind of manufacture method of light emitting diode (LED) chip with vertical structure, including：
S1：First substrate is provided, and cushion, ray structure, diffusion impervious layer is sequentially formed on first substrate, wherein,
The ray structure includes n type gallium nitride layer, active layer, p-type gallium nitride layer, transparency conducting layer and the metallic reflection for sequentially forming
Layer；
S2：Seed Layer and metal substrate are sequentially formed on the diffusion impervious layer, and first substrate is luminous with described
Structure separates；
S3：The ray structure is performed etching, the first through hole through the ray structure is formed（First time photoetching）；
S4：Insulating barrier is formed on the ray structure surface and first through hole side wall；
S5：The insulating barrier is performed etching, second in the n type gallium nitride layer is formed through the insulating barrier and extend to
Through hole（Second photoetching）, and filler metal layer forms N-type electrode in second through hole.
Preferably, the material for forming the current extending is one or more in Ti, Pt, Au, W.
Preferably, the metal supporting layer is formed using electroplating technology.
Preferably, the material for forming the metal supporting layer is one or more in Ni, Cu, Au, Mo, Mn, Sn, and which is thick
About 40 μm ~ 500 μm of degree scope.
Preferably, the metal seed layer is formed using electron beam evaporation or magnetron sputtering technique.
Preferably, the material for forming the metal seed layer is the one kind or several in Pd, Pt, Au, W, Ni, Ta, Co, Ti
Kind, its thickness range is about 100nm ~ 500nm.
Preferably, the N-type electrode is described using electron beam evaporation plating, magnetron sputtering, plating or chemical plating process
Deposit what filler metal layer was formed in two through holes.
The manufacture method of a kind of light emitting diode (LED) chip with vertical structure provided relative to prior art, the present invention, only with 2 road light
Carving technology, you can complete the manufacture of light emitting diode (LED) chip with vertical structure, greatly simplifies the manufacturing process of light emitting diode (LED) chip with vertical structure, effectively drops
The manufacture difficulty and cost of low light emitting diode (LED) chip with vertical structure, enables light emitting diode (LED) chip with vertical structure to realize industrial volume production.
Description of the drawings
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
Accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1-5 is light emitting diode (LED) chip with vertical structure manufacturing process flow diagram provided in an embodiment of the present invention.
Specific embodiment
Embodiments of the present invention are illustrated below by way of particular specific embodiment, those skilled in the art can be by this explanation
Content disclosed by book understands other advantages and effect of the present invention easily.The present invention can also pass through in addition different concrete
Embodiment is carried out or applies, and the every details in this specification can also be based on different viewpoints and application, without the back of the body
Modifications and changes are carried out under the spirit of the present invention.
Refer to accompanying drawing.It should be noted that the diagram provided in the present embodiment only illustrates the present invention in a schematic way
Basic conception, only show in illustrating then with relevant component in the present invention rather than according to component count during actual enforcement, shape
Shape and size are drawn, and which is actual when the implementing form of each component, quantity and ratio can be a kind of random change, and its component cloth
Office's form is likely to increasingly complex.
A kind of manufacture method of light emitting diode (LED) chip with vertical structure, the method are comprised the following steps：
S1：First substrate is provided, and cushion, ray structure, diffusion impervious layer is sequentially formed on first substrate, wherein,
The ray structure includes n type gallium nitride layer, active layer, p-type gallium nitride layer, transparency conducting layer and the metallic reflection for sequentially forming
Layer；
S2：Seed Layer and metal substrate are sequentially formed on the diffusion impervious layer, and first substrate is luminous with described
Structure separates；
S3：The ray structure is performed etching, the first through hole through the ray structure is formed（First time photoetching）；
S4：Insulating barrier is formed on the ray structure surface and first through hole side wall；
S5：The insulating barrier is performed etching, second in the n type gallium nitride layer is formed through the insulating barrier and extend to
Through hole（Second photoetching）, and filler metal layer forms N-type electrode in second through hole.
Specifically, as shown in figure 1, the material of the first substrate 10 can be sapphire, carborundum or silicon, or other
Semi-conducting material, in the present embodiment, preferably the first substrate is Sapphire Substrate, forms cushion 11, then on the first substrate 10
11 surface of cushion formed ray structure 20, i.e., on the first substrate 10 successively grown buffer layer 11, n type gallium nitride layer 201,
Active layer 202, p-type gallium nitride layer 203, the technique for adopting for metal-organic chemical vapor deposition equipment, then in p-type gallium nitride layer
Transparency conducting layer 204 is formed on 203, then the first substrate is placed on the environment high temperature annealing 5min ~ 60min of nitrogen, with
The transparency conducting layer more dense uniform to be formed is made, ohm contact performance is better, the technique for then adopting is steamed for electron beam
Send out or magnetron sputtering method on transparency conducting layer 204 evaporation metal reflecting layer 205, the metallic reflector 205 by Al,
Ag, Pt, Au, Ti or its alloy are constituted, and the scope of its thickness is about 100nm ~ 500nm, and the first substrate is placed on inertia then
Short annealing is carried out in the environment of gas, so as to occur to spread between metal between metallic reflector, so as to strengthen metallic reflector
Structural strength.
After ray structure 20 completes, using electron beam evaporation process or magnetron sputtering technique in the ray structure
20 surfaces form diffusion impervious layer 30, and the diffusion impervious layer 30 is made up of Ti, Pt, Au, W or its alloy, to prevent metal anti-
The metal ion penetrated in layer spreads and forms leakage current, affects the performance of LED chip.
Specifically, as shown in Fig. 2 using electron beam evaporation or magnetron sputtering technique diffusion impervious layer 30 surface shape
Uniformly fine and close metal seed layer 40, and fully annealed, to ensure the good Ohmic contact of metal seed layer 40, make
Electric conductivity between the metal seed layer 40 of formation and the metal supporting layer 50 that is subsequently formed is more excellent, wherein, the metal kind
Sublayer 40 can by Pd, Pt, Au, W, Ni, Ta, Co, Ti in the alloy of one or more metal constitute, its thickness range is about
100nm~500nm。
After metal seed layer 40 completes, metal supporting layer is formed on the surface of metal seed layer 40 by electroplating technology
50, and the first substrate 10 and ray structure 20 are cut separation, form structure as shown in Figure 3.Wherein, the metal supporting layer
Alloys that 50 material can be constituted for one or more in Ni, Cu, Au, Mo, Co, its thickness range are about 40 μm ~ 500 μ
m。
When metal supporting layer 50 is electroplated, different structure, composition can be formed by adjusting rate of deposition and solution composition
With the metal supporting layer 50 of hardness, to eliminate due to ray structure 20 and diffusion impervious layer 30, metal seed layer 40 and gold
Between category supporting layer 50, the internal stress produced due to coefficient of expansion difference.After plating forms metal supporting layer 50, process annealing
10min ~ 100min, further eliminates the internal stress between dielectric layer, in reduction subsequent technique after the first substrate desquamation, due to interior
Stress and the metal level warpage that produces.
After forming metal supporting layer 50, the metal supporting layer 50 is ground and is polished, to adapt to subsequent technique
Need, then the first substrate 10 is peeled off using grinding, wet etching or KrF ultraviolet excimer laser, make described first
Substrate 10 is separated with cushion 11, then using inductively coupled plasma or wet corrosion technique to the cushion 11 after separation
Perform etching, remove the damage layer and non-conductive layer on 201 surface of n type gallium nitride layer, then using wet corrosion technique to N-type nitrogen
Changing gallium layer 201 carries out surface coarsening technique, to form coarse surface.The surface coarsening technique is using KOH, NaOH, Ba
(OH)2In one or more solution surface is corroded, and need the light radiation using wavelength between 200nm ~ 600um
Auxiliary corrosion.
Litho pattern is formed in 20 surface-coated positivity of ray structure or negative photoresist, using inductively coupled plasma
Etching technics, to ray structure 20, i.e. n type gallium nitride layer 201, active layer 202, p-type gallium nitride layer 203, transparency conducting layer
204th, metallic reflector 205 carries out dry or wet etch, as shown in figure 3, formed leading to through the first of the ray structure 20
Hole, the final position of etching is on the surface of diffusion impervious layer.
Specifically, as shown in figure 4, using plasma strengthens chemical vapor deposition method, on the surface of ray structure 20
And 501 side wall deposition insulating barrier 60 of first through hole, the insulating barrier 60 can be by silicon nitride, silicon oxide, silicon oxynitride
Plant or one or more layers deielectric-coating of several formation is constituted, protect the structure of chip, improve chip reliability.
Using inductively coupled plasma or BOE wet-etching technologies, the insulating barrier 60 is performed etching, formed through institute
State insulating barrier 60 and extend to the second through hole in n type gallium nitride layer 201, as shown in Figure 5.
After forming the second through hole, using one kind in electron beam evaporation plating, magnetron sputtering, plating or chemical plating process or several
Kind, in the first through hole, deposition film forms filler metal layer, forms then the N-type electricity electrically connected with n type gallium nitride layer
Pole 1.
Finally chip is cut using the method for tangent or backcut, the core particles of well cutting are carried out into the survey of photoelectric parameter
Examination and sorting, qualified core particles are carried out after the techniques such as follow-up encapsulation, form the LED chip or LED of finished product.
The manufacture method of a kind of light emitting diode (LED) chip with vertical structure that the present embodiment is provided, only with 2 road photoetching processes, you can complete
Into the manufacture of light emitting diode (LED) chip with vertical structure, the manufacturing process of light emitting diode (LED) chip with vertical structure is greatly simplified, effectively reduce vertical structure LED
The manufacture difficulty and cost of chip, enables light emitting diode (LED) chip with vertical structure to realize industrial volume production.
The foregoing description of the disclosed embodiments, enables professional and technical personnel in the field to realize or using the present invention.
Various modifications to these embodiments will be apparent for those skilled in the art, as defined herein
General Principle can be realized without departing from the spirit or scope of the present invention in other embodiments.Therefore, the present invention
The embodiments shown herein is not intended to be limited to, and is to fit to and principles disclosed herein and features of novelty phase one
The most wide scope for causing.
Claims (7)
1. a kind of manufacture method of light emitting diode (LED) chip with vertical structure, including：
First substrate is provided, and cushion, ray structure, diffusion impervious layer is sequentially formed on first substrate, wherein, it is described
Ray structure includes n type gallium nitride layer, active layer, p-type gallium nitride layer, transparency conducting layer and the metallic reflector for sequentially forming；
Sequentially form Seed Layer and metal substrate on the diffusion impervious layer, and by first substrate and the ray structure
Separate；
The ray structure is performed etching, the first through hole through the ray structure is formed（First time photoetching）；
Insulating barrier is formed on the ray structure surface and first through hole side wall；
The insulating barrier is performed etching, is formed through the insulating barrier and is extended in the n type gallium nitride layer second and lead to
Hole（Second photoetching）, and filler metal layer forms N-type electrode in second through hole.
2. LED chip according to claim 1, it is characterised in that the material for forming the current extending be Ti, Pt,
One or more in Au, W.
3. LED chip according to claim 1, it is characterised in that the metal supporting layer is formed using electroplating technology
's.
4. LED chip according to claim 3, it is characterised in that the material for forming the metal supporting layer be Ni, Cu,
One or more in Au, Mo, Mn, Sn, about 40 μm ~ 500 μm of its thickness range.
5. LED chip according to claim 1, it is characterised in that the metal seed layer be using electron beam evaporation or
What person's magnetron sputtering technique was formed.
6. LED chip according to claim 5, it is characterised in that the material for forming the metal seed layer be Pd, Pt,
One or more in Au, W, Ni, Ta, Co, Ti, its thickness range are about 100nm ~ 500nm.
7. LED chip according to claim 1, it is characterised in that the N-type electrode is using electron beam evaporation plating, magnetic control
Sputtering, plating or chemical plating process deposit the formation of filler metal layer in second through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201610981926.2A CN106601877A (en) | 2016-11-09 | 2016-11-09 | Manufacture method of LED chip of vertical structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610981926.2A CN106601877A (en) | 2016-11-09 | 2016-11-09 | Manufacture method of LED chip of vertical structure |
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| CN106601877A true CN106601877A (en) | 2017-04-26 |
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Citations (6)
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| CN101099223A (en) * | 2005-01-11 | 2008-01-02 | 美商旭明国际股份有限公司 | Light emitting diode with conducting metal substrate |
| US20080116472A1 (en) * | 2006-11-21 | 2008-05-22 | Sharp Kabushiki Kaisha | Semiconductor light emitting element and method of manufacturing the same |
| CN102637783A (en) * | 2011-02-15 | 2012-08-15 | 同方光电科技有限公司 | White-light emitting diode with vertical structure and manufacturing method thereof |
| CN204144301U (en) * | 2014-07-25 | 2015-02-04 | 北京中科天顺信息技术有限公司 | A kind of light emitting diode with vertical structure |
| CN104659177A (en) * | 2015-01-20 | 2015-05-27 | 湘能华磊光电股份有限公司 | Group III semiconductor luminescent device |
| CN105514230A (en) * | 2016-03-03 | 2016-04-20 | 映瑞光电科技(上海)有限公司 | GaN-base LED vertical chip structure and manufacture method thereof |
-
2016
- 2016-11-09 CN CN201610981926.2A patent/CN106601877A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101099223A (en) * | 2005-01-11 | 2008-01-02 | 美商旭明国际股份有限公司 | Light emitting diode with conducting metal substrate |
| US20080116472A1 (en) * | 2006-11-21 | 2008-05-22 | Sharp Kabushiki Kaisha | Semiconductor light emitting element and method of manufacturing the same |
| CN102637783A (en) * | 2011-02-15 | 2012-08-15 | 同方光电科技有限公司 | White-light emitting diode with vertical structure and manufacturing method thereof |
| CN204144301U (en) * | 2014-07-25 | 2015-02-04 | 北京中科天顺信息技术有限公司 | A kind of light emitting diode with vertical structure |
| CN104659177A (en) * | 2015-01-20 | 2015-05-27 | 湘能华磊光电股份有限公司 | Group III semiconductor luminescent device |
| CN105514230A (en) * | 2016-03-03 | 2016-04-20 | 映瑞光电科技(上海)有限公司 | GaN-base LED vertical chip structure and manufacture method thereof |
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Application publication date: 20170426 |