CN106601796A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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Publication number
CN106601796A
CN106601796A CN201510661016.1A CN201510661016A CN106601796A CN 106601796 A CN106601796 A CN 106601796A CN 201510661016 A CN201510661016 A CN 201510661016A CN 106601796 A CN106601796 A CN 106601796A
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China
Prior art keywords
fin
substrate
high mobility
barrier layer
sti
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Pending
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CN201510661016.1A
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Chinese (zh)
Inventor
秦长亮
殷华湘
赵超
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to CN201510661016.1A priority Critical patent/CN106601796A/en
Publication of CN106601796A publication Critical patent/CN106601796A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility

Abstract

The invention provides a semiconductor device manufacturing method, comprising the following steps: developing a plurality of fins on a substrate and STIs among the fins wherein each fin includes high mobility materials; and performing ion implantation to form a diffusion preventing layer in each fin so as to prevent the elements in the high mobility materials from diffusing towards the substrate. According to the semiconductor device manufacturing method of the present invention, ions are implanted into the high mobility fins to form a diffusion preventing layer so as to prevent the decrease in concentration of the elements in the high mobility materials in the channel region; and therefore, the stability of the device is increased at a low cost.

Description

Method, semi-conductor device manufacturing method
Technical field
The present invention relates to a kind of method, semi-conductor device manufacturing method, more particularly to a kind of to have little chi The FinFET manufacture methods of very little mobility channel.
Background technology
Move ahead to continue to press on Moore's Law, the driving current of device needs to get a greater increase And need to control short-channel effect.It is integrated with the body silicon fin gate fin-fet of mobility channel (finfet) device is considered as the device of the most potential development for promoting Moore's Law.
The manufacture method of mobility channel finfet devices usually grows high mobility on a silicon substrate Channel material.The raceway groove of high mobility is generally made up of high mobility material, such as germanium, germanium silicon, III-V Race's material, II-VI group material etc..By taking SiGe as an example, high mobility material is re-formed after the growth was completed The fin of composition.A kind of Integrated Solution is one layer of germanium of extension after conventional method forms silicon fin and STI Silicon is used as high mobility material.
But mobility channel device often is faced with a problem.High mobility material is being formed In the follow-up pyroprocess of the fin of composition, high mobility material will be to backing material (usually silicon) Middle diffusion.This will make the high mobility element in the fin channel regions that high mobility material is constituted dense Degree is reduced, so that the channel mobility that the mobility ratio of raceway groove is pre-designed is low, this will deteriorate device The performance of part.The mobility channel finfet of SOI substrate can avoid this problem, but face Substrate is relatively costly, and the problem that SOI substrate thermal diffusivity is poor.
The content of the invention
From the above mentioned, it is an object of the invention to overcome above-mentioned technical difficulty, propose that one kind can The FinFET manufacture methods of the small size mobility channel of Simplified flowsheet reduces cost.
For this purpose, the invention provides a kind of method, semi-conductor device manufacturing method, including：On substrate The STI between multiple fins and fin is formed, each fin includes high mobility material；Perform Ion implanting, forms barrier layer in each fin to prevent the element in high mobility material Spread to substrate.
Wherein, the step of STI between multiple fins and fin is formed on substrate is further wrapped Include：Etched substrate forms the groove between multiple fins and fin；STI is formed in the trench； Etching removes at least a portion of each fin, and multiple second grooves are left in STI；Many Epitaxial growth high mobility material in individual second groove.
Wherein, further include after the step of leaving multiple second grooves, be roughened each second The bottom of groove.
Wherein, the atomic number of ion is injected less than the unit that substrate is different from high mobility material Element.
Wherein, the ion of injection is selected from any one of C, N, O, F, S and combinations thereof.
Wherein, further include before or after forming barrier layer, perform the second ion note Enter, anti-break-through barrier layer is formed in each fin.
Wherein, the doped chemical on anti-break-through barrier layer according to device different type select three races or Group-v element and substrate itself or the simple substance elementary composition with other races or compound.
Wherein, high mobility material selected from II-VI group, the simple substance of iii-v or IV races or with this The compound that race or other races are formed.
Wherein, further include after forming barrier layer, be developed across on multiple fins Gate stack, form source-drain area in the fin of gate stack both sides.
According to the method, semi-conductor device manufacturing method of the present invention, ion is injected in high mobility fin Barrier layer is formed, high mobility concentration of element is reduced in preventing channel region, with low cost raising Device stability.
Description of the drawings
Referring to the drawings describing technical scheme in detail, wherein：
Fig. 1 to Fig. 2 is the sectional view of each step of FinFET manufacture methods according to the present invention；And
Fig. 3 is the indicative flowchart of the FinFET manufacture method according to the present invention.
Specific embodiment
The technology of the present invention side is described in detail referring to the drawings and with reference to schematic embodiment The feature and its technique effect of case, discloses small size Gao Qian for being capable of Simplified flowsheet reduces cost The FinFET manufacture methods of shifting rate raceway groove.It is pointed out that similar reference represents class As structure, term " first " use herein, " second ", " on ", D score Etc. can be used to modify various device architectures or manufacturing process.These modifications are unless stated otherwise simultaneously Non- space, order or the hierarchical relationship for implying institute's modification device architecture or manufacturing process.
As shown in Fig. 3 and Fig. 1, multiple high mobility fins are formed.
Substrate 1 is provided, its material can be monocrystal silicon, SOI, monocrystalline germanium, GeOI, strain Silicon (Strained Si), germanium silicon (SiGe), or compound semiconductor materials, such as nitrogen Change gallium (GaN), GaAs (GaAs), indium phosphide (InP), indium antimonide (InSb), And carbon-based semiconductors such as Graphene, SiC, carbon nanotube etc..It is preferred in the present invention one In embodiment, substrate 1 be monocrystal silicon, in order to it is compatible with CMOS technology and reduce make Cause this.
Using mask graph (it is not shown, can be photoresist soft mask or dielectric material it is hard Mask) etched substrate 1, the multiple fin structure 1F for extending in a first direction are defined, and Groove (not shown) between adjacent fin structure.Etching technics preferably anisotropic dry method Etching, such as dry plasma etch or RIE, etching gas such as carbon fluorine base gas is (at least Containing carbon, fluorine atom, can also also have other atoms such as hydrogen, nitrogen, oxygen), chlorine, bromine steam Vapour, HCl, HBr etc., can also add the oxidants such as oxygen, CO, ozone to adjust etching Speed.
In groove between fin structure 1F, fill insulant forms shallow trench isolation (STI) 2, completely fills the groove between fin 1F.For example pass through thermal oxide, LPCVD, PECVD Etc. technique, the STI 2 of insulant in the groove between fin structure 1F, is defined.At this In one preferred embodiment of invention, 2 materials of STI are silicon oxide or nitrogenize silicon substrate matter, for example SiOx、SiNx、SiOxNy、SiOxCy、SiOxFy、SiOxHy、SiNxCy、SiNxFyIt is (each Individual xy is not necessarily integer).The part 1C for exposing the fin 1F at the top of STI 2 will be used Make the source-drain area and channel region of FinFET.In another preferred embodiment of the present invention, STI 2 Material be low-k materials to reduce the parasitic capacitance of device, formation process be spin coating, spraying, Silk screen printing, wherein low-k materials include but is not limited to organic low-k materials (such as containing aryl or The organic polymer of many yuan of rings of person), inorganic low-k material (such as amorphous carbon nitrogen film, many Brilliant boron nitrogen film, fluorine silica glass, BSG, PSG, BPSG), porous low k material (example As two silicon, three oxygen alkane (SSQ) Quito hole low-k materials, porous silica, porous SiOCH, Mix C silicon dioxide, mix F porous amorphous carbon, porous diamond, porous organic polymer). In another preferred embodiment of the present invention, the material of STI2 also include negative expansion dielectric material or Positive thermal expansion dielectric material (preferably, the linear coefficient of cubical expansion at a temperature of 100K Absolute value is more than 10-4/ K) sublayer, to further enhance channel region stress, negative expansion is situated between Material is to include selected from Bi0.95La0.05NiO3、BiNiO3、ZrW2O8Any one and its The perofskite type oxide of combination, positive thermal expansion dielectric material is to include Ag3[Co(CN)6] frame Frame material.
Afterwards, selective etch eliminates at least a portion (such as top) of fin 1F, Fin 1F remainders (bottom shown in Fig. 1) and remainder are left in STI 2 Multiple groove (not shown) of top.Preferably, using anisotropic etching method, for The material of fin 1F is performed etching, and is directed to Si materials for example with TMAH, KOH.It is excellent Selection of land, is processed to extra micro etch or roughening process are carried out at the top of fin 1F remainders, So that top have it is certain towards the raised or sunken (thick of, certain size (width, spacing) Change structure) with the film quality that improves subsequently epitaxial growing, (such as 0.5～1nm's or so is recessed Male structure using cause epitaxial material by the use of it is concavo-convex accelerate as nucleating layer between crystal grain melt Close).
Then, using techniques such as HDPCVD, MOCVD, MBE, ALD, in multiple ditches In groove, (carrier mobility of material is more than substrate to epitaxial growth high mobility material, for example greatly In the carrier mobility of backing material Si) channel layer 1C is formed, until cover STI 2 pushing up Portion.Simple substance of the high mobility material of channel layer 1C selected from II-VI group, iii-v or IV races Or the compound formed with this race or other races, for example IV races simple substance, IV compounds of group, III-V, II-VI group compound, such as SiGe, SiC, SiGeC, SiGeSn, SiGaN、SiGaP、SiGaAs、InSiN、InSiP、InSiAs、InSiSb、GaN、 InSb, InP, InAs, GaAs, SiInGaAs any one and combinations thereof high mobility material Material or their component proportion material.In a preferred embodiment of the invention, channel layer 1C Material is SiGe.Subsequently preferably, using cmp planarization high mobility material layer until dew Go out at the top of STI 2.
Subsequently, quarter (etch-back) STI 2 is returned until being completely exposed the ditch of high mobility material Channel layer 1C.It can be wet etching to return quarter, for example, corrode for the HF of silicon oxide, or be directed to The hot phosphoric acid corrosion of silicon nitride.Return quarter can also be dry etching, for example with the fluorine-based etching of carbon Gas (adjustment fluorohydrocarbon CxHyFzMiddle xyz proportionings cause to improve for the etching of some materials Speed) plasma dry etch or reactive ion etching.Preferably, return and stop at lining quarter At the top of the fin remainder 1F of 1 material of bottom, such as in fin 1F and mobility channel layer The interface of 1C.
Then, as shown in Fig. 3 and Fig. 2, ion implanting is performed, in the fin of high mobility material Barrier layer 3, namely (such as STI 2 below channel region 1C are formed in piece channel layer 1C Near top, fin remainder 1F and channel region 1C interfaces or lower section).Injection energy Amount such as 500eV～3KeV preferably 1KeV～2.5KeV, implantation dosage such as 1019～5 × 1021Atom/cm3, the channel layer 1C of the element atomic number of injection less than high mobility material In non-Si elements, namely will subsequently spread element (the present invention one be preferable to carry out It is Ge in example).Injection ion is for example preferably chosen from any one of C, N, O, F, S And combinations thereof, and most preferably C (C and Si, Ge are all IV races element, atomic structure class Seemingly, barrier layer can be regarded as the network structure that Si and C forms, if Ge etc. will be prevented High mobility material spreads or migrates, and selects the less purpose of atomic number to be exactly in order that net Eye size reduces, and so can effectively prevent the material transition of larger atomic number).Ion is noted It can be that vertical injection, or inclination are injected (towards channel region 1C) to enter, and incline note The angle for entering is, for example, 5～15 degree.Annealing, the impurity of the injection for making can be performed after injection Activate and redistribute, precise control causes the peak concentration of barrier layer 3 at the top of STI 2 Place or nearby (namely in the lower section of fin 1F top channels area 1C, for example with STI 2 at the top of Flush or lower slightly 1～3nm).Such as 550～1050 DEG C of annealing temperature, preferably 650～ 900 DEG C, optimal 700～800 DEG C, annealing time 1s～10min, 10s～5min, 1～ 3min。
Optionally or preferably, before or after performing ion implanting formation barrier layer, hold The other ion implanting of row forms anti-break-through barrier layer (not shown) in fin 1F, so as to Improve and be dielectrically separated from effect between substrate and raceway groove, eliminate or reduce substrate leakage electricity Stream.The injection doped chemical on anti-break-through barrier layer selects III or V according to device different type Race's element, can with substrate itself element (such as Si) or with the elementary composition simple substance of other races Or compound.In an embodiment of the invention, the doped chemical on anti-break-through barrier layer for NMOS includes B, BF2, Al, Ga, In, for pMOS includes P, As, Sb. In other embodiments of the invention, the injection doped chemical on anti-break-through barrier layer is O, N, so as to The insulation to form silicon oxide, silicon oxynitride, silicon nitride is reacted with the Si in 1/ fin 1F of substrate Material is further enhancing the anti-punch through effect of substrate.It should be noted that anti-break-through barrier layer should Positioned at the lower section of barrier layer 3 guaranteeing effectively to reduce substrate leakage.
Hereafter, can with formation of deposits across channel region 1C gate stack, in gate stack both sides Fin in form source-drain area, form the interlayer dielectric layer (ILD) for covering whole chip, carve Erosion ILD forms contact hole and filler metal realizes that source and drain is interconnected, and is finally completed FinFET system Make.
In said method, compared to conventional body silicon mobility channel finfet, PTSL is being carried out Step carbon injection is carried out during injection just can be with solve problem more.The device made using the program The problem to substrate diffusion of channel material preferably will be suppressed.So as to keep high mobility Characteristic, improves the performance of device.Additionally, compared to SOI device, it is not necessary to expensive SOI Substrate, while there is no radiating sex chromosome mosaicism.
According to the method, semi-conductor device manufacturing method of the present invention, ion is injected in high mobility fin Barrier layer is formed, high mobility concentration of element is reduced in preventing channel region, with low cost raising Device stability.
Although with reference to one or more exemplary embodiments explanation present invention, people in the art Member could be aware that and various suitable changes are made without departing from the scope of the invention and to device architecture And equivalents.Additionally, by disclosed teaching can make many can be adapted to particular condition or The modification of material is without deviating from the scope of the invention.Therefore, the purpose of the present invention does not lie in and is limited to It is as realizing the preferred forms of the present invention and disclosed specific embodiment, and disclosed Device architecture and its manufacture method will include all embodiments for falling within the scope of the present invention.

Claims (9)

1. a kind of method, semi-conductor device manufacturing method, including：
The STI between multiple fins and fin is formed on substrate, each fin includes high migration Rate material；
Ion implanting is performed, barrier layer is formed in each fin to prevent high mobility material In element to substrate spread.
2. method as claimed in claim 1, wherein, formed on substrate between multiple fins and fin STI the step of further include：
Etched substrate forms the groove between multiple fins and fin；
STI is formed in the trench；
Etching removes at least a portion of each fin, and multiple second grooves are left in STI；
The epitaxial growth high mobility material in multiple second grooves.
3. method as claimed in claim 1, wherein, laggard a step of leave multiple second grooves Step includes, is roughened the bottom of each second groove.
4. method as claimed in claim 1, wherein, the atomic number for injecting ion is less than high mobility The element of substrate is different from material.
5. method as claimed in claim 4, wherein, the ion of injection is selected from C, N, O, F, S Any one and combinations thereof.
6. method as claimed in claim 1, wherein, formed before or after barrier layer further Including the second ion implanting of execution forms anti-break-through barrier layer in each fin.
7. method as claimed in claim 6, wherein, the doped chemical on anti-break-through barrier layer is according to device Different type select three races or group-v element and substrate itself or with other race's element groups Into simple substance or compound.
8. method as claimed in claim 1, wherein, high mobility material is selected from II--VI races, III--V races Or the simple substance or the compound formed with this race or other races of IV races.
9. method as claimed in claim 1, wherein, further include after forming barrier layer, shape Into across the gate stack on multiple fins, formed in the fin of gate stack both sides Source-drain area.
CN201510661016.1A 2015-10-14 2015-10-14 Semiconductor device manufacturing method Pending CN106601796A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103311296A (en) * 2012-03-08 2013-09-18 台湾积体电路制造股份有限公司 Semiconductor structure and method with high mobility and high energy bandgap materials
CN103531477A (en) * 2012-07-05 2014-01-22 台湾积体电路制造股份有限公司 FinFET method and structure with embedded underlying anti-punch through layer
US20150255456A1 (en) * 2014-03-04 2015-09-10 Globalfoundries Inc. Replacement fin insolation in a semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103311296A (en) * 2012-03-08 2013-09-18 台湾积体电路制造股份有限公司 Semiconductor structure and method with high mobility and high energy bandgap materials
US20150123144A1 (en) * 2012-03-08 2015-05-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Structures and Methods with High Mobility and High Energy Bandgap Materials
CN103531477A (en) * 2012-07-05 2014-01-22 台湾积体电路制造股份有限公司 FinFET method and structure with embedded underlying anti-punch through layer
US20150255456A1 (en) * 2014-03-04 2015-09-10 Globalfoundries Inc. Replacement fin insolation in a semiconductor device

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Application publication date: 20170426