CN106601603B - A kind of autoregistration injection manufacturing method of cmos image sensor - Google Patents
A kind of autoregistration injection manufacturing method of cmos image sensor Download PDFInfo
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- 239000007924 injection Substances 0.000 title claims abstract description 128
- 238000002347 injection Methods 0.000 title claims abstract description 128
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000010410 layer Substances 0.000 claims abstract description 84
- 239000012535 impurity Substances 0.000 claims abstract description 62
- 230000005540 biological transmission Effects 0.000 claims abstract description 56
- 239000011241 protective layer Substances 0.000 claims abstract description 27
- 230000000873 masking effect Effects 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 39
- 239000000463 material Substances 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 238000002955 isolation Methods 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 230000002411 adverse Effects 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 3
- 238000000151 deposition Methods 0.000 abstract 1
- 238000001259 photo etching Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000005036 potential barrier Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- BKLWQDSDJBFRDF-ZPUQHVIOSA-N (2e,4e)-5-(4-nitrophenyl)penta-2,4-dienal Chemical compound [O-][N+](=O)C1=CC=C(\C=C\C=C\C=O)C=C1 BKLWQDSDJBFRDF-ZPUQHVIOSA-N 0.000 description 1
- 101001024685 Pandinus imperator Pandinin-2 Proteins 0.000 description 1
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- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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Abstract
The invention discloses a kind of autoregistrations of cmos image sensor to inject manufacturing method; other regions other than transmission transistor and photosensitive area PN junction are protected using injection protective layer; and it is deposited with the first sacrificial layer on injection protective layer, to complete the p type impurity injection of transmission transistor after graphical first sacrificial layer forms injection window；Then by depositing the second sacrificial layer and planarizing, remove the first sacrificial layer that photosensitive area exposes, using the second sacrificial layer as the masking layer in transmission transistor p type impurity area, this completes pattern transfer and realize height alignment, when so that the subsequent N-type for carrying out photosensitive area PN junction again and p-type being injected, the problem of p type impurity area of transmission transistor overlaps or separates with the N-type of photosensitive area PN junction and p-type injection region would not occur, to reduce dark current and half-light response by misalignment bring adverse effect.
Description
Technical field
The present invention relates to IC manufacturing processing technique fields, are carrying out cmos image biography more particularly, to one kind
Manufacturing method is injected in autoregistration when the injection of sensor photosensitive area N-type impurity and the injection of transmission transistor p type impurity.
Background technique
Cmos image sensor is widely used in monitoring, equal fields of taking pictures.The most basic element of cmos image sensor is
One PN junction light sensitive diode and coupled transmission transistor.The electrical requirement of transmission transistor is cannot be photosensitive with PN junction
Otherwise the N-type impurity area break-through in area, including break-through under surface punchthrough and surface will affect dark current and the open ended electronics of PN junction
Number.The electrical requirement of PN junction photosensitive area is that cannot have potential barrier appearance on electron channel, otherwise will affect device dark photoresponse.
Referring to Fig. 1, Fig. 1 is a kind of cross-sectional view of the structure of cmos image sensor.As shown in Figure 1, perpendicular forming diagram
When straight left side of dotted line transmission transistor p-type injection region, three steps are commonly divided into, are from top to bottom respectively threshold value electricity in the substrate
Pressure adjusts injection, anti-break-through injection, trap injection.Illustrate the N-type impurity injection region of photosensitive area in vertical right side of dotted line substrate
(NPPD) electron number after resetting is provided；First p type impurity injection region (PPin) and deep p-well (Deep p well) are for vising
Current potential after sensor devices resetting；Second p type impurity injection region (PPin2) is the generation for preventing photosensitive area surface dark current
And injection formation is carried out, dosage is bigger than injection when forming the first p type impurity injection region.The dotted line of right-to-left in figure
Channel when arrow is resetting or electronics export, LTR are the injection photoetching window of transmission transistor, and LNPPD is the note of photosensitive area
Enter photoetching window.
When carrying out above-mentioned injection, traditional way is that the p-type injection of transmission transistor is respectively formed by Twi-lithography
The N-type impurity injection region and the first p type impurity injection region in area and photosensitive area.Due to the precision problem of photoetching, the P of transmission transistor
Type impurity injection region and the N-type impurity injection region of photosensitive area PN junction may overlap phenomenon, it is also possible to which generation is mutually covered
Lid less than, generate gap the phenomenon that.Following ask will be present since Twi-lithography can not be accurately aimed at, thus using traditional method
Topic:
1) the injection photoetching window LTR of such as transmission transistor covers the injection photoetching window LNPPD of photosensitive area, will cause
The N-type impurity injection region for covering PN junction is crossed in the p type impurity injection region of transmission transistor, leads to later photosensitive area polysilicon gate
Under N-type impurity concentration be lower, and the electron channel between grid silicon oxide layer and N-type impurity injection region is caused potential barrier occur；This
It will affect the half-light response of device.
2) the injection photoetching window LNPPD of such as photosensitive area covers the injection photoetching window LTR of transmission transistor, will cause
The p type impurity injection region for covering transmission transistor is crossed in the N-type impurity injection region of photosensitive area PN junction, leads to later transmission crystal
P type impurity concentration under pipe polysilicon gate is lower, and such transmission transistor may be threaded through, and the charge of photosensitive area PN junction is caused to hold
Amount reduces；This will affect device dark current and open ended electron number, also have residual electron after a small amount of resetting, lead to dark electricity
Stream increases.
3) as having gap between the injection photoetching window LNPPD of photosensitive area and the injection photoetching window LTR of transmission transistor,
The p type impurity injection region of the N-type impurity injection region and transmission transistor of causing photosensitive area PN junction is had to the area not covered mutually
Domain, and make there is one gently to mix p type island region appearance under grid oxygen, cause the electron channel under grid oxygen potential barrier occur；This equally will affect
The half-light of device responds.
Therefore, the p type impurity injection region of the N-type impurity injection region and transmission transistor of realization photosensitive area PN junction is accurate right
Standard, it is very important.
Summary of the invention
It is an object of the invention to overcome drawbacks described above of the existing technology, provide a kind of cmos image sensor from
Alignment injection manufacturing method.
To achieve the above object, technical scheme is as follows:
A kind of autoregistration injection manufacturing method of cmos image sensor, comprising the following steps:
Step S01: providing a substrate, forms shallow trench isolation and deep p-well in the substrate；
Step S02: sequentially forming injection protective layer, the first sacrificial layer in the substrate surface, and then graphical described the
One sacrificial layer forms the injection window of transmission transistor；
Step S03: by the injection window of the transmission transistor, p type impurity injection is carried out in Xiang Suoshu substrate；
Step S04: the second sacrificial layer is deposited in above-mentioned device surface, and is planarized, first sacrificial layer is exposed
Surface；
Step S05: then removal first sacrificial layer is infused by transmission transistor p type impurity of second sacrificial layer
Enter the masking layer in area, the N-type impurity injection and the injection of the first p type impurity of photosensitive area PN junction is carried out in Xiang Suoshu substrate, described
The N trap and p-well of device are formed in substrate；
Step S06: removal second sacrificial layer and injection protective layer.
Preferably, further includes: in step S02, be initially formed 3rd sacrifice layer in the substrate surface, re-form injection protection
Layer；In step S06, second sacrificial layer, injection protective layer and 3rd sacrifice layer are successively removed.
Preferably, it includes the trap carried out by several times from bottom to top that p type impurity injection is carried out in step S03, in Xiang Suoshu substrate
Injection, anti-break-through injection and threshold voltage adjustments injection.
Preferably, further include step S07: forming gate oxide in the substrate surface, and on the gate oxide
Form the grid of the transmission transistor.
Preferably, further include step S08: the source and drain for carrying out transmission transistor in the substrate gently mixes injection, forms grid
Pole side wall, and carry out the source and drain injection of transmission transistor.
It preferably, further include after forming grid curb wall, in the first p type impurity injection region of photosensitive area PN junction in step S08
The second p type impurity injection of middle progress.
Preferably, the thickness of the injection protective layer is not more than 20 nanometers.
Preferably, first sacrificial layer with a thickness of 100-500 nanometers.
Preferably, the material of the injection protective layer is silicon nitride, and the material of first sacrificial layer is silica.
Preferably, the 3rd sacrifice layer is identical as the material of the gate oxide and thickness, second sacrificial layer with
The material and thickness of the transfer transistor gate are identical.
It can be seen from the above technical proposal that the present invention using injection protective layer to transmission transistor and photosensitive area PN junction with
Other outer regions are protected, and since the injection of transmission transistor p type impurity is deeper, are also deposited with first on injection protective layer
Sacrificial layer, to complete the p type impurity injection of transmission transistor after graphical first sacrificial layer；Then pass through deposit second
Sacrificial layer simultaneously planarizes, the first sacrificial layer that removal photosensitive area exposes, using the second sacrificial layer as transmission transistor p type impurity area
Masking layer, this completes pattern transfer and realize height alignment so that the subsequent N-type for carrying out photosensitive area PN junction again and
When p-type is injected, would not occur the p type impurity area of transmission transistor and the N-type of photosensitive area PN junction and p-type injection region overlap or
The problem of separation, to reduce dark current and half-light response by misalignment bring adverse effect.
Detailed description of the invention
Fig. 1 is a kind of cross-sectional view of the structure of cmos image sensor；
Fig. 2 is a kind of autoregistration injection manufacturing method flow chart of cmos image sensor of the invention；
Fig. 3-Fig. 8 is the autoregistration of the method progress cmos image sensor in a preferred embodiment of the present invention according to fig. 2
The process sequence diagram of injection.
Specific embodiment
With reference to the accompanying drawing, specific embodiments of the present invention will be described in further detail.
It should be noted that in following specific embodiments, when describing embodiments of the invention in detail, in order to clear
Ground indicates structure of the invention in order to illustrate, spy does not draw to the structure in attached drawing according to general proportion, and has carried out part
Amplification, deformation and simplified processing, therefore, should be avoided in this, as limitation of the invention to understand.
In specific embodiment of the invention below, referring to Fig. 2, Fig. 2 is a kind of cmos image sensing of the invention
Manufacturing method flow chart is injected in the autoregistration of device.As shown in Fig. 2, a kind of autoregistration of cmos image sensor of the invention is injected
Manufacturing method, comprising the following steps:
Step S01: providing a substrate, forms shallow trench isolation and deep p-well in the substrate.
Please refer to Fig. 3.Conventional bulk silicon substrate 10 can be used, stand CMOS shape is used in the substrate 10
Deep p-well 11 is formed at shallow trench isolation (figure omits) and injection.
Step S02: sequentially forming injection protective layer, the first sacrificial layer in the substrate surface, and then graphical described the
One sacrificial layer forms the injection window of transmission transistor.
Please refer to Fig. 3.Then, formation injection protective layer 16, the first sacrificial layer 18 are successively deposited on 10 surface of substrate；
Wherein, the thickness of the injection protective layer is desirably no more than 20 nanometers, and the material of the injection protective layer can be silicon nitride etc.；By
It is deeper in the p type impurity injection of transmission transistor, therefore also need first of one layer thicker of the deposit on injection protective layer to sacrifice
Layer, therefore, the thickness of first sacrificial layer can be 100-500 nanometers, close with the gate of transmission transistor；Described
The material of one sacrificial layer can be silica etc..First step process layer of first sacrificial layer as pattern transfer of the present invention.
It can be initially formed a 3rd sacrifice layer 15 on 10 surface of substrate, as temporarily replacing for subsequent device gate oxide
Generation；Therefore, material identical with the gate oxide and thickness can be used in the 3rd sacrifice layer.Then, injection is re-formed to protect
Sheath.
Then, photoresist layer 17 can be re-formed on the first sacrificial layer；It then, can be graphical by photoetching, etching technics
First sacrificial layer 18 forms the injection window (diagram left side barbed portion) of transmission transistor, injects the sense other than window
Light area is still covered by the first sacrificial layer.Etching stopping is in injection protective layer 16.
Step S03: by the injection window of the transmission transistor, p type impurity injection is carried out in Xiang Suoshu substrate.
Please continue to refer to Fig. 3.Then, by being formed by injection window, progress p type impurity injection in Xiang Suoshu substrate,
It may include the trap injection of the different injection depth and condition that carry out by several times from bottom to top, anti-break-through injection and threshold voltage tune
Section injection, to be respectively formed trap injection region 12, anti-break-through injection region 13 and threshold voltage adjustments injection region 14.
Step S04: the second sacrificial layer is deposited in above-mentioned device surface, and is planarized, first sacrificial layer is exposed
Surface.
Please refer to Fig. 4.Then, remaining photoresist is removed, then, deposits to form the second sacrificial layer 19 in device surface,
It will injection protective layer 16 and the covering of 18 surface of the first sacrificial layer；Then, cmp planarization can be carried out to the second sacrificial layer 19, with dew
First sacrificial layer, 18 surface out.Material identical with subsequent transmission transistor gate and thickness can be used in second sacrificial layer
Degree, such as polysilicon can be used and form the second sacrificial layer.
Step S05: then removal first sacrificial layer is infused by transmission transistor p type impurity of second sacrificial layer
Enter the masking layer in area, the N-type impurity injection and the injection of the first p type impurity of photosensitive area PN junction is carried out in Xiang Suoshu substrate, described
The N trap and p-well of device are formed in substrate.
Please refer to Fig. 5.Then, the first sacrificial layer of silica 18 that photosensitive area exposes can be removed by wet processing, and stopped
Only in injection protective layer 16.
Please refer to Fig. 6.Then, so that it may which second sacrificial layer 19 is the masking of transmission transistor p type impurity injection region
Layer, protects it, and the N-type impurity injection and the injection of the first p type impurity of photosensitive area PN junction, shape are carried out into the substrate
At N-type impurity injection region 21 and the first p type impurity injection region 20.This completes pattern transfer and height alignment is realized,
When so that carrying out the N-type and p-type injection of photosensitive area PN junction again, p type impurity area 12-14 and the sense of transmission transistor would not occur
The problem of N-type of light area PN junction and p-type injection region 21,20 overlap or separate, to reduce dark current, avoids device
Half-light response is affected.
At this point, just foring the N trap and p-well of device in the substrate.
Step S06: removal second sacrificial layer and injection protective layer.
Please refer to Fig. 7.Then, common process can be used, successively remove remaining second sacrificial layer 19, removal injection
Protective layer 16, and removal 3rd sacrifice layer 15.
The present invention can also further perform the step of:
Step S07: forming gate oxide in the substrate surface, and the transmission crystalline substance is formed on the gate oxide
The grid of body pipe.
Please continue to refer to Fig. 7.Then, 10 surface deposition of the substrate after removing 3rd sacrifice layer 15 or growth shape
At real component grid oxidizing layer 22.
Please refer to Fig. 8.Then, the grid 25 of the transmission transistor is formed on the gate oxide 22, such as is formed
Polysilicon gate.
Step S08: the source and drain for carrying out transmission transistor in the substrate gently mixes injection, forms grid curb wall, Yi Jijin
The source and drain of row transmission transistor is injected.
Please continue to refer to Fig. 8.Then, CMOS common process can be used, transmission transistor is carried out in the substrate 10
Source and drain gently mixes injection 24 (LDD)；Then, can continue to form grid curb wall 26 in 25 side of polysilicon gate；And it is then passed
The source and drain of defeated transistor injects 23 (NSD), and carries out in the first p type impurity injection region 20 (P Pin) of photosensitive area PN junction
The injection of second p type impurity, forms the second p type impurity injection region 27 (P Pin2).
In conclusion the present invention using injection protective layer to other regions other than transmission transistor and photosensitive area PN junction into
Row protection is also deposited with the first sacrificial layer on injection protective layer, to scheme since the injection of transmission transistor p type impurity is deeper
The p type impurity injection of transmission transistor is completed after first sacrificial layer described in shape；Then pass through deposit the second sacrificial layer and flat
Change, the first sacrificial layer that removal photosensitive area exposes, using the second sacrificial layer as the masking layer in transmission transistor p type impurity area, this
Sample just completes pattern transfer and realizes height alignment, when so that the subsequent N-type for carrying out photosensitive area PN junction again and p-type being injected,
It is asked with what the N-type of photosensitive area PN junction and p-type injection region were overlapped or separated in the p type impurity area that transmission transistor would not occur
Topic, to reduce dark current and half-light response by misalignment bring adverse effect.
Above-described to be merely a preferred embodiment of the present invention, the patent that the embodiment is not intended to limit the invention is protected
Range is protected, therefore all with the variation of equivalent structure made by specification and accompanying drawing content of the invention, similarly should be included in
In protection scope of the present invention.
Claims (10)
1. manufacturing method is injected in a kind of autoregistration of cmos image sensor, which comprises the following steps:
Step S01: providing a substrate, forms shallow trench isolation and deep p-well in the substrate；
Step S02: injection protective layer, the first sacrificial layer are sequentially formed in the substrate surface, then graphical described first is sacrificial
Domestic animal layer, forms the injection window of transmission transistor；
Step S03: by the injection window of the transmission transistor, p type impurity injection is carried out in Xiang Suoshu substrate；
Step S04: in the second sacrificial layer of surface deposition, and being planarized, and first sacrificial layer surface is exposed；
Step S05: removal first sacrificial layer, then using second sacrificial layer as transmission transistor p type impurity injection region
Masking layer, the N-type impurity injection and the injection of the first p type impurity of photosensitive area PN junction are carried out in Xiang Suoshu substrate, in the substrate
The middle N trap and p-well for forming device；
Step S06: removal second sacrificial layer and injection protective layer.
2. manufacturing method is injected in the autoregistration of cmos image sensor according to claim 1, which is characterized in that also wrap
It includes: in step S02, being initially formed 3rd sacrifice layer in the substrate surface, re-form injection protective layer；In step S06, successively go
Except second sacrificial layer, injection protective layer and 3rd sacrifice layer.
3. manufacturing method is injected in the autoregistration of cmos image sensor according to claim 1, which is characterized in that step
It carrying out p type impurity in S03, in Xiang Suoshu substrate to inject including the trap injection carried out by several times from bottom to top, anti-break-through is injected, and
Threshold voltage adjustments injection.
4. manufacturing method is injected in the autoregistration of cmos image sensor according to claim 2, which is characterized in that further include
Step S07: gate oxide is formed in the substrate surface, and forms the grid of the transmission transistor on the gate oxide
Pole.
5. manufacturing method is injected in the autoregistration of cmos image sensor according to claim 4, which is characterized in that further include
Step S08: the source and drain for carrying out transmission transistor in the substrate gently mixes injection, forms grid curb wall, and carries out transmission crystalline substance
The source and drain of body pipe is injected.
6. manufacturing method is injected in the autoregistration of cmos image sensor according to claim 5, which is characterized in that step
It further include carrying out the second p type impurity note in the first p type impurity injection region of photosensitive area PN junction after forming grid curb wall in S08
Enter.
7. manufacturing method is injected in the autoregistration of cmos image sensor according to claim 1, which is characterized in that the note
Enter the thickness of protective layer no more than 20 nanometers.
8. manufacturing method is injected in the autoregistration of cmos image sensor according to claim 1, which is characterized in that described the
One sacrificial layer with a thickness of 100-500 nanometers.
9. manufacturing method is injected in the autoregistration of cmos image sensor according to claim 1, which is characterized in that the note
The material for entering protective layer is silicon nitride, and the material of first sacrificial layer is silica.
10. manufacturing method is injected in the autoregistration of cmos image sensor according to claim 4, which is characterized in that described
3rd sacrifice layer is identical as the material of the gate oxide and thickness, second sacrificial layer and the transfer transistor gate
Material and thickness are identical.
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Citations (1)
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| CN102246303A (en) * | 2008-12-10 | 2011-11-16 | 伊斯曼柯达公司 | Image sensors with lateral overflow drains |
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| JPH0770698B2 (en) * | 1986-12-02 | 1995-07-31 | 日本電気株式会社 | Method of manufacturing solid-state imaging device |
| KR100523669B1 (en) * | 2003-04-29 | 2005-10-24 | 매그나칩 반도체 유한회사 | Method of manufacturing cmos image sensor |
| KR100716914B1 (en) * | 2005-12-29 | 2007-05-10 | 동부일렉트로닉스 주식회사 | Fabrication method of cmos image sensor |
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| CN102246303A (en) * | 2008-12-10 | 2011-11-16 | 伊斯曼柯达公司 | Image sensors with lateral overflow drains |
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