CN106601306B - Method for improving performance of flash memory chip - Google Patents
Method for improving performance of flash memory chip Download PDFInfo
- Publication number
- CN106601306B CN106601306B CN201611161176.0A CN201611161176A CN106601306B CN 106601306 B CN106601306 B CN 106601306B CN 201611161176 A CN201611161176 A CN 201611161176A CN 106601306 B CN106601306 B CN 106601306B
- Authority
- CN
- China
- Prior art keywords
- sector
- erase
- memory
- erasing
- overtime
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5004—Voltage
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5006—Current
Landscapes
- Read Only Memory (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
The invention relates to the field of memories, in particular to a method for improving the performance of a flash memory chip, which comprises the following steps: respectively carrying out erasing operation on each sector by taking a second erasing reference current as a standard; respectively judging whether the erasing time of each sector is overtime by taking second specification time as a standard, and recording all overtime sectors; searching the slowest erasing memory cell in the overtime sector, and respectively recording the address of the slowest erasing memory cell in each overtime sector; analyzing each address respectively to repair the storage unit corresponding to each address according to the analysis result; according to the technical scheme, the standard first erasing reference current is increased to expose the memory unit which is hidden deeper and has slow erasing, and meanwhile, the error search of the normal memory unit can be eliminated, so that the problem that the chip cannot be normally repaired due to the fact that the number of the memory units needing to be repaired is too large due to the problem is solved.
Description
Technical Field
The invention relates to the field of memories, in particular to a method for improving the performance of a flash memory chip.
Background
Flash memory chips typically include an array region formed by an array of memory devices, each memory cell configured to store one bit of data, and the memory cells in the array region are typically logically divided into a plurality of sectors.
The market is demanding more and more on the speed and performance of erase operations for flash memory products. Due to the existence of single or a few memory cells which are slowly erased in the array area, firstly, during the performance test, the chip or sector erasing time exceeds the specification time and is invalid; secondly, the whole sector erasing time is longer and longer in the testing process, and the erasing time can be several times or even dozens of times of that of a normal sector along with the testing, so that the performance of the flash memory chip can not meet the requirements of customers.
At present, the problem of searching for memory cells with slow erase in a flash memory chip is mainly found by a uniform fixed reference current or reference voltage in a read operation, which causes the following problems: the memory cells with slow erase cannot be searched completely; the normal memory cells are searched by mistake, and the memory cells to be repaired are too many due to too many wrong searches, so that the chip can not be repaired normally.
Disclosure of Invention
In view of the above problems, the present invention provides a method for improving performance of a flash memory chip, where the flash memory chip includes a memory array, the memory array includes a plurality of sectors, each of the sectors includes a plurality of memory cells, and each of the memory cells is configured to store one bit of data;
providing a first erasing reference current for comparing with the current in the memory unit to judge whether the data stored in the memory unit is erased or not;
providing a first specification time for judging whether the sector is overtime and invalid in the erasing process;
the method comprises the following steps:
step S1, performing an erase operation on each of the sectors respectively based on a second erase reference current higher than the first erase reference current;
step S2, determining whether the erase time of each sector is over time based on a second specification time shorter than the first specification time, and recording all over-time sectors;
step S3, searching for the memory cell with the slowest erase in the overtime sectors, and recording the address of the memory cell with the slowest erase in each overtime sector;
step S4, analyzing each address respectively, so as to repair the storage unit corresponding to each address respectively according to the analysis result.
In the above method, a specific method of searching for the memory cell with the slowest erase in each of the failed sectors is:
providing a step voltage on the word line of the memory unit, respectively searching the overtime sectors in a reading mode by adopting the step voltage according to the sequence from high to low, defining the memory unit as the memory unit with the slowest erasing when the first memory unit is searched, and stopping searching in the current sector.
The method described above, wherein, further comprising:
step S5, performing a normal erase test on the sector where each repaired memory cell is located, respectively, with the first erase reference current and the first specification time as standards;
in step S6, if the erase test is passed, the second erase reference current is restored to the first erase reference current.
The method above, wherein the highest voltage of the step voltages is higher than a preset upper limit;
the preset upper limit is a maximum threshold voltage of the memory cell in an erased state.
The method above, wherein the preset upper limit is 4.5V.
The method above, wherein the difference between voltage values of adjacent steps is equal.
The method above, wherein the difference is 0.1V.
In the above method, before analyzing each address separately, each address needs to be compressed.
The method above, wherein the operation of searching the sector with the timeout is a read operation.
In the above method, a testing machine is provided;
the tester provides test signals required for the erase operation and the read operation, an
The tester records the address.
Has the advantages that: the method for improving the performance of the flash memory chip provided by the invention has the advantages that the standard first erasing reference current is increased to expose the memory unit which is hidden deeper and has slow erasing, and meanwhile, the error search of the normal memory unit can be eliminated, so that the problem that the chip cannot be normally repaired due to excessive memory units needing to be repaired caused by the problem is avoided.
Drawings
FIG. 1 is a flowchart illustrating steps of a method for improving performance of a flash memory chip according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating steps of a method for improving performance of a flash memory chip according to an embodiment of the present invention;
FIG. 3 is a distribution diagram of the respective sectors and the summed cells in a read operation at a staircase voltage according to an embodiment of the present invention;
FIGS. 4-6 are graphs showing the distribution of memory cells of sector 0, sector 2 and sector 4 according to the staircase voltage during a read operation, respectively, in accordance with one embodiment of the present invention.
Detailed Description
The invention is further illustrated with reference to the following figures and examples.
In a preferred embodiment, as shown in fig. 1, a method for improving performance of a flash memory chip is provided, the flash memory chip includes a memory array, the memory array includes a plurality of sectors, each sector includes a plurality of memory cells, and each memory cell is used for storing one bit of data;
providing a first erase reference current for comparing with the current in the memory cell to determine whether the data stored in the memory cell is erased;
providing a first specification time for judging whether the sector is overtime and invalid in the erasing process;
the method further comprises the following steps:
step S1, performing an erase operation on each sector respectively based on a second erase reference current higher than the first erase reference current;
step S2, respectively judging whether the erasing time of each sector is overtime by using a second specification time shorter than the first specification time as a standard, and recording all overtime sectors;
step S3, searching the memory unit with the slowest erasure in the overtime sector, and respectively recording the address of the memory unit with the slowest erasure in each overtime sector;
and step 4, analyzing each address respectively, so as to repair the memory cell corresponding to each address respectively according to the analysis result.
Specifically, the erase speed of each memory device in the sector is different, and some memory cells which are erased slowly are hidden deeply, so that the memory device which is erased slowly is exposed by raising the standard first erase reference current, so that the memory cells which are erased slowly (hidden) are distinguished from the memory cells which are erased normally in the subsequent steps, and the search is more thorough.
In a preferred embodiment, the specific method of searching for the slowest erased memory cell in each failed sector is:
providing a step voltage on the word line of the memory unit, respectively searching the whole overtime sector in a reading mode by adopting the step voltage according to the sequence from high to low, defining the memory unit as the memory unit with the slowest erasing when the first memory unit is searched, and stopping the search in the current sector.
For example, the step voltage may be set to a set of voltages having a maximum value of 4.5V and a minimum value of 3.7V based on the erase reference voltage of 4.1V, so as to be stepped.
In a preferred embodiment, as shown in fig. 2, the method may further include:
step S5, normal erasing test is respectively carried out on the sector where each repaired storage unit is located by taking the first erasing reference current and the first specification time as standards;
in step S6, if the erase test is passed, the second erase reference current is restored to the first erase reference current.
In the above embodiment, preferably, the highest voltage in the step voltage is higher than a preset upper limit;
the predetermined upper limit is the maximum threshold voltage of the memory cell in the erased state. Therefore, the highest voltage in the step voltage can be prevented from being not high enough to a certain extent, and the memory cell which is erased the slowest is prevented from being missed out of the searching range.
In the above embodiment, preferably, the preset upper limit is 4.5V.
In the above-described embodiment, it is preferable that the difference between voltage values of adjacent magnitudes in the step voltage be equal.
In the above embodiment, preferably, the difference is 0.1V.
In a preferred embodiment, each address needs to be compressed before being analyzed separately.
In a preferred embodiment, the operation of searching for a sector that times out is a read operation.
In a preferred embodiment, a tester is provided;
the tester provides test signals required for erase operation and read operation, an
The tester records the address.
More specifically, the analysis can be performed with reference to FIGS. 3-6. In fig. 3, BLK0, BLK1, BLK2 and BLK3 represent sector 0, sector 1, sector 2 and sector 3, respectively, where sector 0, sector 2 and sector 3 time out and sector 1 does not time out, and it can be analyzed that, although sector 0 and sector 1 both seek to obtain a memory cell that is slowest relative to the sector when the step voltage is, for example, 4.1V, such as the memory cell corresponding to the rightmost sample of the horizontal axis in fig. 4-6, since sector 1 does not time out and sector 0 times out, the memory cell obtained by sector 1 at 4.1V is a normal memory cell, and the memory device corresponding to sector 0 is a memory cell that is slow to erase; sector 2 is searched at 4.0V to obtain a memory cell, which is a severely slow erasing cell and is a hidden slow erasing cell, and the memory cell can be identified by using the invention.
Respectively carrying out erasing operation on each sector by taking a second erasing reference current as a standard; judging whether the erasing time of each sector is overtime or not by adopting second specification time, and recording all overtime sectors; searching the slowest erasing memory cell in the overtime sector, and respectively recording the address of the slowest erasing memory cell in each overtime sector; analyzing each address respectively to repair the storage unit corresponding to each address according to the analysis result; according to the technical scheme, the standard first erasing reference current is increased to expose the memory unit which is hidden deeper and has slow erasing, and meanwhile, the error search of the normal memory unit can be eliminated, so that the problem that the chip cannot be normally repaired due to the fact that the number of the memory units needing to be repaired is too large due to the problem is solved.
While the specification concludes with claims defining exemplary embodiments of particular structures for practicing the invention, it is believed that other modifications will be made in the spirit of the invention. While the above invention sets forth presently preferred embodiments, these are not intended as limitations.
Various alterations and modifications will no doubt become apparent to those skilled in the art after having read the above description. Therefore, the appended claims should be construed to cover all such variations and modifications as fall within the true spirit and scope of the invention. Any and all equivalent ranges and contents within the scope of the claims should be considered to be within the intent and scope of the present invention.
Claims (10)
1. A method for improving the performance of a flash memory chip, wherein the flash memory chip comprises a memory array, the memory array comprises a plurality of sectors, each sector comprises a plurality of memory cells, and each memory cell is used for storing one bit of data;
providing a first erasing reference current for comparing with the current in the memory unit to judge whether the data stored in the memory unit is erased or not;
providing a first specification time for judging whether the sector is overtime and invalid in the erasing process;
characterized in that the method comprises:
step S1, performing an erase operation on each of the sectors respectively based on a second erase reference current higher than the first erase reference current;
step S2, determining whether the erase time of each sector is over time based on a second specification time shorter than the first specification time, and recording all over-time sectors;
step S3, searching for the memory cell with the slowest erase in the overtime sectors, and recording the address of the memory cell with the slowest erase in each overtime sector;
step S4, analyzing each address respectively, so as to repair the storage unit corresponding to each address respectively according to the analysis result.
2. The method of claim 1, wherein the specific method of searching for the slowest erased memory cell in each of the sectors that have timed out is:
providing a step voltage on the word line of the memory unit, respectively searching the overtime sectors in a reading mode by adopting the step voltage according to the sequence from high to low, defining the memory unit as the memory unit with the slowest erasing when the first memory unit is searched, and stopping searching in the current sector.
3. The method of claim 1, further comprising:
step S5, performing a normal erase test on the sector where each repaired memory cell is located, respectively, with the first erase reference current and the first specification time as standards;
in step S6, if the erase test is passed, the second erase reference current is restored to the first erase reference current.
4. The method of claim 2, wherein the highest voltage of the step voltages is above a predetermined upper limit;
the preset upper limit is a maximum threshold voltage of the memory cell in an erased state.
5. The method of claim 4, wherein the predetermined upper limit is 4.5V.
6. The method of claim 2, wherein the step voltages have equal differences between adjacent voltage values.
7. The method of claim 6, wherein the difference is 0.1V.
8. The method of claim 1, wherein each of the addresses is compressed before being analyzed separately.
9. The method of claim 1, wherein the operation of searching for the sector that times out is a read operation.
10. The method of claim 1, wherein a tester is provided;
the tester provides test signals required for the erase operation and the read operation, an
The tester records the address.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611161176.0A CN106601306B (en) | 2016-12-15 | 2016-12-15 | Method for improving performance of flash memory chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611161176.0A CN106601306B (en) | 2016-12-15 | 2016-12-15 | Method for improving performance of flash memory chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106601306A CN106601306A (en) | 2017-04-26 |
| CN106601306B true CN106601306B (en) | 2019-12-31 |
Family
ID=58802571
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611161176.0A Active CN106601306B (en) | 2016-12-15 | 2016-12-15 | Method for improving performance of flash memory chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106601306B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101652762A (en) * | 2008-04-24 | 2010-02-17 | 株式会社东芝 | Memory system |
| CN102568588A (en) * | 2010-12-31 | 2012-07-11 | 北京兆易创新科技有限公司 | Over-erasing checking method and over-erasing checking system for non-volatile memory |
| CN104051012A (en) * | 2013-03-15 | 2014-09-17 | 北京兆易创新科技股份有限公司 | Memory erase method and device |
| CN104217760A (en) * | 2014-08-26 | 2014-12-17 | 上海华虹宏力半导体制造有限公司 | Flash memory configuration method |
| CN104464809A (en) * | 2014-11-05 | 2015-03-25 | 武汉新芯集成电路制造有限公司 | Method for prolonging service life of flash memory |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5741427B2 (en) * | 2011-12-28 | 2015-07-01 | 富士通セミコンダクター株式会社 | Semiconductor memory device testing method and semiconductor memory device |
-
2016
- 2016-12-15 CN CN201611161176.0A patent/CN106601306B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101652762A (en) * | 2008-04-24 | 2010-02-17 | 株式会社东芝 | Memory system |
| CN102568588A (en) * | 2010-12-31 | 2012-07-11 | 北京兆易创新科技有限公司 | Over-erasing checking method and over-erasing checking system for non-volatile memory |
| CN104051012A (en) * | 2013-03-15 | 2014-09-17 | 北京兆易创新科技股份有限公司 | Memory erase method and device |
| CN104217760A (en) * | 2014-08-26 | 2014-12-17 | 上海华虹宏力半导体制造有限公司 | Flash memory configuration method |
| CN104464809A (en) * | 2014-11-05 | 2015-03-25 | 武汉新芯集成电路制造有限公司 | Method for prolonging service life of flash memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106601306A (en) | 2017-04-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101498009B1 (en) | Defective block isolation in a non-volatile memory system | |
| US7050344B1 (en) | Failure test method for split gate flash memory | |
| US6477672B1 (en) | Memory testing apparatus | |
| EP2062265B1 (en) | Non-volatile memory and method for reduced erase/write cycling during trimming of initial programming voltage | |
| US8429326B2 (en) | Method and system for NAND-flash identification without reading device ID table | |
| US9218242B2 (en) | Write operations for defect management in nonvolatile memory | |
| WO2022198903A1 (en) | Detection method and detection apparatus for memory | |
| US20100020614A1 (en) | Non-Volatile Memory With Linear Estimation of Initial Programming Voltage | |
| US20080062765A1 (en) | Method for Non-Volatile Memory With Linear Estimation of Initial Programming Voltage | |
| JP2000348492A5 (en) | ||
| JP4819951B2 (en) | Nonvolatile memory and method for linear estimation of initial programming voltage | |
| US7859900B2 (en) | Built-in self-repair method for NAND flash memory and system thereof | |
| US7272758B2 (en) | Defective memory block identification in a memory device | |
| CN101308703B (en) | Method for nrom array word line retry erasing and threshold voltage recovering | |
| JP4227974B2 (en) | Chip information management method, chip information management system, and chip information management program | |
| CN112579382A (en) | NVMe solid state disk bad block analysis method, device, terminal and storage medium | |
| CN106601306B (en) | Method for improving performance of flash memory chip | |
| JP2000195300A (en) | Flash memory and its testing method | |
| CN109390029B (en) | Method and device for automatically repairing word line fault of NOR type memory array | |
| Martirosyan et al. | An efficient fault detection and diagnosis methodology for volatile and non-volatile memories | |
| US7415646B1 (en) | Page—EXE erase algorithm for flash memory | |
| CN101458968B (en) | Method and device for obtaining disabled binary digit distribution information in non-volatile memory | |
| JPH09288899A (en) | Semiconductor storage device | |
| CN110942800B (en) | Three-dimensional memory data retention capability test structure and test method | |
| US8923083B2 (en) | Method of identifying damaged bitline address in non-volatile |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |