CN106601302A - Electric fuse memory unit and electric fuse memory array - Google Patents
Electric fuse memory unit and electric fuse memory array Download PDFInfo
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- CN106601302A CN106601302A CN201510661896.2A CN201510661896A CN106601302A CN 106601302 A CN106601302 A CN 106601302A CN 201510661896 A CN201510661896 A CN 201510661896A CN 106601302 A CN106601302 A CN 106601302A
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- transistor
- electric fuse
- memory element
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- bit line
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Abstract
The present invention provides an electric fuse memory unit and an electric fuse memory array, and relates to the technical field of semiconductors. The electric fuse memory unit comprises: an electric fuse provided with a first terminal and a second terminal opposite to the first terminal; a first transistor, wherein the drain electrode of the first transistor is connected to the second terminal of the electric fuse, the grid electrode of the first transistor is connected to a read word line, and the source electrode of the first transistor is connected to a first bit line; and a second transistor, wherein the drain electrode of the second transistor is connected to the second terminal of the electric fuse, and the grid electrode of the second transistor is connected to a fusing word line. According to the embodiments of the present invention, the NMOS transistor transmission gate connected to the read word line is additionally arranged between the electric fuse and the second transistor to separate the read and the write so as to limit the flowing read current, such that the number of the read operations is not limited, and the read operation speed of the electric fuse memory unit can be improved through the new read time sequence.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of electric fuse memory element
With electric fuse storage array.
Background technology
In technical field of semiconductors, electrically programmable fuse (eFuse) technology due to with
The advantage such as CMOS logic device is compatible and easy to use and as disposable programmable (OTP)
Memorizer is widely used in many circuits.
EFuse technology is theoretical according to electromigration, by electric fuse by the fusing of electric current whether depositing
Storage information, polysilicon electric fuse resistance very little before fusing, the electricity after lasting high current fusing
Infinity is visually done in resistance, and the state of electric fuse fracture is by permanent holding.EFuse technology
It has been widely used in redundant circuit to improve the problem of chip failure or the ID of chip, if
Standby basic code etc. is replacing the disposable programmable memory of low capacity.
Figure 1A shows the schematic diagram of existing eFuse memory element, eFuse memory element,
Including electric fuse and a nmos pass transistor, the nmos pass transistor is the crystalline substance of read-write multiplexing
Body pipe, it has than larger size, therefore the speed ratio of its read operation is relatively low.Figure 1B shows
The schematic diagram of existing eFuse storage arrays is gone out, it includes that rows and columns eFuse are stored
Unit, grid connection wordline WL of the NMOS in each eFuse memory element, wordline
WL is the holding wire for controlling read operation, by the electric current of electric fuse be subject to read current and it is lasting when
Between restriction, therefore, limit the number of times of read operation.
Because the width of polysilicon electric fuse is more and more narrow, change is limited more for read operation
Seriously, for example in 28nm node technologies.The presence of the problems referred to above so that eFuse technology
In being only used for the application of limited read operation number of times, for example, when system is opened, with accordingly
SRAM store eFuse macro-data；Again for example, stored ID is seldom read,
Unless needed for inspection chip id.
Therefore, it is necessary to a kind of new electric fuse memory element and electric fuse storage array are proposed,
To solve during a bin as low capacity, in some high-speed applications, it is no longer necessary to utilize
Static memory (SRAM) goes first to read data to meet unconfined reading number of times and same with system
The problem of the reading rate of step.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will be concrete real
Apply in mode part and further describe.The Summary of the present invention is not meant to
Attempt the key feature and essential features for limiting technical scheme required for protection, less
Mean the protection domain for attempting to determine technical scheme required for protection.
For the deficiencies in the prior art, the present invention provides a kind of electric fuse memory element, including：
Electric fuse, the electric fuse has first end and second end relative with the first end；
The first transistor, second end of the drain electrode of the first transistor and the electric fuse
Connection, the grid connection readout word line of the first transistor, the source electrode of the first transistor connects
Connect the first bit line；
Transistor seconds, second end of the drain electrode of the transistor seconds and the electric fuse
Connection, the grid connection of the transistor seconds fuses wordline.
Further, the first transistor and the transistor seconds are nmos pass transistor.
Further, the first transistor is PMOS transistor.
Further, the size of the first transistor is less than the size of the transistor seconds two
The order of magnitude.
Further, when fusing, the conducting resistance of the transistor seconds is than the electric fuse
Resistance is order of magnitude greater.
Further, the conducting resistance of a first transistor number less than the resistance of the fuse
Magnitude.
Further, the source ground of the transistor seconds.
Further, the first end of the electric fuse connects the second bit line.
The embodiment of the present invention two provides a kind of electric fuse storage array, including：
Some row readout word lines, some rows fuse wordline, the bit line of some row first and some row second
Bit line；
Into several electric fuse memory element of rows and columns arrangement, each described electric fuse is deposited
Storage unit includes：Electric fuse, the electric fuse has first end and relative with the first end
Second end, the first transistor, the drain electrode of the first transistor and described the of the electric fuse
Two ends connect, and the grid of the first transistor connects its readout word line being expert at, described
The source electrode of the first transistor connects first bit line of its column, and transistor seconds is described
The drain electrode of transistor seconds is connected with second end of the electric fuse, the transistor seconds
Grid connect that it is expert at described fuse wordline.
Further, also including several PMOS transistors, each described PMOS transistor
Drain electrode be connected with second bit line of its column respectively.
Further, keep the PMOS transistor always on, make the first transistor
Door is controlled as readout word line.
Further, the first transistor and the transistor seconds are nmos pass transistor.
Further, the first transistor is PMOS transistor.
Further, the size of the first transistor is less than the size of the transistor seconds two
The order of magnitude.
Further, when fusing, the conducting resistance of the transistor seconds is than the electric fuse
Resistance is order of magnitude greater.
Further, the conducting resistance of the first transistor is less than the resistance of the electric fuse one
The order of magnitude.
Further, the source ground of the transistor seconds, the first end of the electric fuse
Connect second bit line of its column.
Electric fuse memory element in the embodiment of the present invention is by electric fuse and transistor seconds
Between increase the nmos pass transistor transmission gate that is connected with readout word line so that read-write separates,
Reach restriction and flow through read current so that the number of times of read operation is unrestricted, and with during new reading
Sequence is improving the read operation speed of electric fuse memory element.
Description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.It is attached
Embodiments of the invention and its description are shown in figure, for explaining the principle of the present invention.
In accompanying drawing：
Figure 1A shows the structural representation of existing eFuse memory element；
Figure 1B shows the structural representation of existing eFuse storage arrays；
Fig. 2 is the structural representation of the eFuse memory element of one embodiment of the present of invention；
Fig. 3 is the structural representation of the eFuse storage arrays of one embodiment of the present of invention；
Fig. 4 is shown in the sequential chart of the storage array of prior art and the embodiment of the present invention two
Storage array sequential chart, wherein, sequential chart 4a for prior art storage array when
Sequence figure, sequential chart 4b is the sequential chart of the storage array in the embodiment of the present invention two.
Specific embodiment
In the following description, a large amount of concrete details are given to provide to the present invention more
Thoroughly understand.It is, however, obvious to a person skilled in the art that of the invention
Can be carried out without the need for one or more of these details.In other examples, in order to keep away
Exempt to obscure with the present invention, for some technical characteristics well known in the art are not described.
It should be appreciated that the present invention can be implemented in different forms, and it is not construed as office
It is limited to embodiments presented herein.On the contrary, providing these embodiments disclosure will be made thoroughly and complete
Entirely, and will fully convey the scope of the invention to those skilled in the art.In the accompanying drawings,
In order to clear, the size and relative size in Ceng He areas may be exaggerated.It is identical attached from start to finish
Icon note represents identical element.
It should be understood that be referred to as when element or layer " ... on ", " with ... it is adjacent ", " being connected to "
Or when " being coupled to " other elements or layer, its can directly on other elements or layer and
It is adjacent, be connected or coupled to other elements or layer, or there may be element between two parties or layer.
Conversely, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " being directly connected to "
Or when " being directly coupled to " other elements or layer, then there is no element between two parties or layer.Should
Understand, although can using term first, second, third, etc. describe various elements, part,
Area, floor and/or part, these elements, part, area, floor and/or part should not be by these
Term is limited.These terms be used merely to distinguish element, part, area, floor or part with
Another element, part, area, floor or part.Therefore, without departing from present invention teach that under,
First element discussed below, part, area, floor or part be represented by the second element, part,
Area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... it
Under ", " ... on ", " above " etc., can describe for convenience here and by using from
And an element or feature shown in figure are described with other elements or the relation of feature.Should be bright
In vain, in addition to the orientation shown in figure, spatial relationship term is intended to also include using and operate
In device different orientation.For example, if the device upset in accompanying drawing, then, is described as
" below other elements " or " under it " or " under it " element or feature will be orientated
Be other elements or feature " on ".Therefore, exemplary term " ... below " and " ...
Under " may include upper and lower two orientations.Device can additionally be orientated and (be rotated by 90 ° or other
Orientation) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as this
Bright restriction.When here is used, " one " of singulative, " one " and " described/should "
It is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that art
Language " composition " and/or " including ", when using in this specification, determine the feature,
The presence of integer, step, operation, element and/or part, but be not excluded for it is one or more its
The presence or addition of its feature, integer, step, operation, element, part and/or group.
When here is used, term "and/or" includes any and all combination of related Listed Items.
Herein with reference to the horizontal stroke of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Sectional view is describing inventive embodiment.As a result, it is contemplated that due to such as manufacturing technology and/
Or from the change of shown shape caused by tolerance.Therefore, embodiments of the invention should not limit to
In the given shape in area shown here, but including inclined due to for example manufacturing caused shape
Difference.For example, be shown as the injection region of rectangle its edge generally there is circle or bending features and
/ or implantation concentration gradient, rather than the binary change from injection region to non-injection regions.Equally,
The disposal area formed by injection can cause the surface that the disposal area and injection are passed through when carrying out
Between area in some injection.Therefore, the area for showing in figure is substantially schematic, it
Shape be not intended display device area true form and be not intended limit the present invention
Scope.
In order to thoroughly understand the present invention, detailed structure will be proposed in following description, so as to
Explain technical scheme proposed by the present invention.Presently preferred embodiments of the present invention is described in detail as follows, so
And in addition to these detailed descriptions, the present invention can also have other embodiment.
Embodiment one
Below, deposit come a kind of eFuse for describing one embodiment of the present of invention proposition with reference to Fig. 2
Storage unit.
Exemplarily, as shown in Fig. 2 the eFuse memory element of the present invention, including following unit
Part：
Including electric fuse 20, the electric fuse 20 have first end 1 and with the first end 1
The second relative end 2.The first end of the electric fuse connects the second bit line (not shown).
Exemplarily, the material of the electric fuse 20 can include polysilicon.Wherein described
One end 1 is the anode of electric fuse 20, and second end is the negative electrode of electric fuse 20.
Also include the first transistor 21, the drain electrode of the first transistor 21 and the electric fuse
20 second end 2 connects, the grid connection readout word line RWL of the first transistor 21,
The source electrode connection sense bit line RBL of the first transistor 21.The conduct of the first transistor 21
Read operation transistor.
Also include transistor seconds 22, the drain electrode of the transistor seconds 22 and the electric fuse
20 second end 2 connects, and the grid connection of the transistor seconds 22 fuses wordline
BWL.Further, the source ground of the transistor seconds 22.The transistor seconds is made
For write operation transistor.
In one example, the first transistor 21 be nmos pass transistor, described second
Transistor 22 is nmos pass transistor.Wherein, the size of the first transistor 21 compares institute
State little two orders of magnitude of size of transistor seconds 22.When fusing, the transistor seconds
22 conducting resistance is more order of magnitude greater than the resistance of the electric fuse 20.And it is described first brilliant
The conducting resistance of body pipe 21 an order of magnitude less than the resistance of the electric fuse 20.
The NMOS being connected with readout word line by the increase between electric fuse and transistor seconds is brilliant
Body pipe transmission gate is overcoming the restriction to read operation.Nmos pass transistor transmission gate is used to limit stream
Jing read currents, and cause the number of times of read operation unrestricted.
The challenge for wherein overcoming read operation number of times is mainly manifested in following aspect：
(1) size of maximum read current (read current) is restricted, for example, due to
The conducting resistance of the first transistor an order of magnitude less than the resistance of the electric fuse, therefore
Read current fuses the 1/10 of electric current (burning current) for maximum, when maximum fuses electric current
For 15mA when, then maximum read current is 1.5mA；Maximum readout time is also limited accordingly
System, for example, maximum readout time (read flow time) is 1s, then read access number of times is about
10000000 times, calculating formula is 1/100ns=10000000.
(2) maximum measured (when not fusing) before fusing flows through electric current and is restricted, for example
Fuse electric current for maximum 1/100, when it is 15mA that maximum fuses electric current, then it is
0.15mA.And limit without number of times.
Exemplarily, the first transistor can also be capable of achieving phase with PMOS transistor
Same function.
In sum, the electric fuse memory element in the embodiment of the present invention is by electric fuse and
Increase the nmos pass transistor transmission gate that is connected with readout word line between two-transistor to overcome to reading
The restriction of operation.Separate read-write using different nmos pass transistors to flow through reaching restriction
The effect of read current so that the number of times of read operation is unrestricted.
Embodiment two
A kind of electric fuse storage array is also provided in another embodiment of the present invention, the electric fuse is deposited
Storage array includes the electric fuse memory element in previous embodiment.
Specifically, the electric fuse storage array in the embodiment of the present invention is carried out in detail with reference to Fig. 3
Description.
The electric fuse storage array of this enforcement includes several electric fuse memory element 30, described
The 30 one-tenth rows and columns arrangements of several electric fuse memory element, for example, are arranged in m rows,
N is arranged, and wherein m and n is integer.
Electric fuse storage array in the embodiment of the present invention also includes several PMOS transistors
31, each PMOS transistor 31 drain electrode respectively with the second bit line BL2 of its column
It is connected, the quantity of the PMOS transistor can be equal to the columns of electric fuse memory element, example
Such as, if several electric fuse memory element 30 are arranged as n row, there is n PMOS brilliant
Body pipe 31, the corresponding string electric fuse memory element of each PMOS transistor 31.Further
Ground, source electrode connection the power line Vdd, power line Vdd of each PMOS transistor 31
Suitable for providing supply voltage, the grid of each PMOS transistor is connected to column decoding
Device, column decoder is applied to each column PMOS transistor offer column decoding signal, and the row are translated
Code signal is used to control the on or off of PMOS transistor.
Electric fuse storage array in the embodiment of the present invention also include some row readout word line RWL,
Some rows fuse wordline BWL, some row the first bit line BL1 and some row the second bit line BL2.
In the present embodiment, the quantity of the first bit line BL1 and the second bit line BL2 is stored with electric fuse
The columns correspondence of unit, for example, there is n row electric fuse memory element, then have the bit line of n row first
BL1, and n row the second bit line BL2.Readout word line RWL and the number for fusing wordline BWL
Amount is corresponding with the line number of electric fuse memory element, for example, there is m row electric fuse memory element,
M row readout word line RWL then can be set, and m rows fuse wordline BWL.
Exemplarily, each described electric fuse memory element 30 includes：Each described electric fuse
Memory element includes：Electric fuse, the electric fuse has first end and relative with the first end
The second end, the first transistor, the drain electrode of the first transistor with described in the electric fuse
Second end connects, and the grid of the first transistor connects its readout word line being expert at
RWL, the source electrode of the first transistor connects the first bit line BL1 of its column,
Transistor seconds, the drain electrode of the transistor seconds connects with second end of the electric fuse
Connect, what the grid of the transistor seconds connected that it is expert at described fuses wordline BWL.
Exemplarily, the material of the electric fuse can include polysilicon.Wherein described first end
For the anode of electric fuse, second end is the negative electrode of electric fuse.
Further, the source ground of the transistor seconds, the electricity that each memory element includes
The first end of fuse connects the second bit line BL2 of its column.
In one example, the first transistor is nmos pass transistor, and described second is brilliant
Body pipe is nmos pass transistor.Wherein, the size of the first transistor is more brilliant than described second
Little two orders of magnitude of size of body pipe.When fusing, the conducting resistance ratio of the transistor seconds
The resistance of the fuse is order of magnitude greater.And the conducting resistance of the first transistor is than described
Little an order of magnitude of resistance of fuse.
The electric fuse storage array being related in the embodiment of the present invention has different read operation sequential
(read operation timing).Nmos pass transistor conduct is fused with using for prior art
Wordline control door is different.In the present embodiment, then by electric fuse memory element 30
Nmos pass transistor that grid is connected with sense bit line and a PMOS transistor 31 are used as reading road
Footpath controls door.
As Fig. 4 is shown in the sequential chart and the embodiment of the present invention of storage array of prior art
Storage array sequential chart, wherein sequential chart 4a for prior art storage array sequential
Figure, sequential chart 4b is the sequential chart of the storage array in the embodiment of the present invention.Wherein, for
For prior art, as shown in figure sequential chart 4a, each electric fuse memory element only has one
Individual nmos pass transistor, the grid of the nmos pass transistor connects its wordline being expert at, when
When circuit carries out read operation, PMOS transistor connects high level, and PMOS transistor is closed, the
A line wordline connects high level, then read the nmos pass transistor N1 conductings in unit 1, afterwards,
The wordline being connected with the nmos pass transistor N2 grids of the reading unit 2 positioned at another row connects height
Level, then N2 conductings.
As shown in sequential chart 4b, the embodiment of the present invention adopts sequential unlike the prior art,
For in the embodiment of the present invention reading element circuit work for read operation state when, PMOS crystal
Pipe connects low level, keeps PMOS transistor to open, and will fuse wordline BWL connecing low level,
Make to fuse the closing of wordline BWL, be connected with the grid for reading the first transistor in unit 1
Readout word line RWL1 connects high level, then the first transistor conducting, then will be stored in node
Data read-out afterwards, is connected to sense bit line with the grid for reading the first transistor in unit 2
Readout word line RWL2 connect high level, then read unit 2 in the first transistor conducting, pass through
Each reads the conducting of the first transistor in unit realizing read operation.
Wherein, in the present embodiment, when read operation is carried out, PMOS transistor is kept as far as possible
It is always on, control door as readout word line using the first transistor namely nmos pass transistor.
The size of the first transistor two orders of magnitude less than the size of the transistor seconds, therefore wordline
It is less with what the load of bit line became, therefore, compared with prior art, the reading behaviour in the present embodiment
Make speed faster.
Therefore, it can in the following manner accelerate read access speed, (1) is by increasing and reading
To reduce wordline load and bit-line load, (2) exist the connected nmos pass transistor of wordline BWL
Using mentioning in foregoing teachings between PMOS transistor, transistor seconds and the first transistor
Sequential.
The present invention is illustrated by above-mentioned two embodiment, how to cause read operation
Number of times is unrestricted, and realizes the function of reading synchronously to use.Therefore SRAM can not be used
To store the data of eFuse.
But it is to be understood that, above-described embodiment is only intended to citing and descriptive purpose, rather than
It is intended to limit the invention in described scope of embodiments.In addition those skilled in the art can
To be understood by, above-described embodiment is the invention is not limited in, teaching of the invention may be used also
To make more kinds of variants and modifications, for example, the first transistor can be with PMOS
Transistor, is also capable of achieving identical function.These variants and modifications are all fallen within required by the present invention
Within the scope of protection.Protection scope of the present invention is by the appended claims and its equivalent model
Enclose and defined.
Claims (17)
1. a kind of electric fuse memory element, including：
Electric fuse, the electric fuse has first end and second end relative with the first end；
The first transistor, second end of the drain electrode of the first transistor and the electric fuse
Connection, the grid connection readout word line of the first transistor, the source electrode of the first transistor connects
Connect the first bit line；
Transistor seconds, second end of the drain electrode of the transistor seconds and the electric fuse
Connection, the grid connection of the transistor seconds fuses wordline.
2. electric fuse memory element according to claim 1, it is characterised in that described
The first transistor and the transistor seconds are nmos pass transistor.
3. electric fuse memory element according to claim 1, it is characterised in that described
The first transistor is PMOS transistor.
4. electric fuse memory element according to claim 1, it is characterised in that described
The size of the first transistor two orders of magnitude less than the size of the transistor seconds.
5. electric fuse memory element according to claim 4, it is characterised in that molten
During burning, a conducting resistance quantity bigger than the resistance of the electric fuse of the transistor seconds
Level.
6. electric fuse memory element according to claim 4, it is characterised in that described
The conducting resistance of the first transistor an order of magnitude less than the resistance of the fuse.
7. electric fuse memory element according to claim 1, it is characterised in that described
The source ground of transistor seconds.
8. electric fuse memory element according to claim 1, it is characterised in that described
The first end of electric fuse connects the second bit line.
9. a kind of electric fuse storage array, including：
Some row readout word lines, some rows fuse wordline, the bit line of some row first and some row second
Bit line；
Into several electric fuse memory element of rows and columns arrangement, each described electric fuse is deposited
Storage unit includes：Electric fuse, the electric fuse has first end and relative with the first end
Second end, the first transistor, the drain electrode of the first transistor and described the of the electric fuse
Two ends connect, and the grid of the first transistor connects its readout word line being expert at, described
The source electrode of the first transistor connects first bit line of its column, and transistor seconds is described
The drain electrode of transistor seconds is connected with second end of the electric fuse, the transistor seconds
Grid connect that it is expert at described fuse wordline.
10. electric fuse storage array according to claim 9, it is characterised in that also wrap
Include several PMOS transistors, the drain electrode of each PMOS transistor respectively with its institute
It is connected in second bit line of row.
11. electric fuse storage arrays according to claim 10, it is characterised in that protect
Hold the PMOS transistor always on, make the first transistor as readout word line control
Door.
12. electric fuse storage arrays according to claim 9, it is characterised in that described
The first transistor and the transistor seconds are nmos pass transistor.
13. electric fuse storage arrays according to claim 9, it is characterised in that described
The first transistor is PMOS transistor.
14. electric fuse storage arrays according to claim 9, it is characterised in that described
The size of the first transistor two orders of magnitude less than the size of the transistor seconds.
15. electric fuse storage arrays according to claim 14, it is characterised in that
When fusing, a conducting resistance quantity bigger than the resistance of the electric fuse of the transistor seconds
Level.
16. electric fuse storage arrays according to claim 14, it is characterised in that institute
State conducting resistance an order of magnitude less than the resistance of the electric fuse of the first transistor.
17. electric fuse storage arrays according to claim 9, it is characterised in that described
The source ground of transistor seconds, the first end of the electric fuse connects the institute of its column
State the second bit line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510661896.2A CN106601302A (en) | 2015-10-14 | 2015-10-14 | Electric fuse memory unit and electric fuse memory array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510661896.2A CN106601302A (en) | 2015-10-14 | 2015-10-14 | Electric fuse memory unit and electric fuse memory array |
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| Publication Number | Publication Date |
|---|---|
| CN106601302A true CN106601302A (en) | 2017-04-26 |
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|---|---|---|---|
| CN201510661896.2A Pending CN106601302A (en) | 2015-10-14 | 2015-10-14 | Electric fuse memory unit and electric fuse memory array |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111899772A (en) * | 2019-05-05 | 2020-11-06 | 中芯国际集成电路制造(上海)有限公司 | efuse memory cell, memory and writing and reading methods thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102403017A (en) * | 2010-09-08 | 2012-04-04 | 台湾积体电路制造股份有限公司 | Electrical fuse memory arrays |
| CN102959637A (en) * | 2010-06-28 | 2013-03-06 | 高通股份有限公司 | Non-volatile memory with split write and read bitlines |
| CN103065685A (en) * | 2011-10-21 | 2013-04-24 | 台湾积体电路制造股份有限公司 | Electrical fuse memory arrays |
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2015
- 2015-10-14 CN CN201510661896.2A patent/CN106601302A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102959637A (en) * | 2010-06-28 | 2013-03-06 | 高通股份有限公司 | Non-volatile memory with split write and read bitlines |
| CN102403017A (en) * | 2010-09-08 | 2012-04-04 | 台湾积体电路制造股份有限公司 | Electrical fuse memory arrays |
| CN103065685A (en) * | 2011-10-21 | 2013-04-24 | 台湾积体电路制造股份有限公司 | Electrical fuse memory arrays |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111899772A (en) * | 2019-05-05 | 2020-11-06 | 中芯国际集成电路制造(上海)有限公司 | efuse memory cell, memory and writing and reading methods thereof |
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Application publication date: 20170426 |