CN106601196A - Gate drive circuit and operation method thereof - Google Patents
Gate drive circuit and operation method thereof Download PDFInfo
- Publication number
- CN106601196A CN106601196A CN201511004839.3A CN201511004839A CN106601196A CN 106601196 A CN106601196 A CN 106601196A CN 201511004839 A CN201511004839 A CN 201511004839A CN 106601196 A CN106601196 A CN 106601196A
- Authority
- CN
- China
- Prior art keywords
- transistor
- gate drive
- drive circuit
- contact
- closed mode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
Abstract
The invention discloses a gate drive circuit, including a bias pin and first to fifth transistors. The bias pin is coupled to an external resistor and an external capacitor. The first transistor is coupled between the first gate drive voltage and the first contact. The first contact is coupled to the output of the gate drive circuit. The second transistor is coupled to the second and third contacts. The second contact is coupled to the first contact and the third contact is coupled to the bias pin. The first transistor and the third to fifth transistors are P-type transistors and the second transistor is an N-type transistor. The third to fifth transistors are arranged to be opposite to the second transistor and is parallelly connected to the second and third contacts. During the precharge period, the first transistor is maintained in the on state and the second transistor is maintained in the closed state, and the third to fifth transistors are sequentially turned from the closed state to the on state.
Description
Technical field
The present invention is with the drive circuit of display panels relevant, especially with regard to a kind of display panels that are applied to
Gate drive circuit and its How It Works.
Background technology
Generally, due to the transistor switch on display panels is had on parasitic capacitance and display panels often
The storage capacitors value of individual pixel (Pixel) is also not quite similar, and causes gate drive circuit to export the lock to display panels
The gate output voltage signal of polar curve (Gate Lines) is switching to relatively low by the first higher gate drive voltage (VGH)
During two gate drive voltage (VGL) voltage that storage capacitors can be stored have a coupling effect, even if to common voltage
(VCOM) after being adjusted, the picture shown by display panels still has the phenomenon of flicker (Flicker) to be occurred.
In order to improve above-mentioned film flicker phenomenon, it will usually by the gate output voltage signal to gate drive circuit
Waveform carry out the mode of top rake (Gate Pulse Shading) to carry out.Fig. 1 to Fig. 3 is refer to, Fig. 1 is prior art
The schematic diagram of gate drive circuit；Fig. 2 is the sequential chart of the control signal S1～S3 in Fig. 1；Fig. 3 is to proceed by waveform chamfering
When the schematic diagram of voltage dips phenomenon that affected and occur by the external parasitic capacitances of gate drive circuit.
As shown in figure 1, in traditional gate drive circuit 1, bias pin PB is respectively coupled to non-essential resistance RE and outside
Electric capacity CP, when gate drive circuit 1 not yet carries out top rake (during the T1 in Fig. 2) to gate output voltage signal, external electrical
The electric charge held on CP is zero；When gate drive circuit 1 starts to carry out gate output voltage signal top rake (during the T2 in Fig. 2)
When, electric charge and gate drive circuit 1 that the electric charge in external capacitive CP can be first and in internal capacitance CG of gate drive circuit 1
External load electric capacity CLOAD on electric charge one another and, and cause the voltage VBIAS and the first contact N1 of bias pin PB
Voltage VGHP reaches a steady state point, and this will cause when the time T2 is entered, and gate output voltage signal can be because aforesaid electric charge
Neutralizing effect and first rapid decrease, when the voltage VGHP of the voltage VBIAS and the first contact N1 of bias pin PB reaches steady state point
The waveform of top rake just occurs afterwards.This voltage dips phenomenon is more obvious, that is, lock in the case where external capacitive CP is bigger
The top rake waveform of pole output voltage signal can be affected by the size of the external parasitic capacitances of gate drive circuit and be changed, urgently
It is to be overcome.
The content of the invention
Therefore, the present invention proposes a kind of gate drive circuit and its How It Works, to solve what prior art was suffered from
The problems referred to above.
A preferred embodiment of the invention is a kind of gate drive circuit.In this embodiment, gate drive
Circuit is applied to display panels.Gate drive circuit includes bias pin, the first transistor, transistor seconds, the 3rd brilliant
Body pipe, the 4th transistor and the 5th transistor.Bias pin is respectively coupled to non-essential resistance and external capacitive.The first transistor is coupled
Between the first gate drive voltage and the first contact, wherein the first contact couples the output end of gate drive circuit.Second is brilliant
Body pipe is respectively coupled to the second contact and the 3rd contact, wherein the second contact couples the first contact and the 3rd contact coupling bias connects
Pin.Third transistor arranges and is respectively coupled to the second contact and the 3rd contact relative to transistor seconds.4th transistor is relative
The second contact and the 3rd contact are arranged and are also respectively coupled in transistor seconds.5th transistor is arranged relative to transistor seconds
And also it is respectively coupled to the second contact and the 3rd contact.The first transistor, third transistor, the 4th transistor and the 5th transistor are equal
It is N-type transistor for P-type transistor and transistor seconds；Third transistor, the 4th transistor and the 5th transistor are connected in parallel to each other；
Interior in the precharge phase of gate drive circuit, the first transistor is maintained under opening and transistor seconds is maintained at closing
Under state, third transistor, the 4th transistor and the 5th transistor sequentially by closed mode are changed into opening respectively.
In an embodiment, when gate drive circuit terminate between precharge phase and during entering waveform chamfering it is interior, first is brilliant
Body pipe is changed into closed mode by opening and transistor seconds is changed into opening by closed mode, third transistor,
4th transistor and the 5th transistor are maintained under opening.
In an embodiment, when gate drive circuit enter precharge phase between before, gate drive circuit normal operation and
The first transistor is maintained under opening, and transistor seconds, third transistor, the 4th transistor and the 5th transistor are maintained
Under closed mode.
In an embodiment, during gate drive circuit terminates waveform chamfering and within a non-overlapped period, first
Transistor is maintained under closed mode, and transistor seconds is changed into closed mode, third transistor, the 4th crystal by opening
Pipe and the 5th transistor are changed into closed mode by opening.
In an embodiment, after gate drive circuit terminates non-overlapped period, gate drive circuit normal operation and
One transistor is changed into opening, transistor seconds, third transistor, the 4th transistor and the 5th transistor by closed mode
It is maintained under closed mode.
In an embodiment, gate drive circuit further includes internal capacitance, and its one end is coupled to the first contact and the
Between two point and its other end couples second gate drive voltage, wherein the second gate drive voltage is less than the first gate drive
Voltage.
Another preferred embodiment of the invention is also a kind of gate drive circuit.In this embodiment, gate
Drive circuit is applied to display panels.Gate drive circuit includes bias pin, the first transistor～the 4th transistor.Partially
Crimping pin is respectively coupled to non-essential resistance and external capacitive.The first transistor be coupled to the first gate drive voltage and the first contact it
Between, wherein the first contact couples the output end of gate drive circuit.Transistor seconds is respectively coupled to the second contact and the 3rd contact,
Wherein the second contact couples the first contact and the 3rd contact coupling bias pin.Third transistor is arranged relative to transistor seconds
And it is respectively coupled to the second contact and the 3rd contact.4th transistor couples are between the first gate drive voltage and bias pin.
The first transistor, third transistor and the 4th transistor are P-type transistor and transistor seconds is N-type transistor；In gate
The precharge phase of drive circuit is interior, and the first transistor is maintained under opening and transistor seconds and third transistor are tieed up
Under being held in closed mode, the 4th transistor is changed into opening by closed mode.
In an embodiment, further comprise the steps of：When the gate drive circuit terminates to be gone forward side by side between the precharge phase
It is interior during entering a waveform chamfering, by the first transistor by opening be changed into closed mode and by the transistor seconds by
Closed mode is changed into opening, and maintains the third transistor, the 4th transistor and the 5th transistor respectively in opening
Under opening state.
In an embodiment, further comprise the steps of：Before the gate drive circuit is entered between the precharge phase,
The gate drive circuit normal operation and maintain the first transistor under opening, and maintain respectively the transistor seconds,
The third transistor, the 4th transistor and the 5th transistor are under closed mode.
In an embodiment, further comprise the steps of：During the gate drive circuit terminates the waveform chamfering simultaneously
Into within a non-overlapped period, the first transistor is maintained under closed mode, and the transistor seconds is turned by opening
It is changed into closed mode and is respectively changed into the third transistor, the 4th transistor and the 5th transistor by opening
Closed mode.
In an embodiment, further comprise the steps of：After the gate drive circuit terminates the non-overlapped period, should
Gate drive circuit normal operation and the first transistor is changed into into opening by closed mode, and maintain respectively this second
Transistor, the third transistor, the 4th transistor and the 5th transistor are under closed mode.
In an embodiment, the gate drive circuit further includes an internal capacitance, and one end of the internal capacitance couples
To between first contact and second contact and its other end couples one second gate drive voltage, second gate drive electricity
Force down in the first gate drive voltage.
Another preferred embodiment of the invention is a kind of gate drive circuit How It Works.In this embodiment
In, gate drive circuit How It Works are applied to the gate drive circuit of display panels to operate.Gate drive circuit
Comprising bias pin, the first transistor, transistor seconds, third transistor, the 4th transistor and the 5th transistor.Bias pin
It is respectively coupled to non-essential resistance and external capacitive.The first transistor is coupled between the first gate drive voltage and the first contact.The
One contact couples the output end of gate drive circuit, and transistor seconds is respectively coupled to the second contact and the 3rd contact, the second contact
Couple the first contact and the 3rd contact coupling bias pin, the first transistor, third transistor, the 4th transistor and the 5th crystal
Pipe is P-type transistor and transistor seconds is N-type transistor.Gate drive circuit How It Works are comprised the steps of：By
Three transistors, the 4th transistor and the 5th transistor are connected in parallel to each other and arrange both with respect to transistor seconds and be respectively coupled to second
Contact and the 3rd contact；And it is interior in the precharge phase of gate drive circuit, maintain the first transistor under opening and
Transistor seconds is maintained under closed mode, and by third transistor, the 4th transistor and the 5th transistor sequentially respectively by closing
Closed state is changed into opening.
In an embodiment, when the gate drive circuit terminate between the precharge phase and during entering a waveform chamfering it is interior,
The first transistor and the 4th transistor are changed into closed mode and the transistor seconds and the 3rd brilliant by opening
Body pipe is changed into opening by closed mode.
In an embodiment, before the gate drive circuit is entered between the precharge phase, the gate drive circuit is normal
Operate and the first transistor is maintained under opening, the transistor seconds, the third transistor and the 4th transistor are equal
Under being maintained at closed mode.
In an embodiment, during the gate drive circuit terminates the waveform chamfering and within a non-overlapped period,
The first transistor and the 4th transistor are maintained under closed mode, and the transistor seconds and the third transistor are by opening
The state of opening is changed into closed mode.
In an embodiment, after the gate drive circuit terminates the non-overlapped period, the gate drive circuit is normally transported
Make and the first transistor is changed into opening by closed mode, the transistor seconds, the third transistor and the 4th are brilliant
Body Guan Jun is maintained under closed mode.
In an embodiment, further include：One internal capacitance, its one end is coupled to first contact and second contact
Between and its other end couples one second gate drive voltage, wherein the second gate drive voltage is less than first gate drive
Voltage.
Another preferred embodiment of the invention is also a kind of gate drive circuit How It Works.In this embodiment
In, gate drive circuit How It Works are applied to the gate drive circuit of display panels to operate.Gate drive circuit
Comprising bias pin, the first transistor, transistor seconds, third transistor and the 4th transistor.Bias pin is respectively coupled to outer
Portion's resistance and external capacitive.The first transistor is coupled between the first gate drive voltage and the first contact.First contact is coupled
The output end of gate drive circuit.Transistor seconds is respectively coupled to the second contact and the 3rd contact.Second contact coupling first connects
Point and the 3rd contact coupling bias pin.The first transistor, third transistor and the 4th transistor are P-type transistor and second
Transistor is N-type transistor.Gate drive circuit How It Works are comprised the steps of：By third transistor relative to the second crystal
Pipe arranges and is respectively coupled to the second contact and the 3rd contact；4th transistor couples are connect in the first gate drive voltage with bias
Between pin；And it is interior in the precharge phase of gate drive circuit, the first transistor is under opening and maintains respectively for maintenance
4th transistor is changed into opening by transistor seconds and third transistor under closed mode by closed mode.
In an embodiment, further comprise the steps of：When the gate drive circuit terminates to be gone forward side by side between the precharge phase
It is interior during entering a waveform chamfering, respectively the first transistor and the 4th transistor are changed into into closed mode simultaneously by opening
Respectively the transistor seconds and the third transistor are changed into into opening by closed mode.
In an embodiment, further comprise the steps of：Before the gate drive circuit is entered between the precharge phase,
The gate drive circuit normal operation and maintain the first transistor under opening, and maintain respectively the transistor seconds,
The third transistor and the 4th transistor are under closed mode.
In an embodiment, further comprise the steps of：During the gate drive circuit terminates the waveform chamfering simultaneously
Into within a non-overlapped period, the first transistor and the 4th transistor are maintained respectively under closed mode, and respectively should
Transistor seconds and the third transistor are changed into closed mode by opening.
In an embodiment, further comprise the steps of：After the gate drive circuit terminates the non-overlapped period, should
Gate drive circuit normal operation and the first transistor is changed into into opening by closed mode, and maintain respectively this second
Transistor, the third transistor and the 4th transistor are under closed mode.
In an embodiment, the gate drive circuit further includes an internal capacitance, and one end of the internal capacitance couples
To between first contact and second contact and its other end couples one second gate drive voltage, second gate drive electricity
Force down in the first gate drive voltage.
Compared to prior art, gate drive circuit of the invention and its How It Works can be prevented effectively from existing skill
Voltage dips (Voltage Drop) phenomenon produced during the waveform chamfering of gate output voltage signal is carried out in art so that root
The outside of gate drive circuit will not be subject to according to the top rake waveform obtained by the gate drive circuit and its How It Works of the present invention
The impact of the size of parasitic capacitance and change.
Can be entered by invention below specific embodiment and appended accompanying drawing with regard to the advantages and spirit of the present invention
The understanding of one step.
Description of the drawings
Fig. 1 is the schematic diagram of the gate drive circuit of prior art.
Fig. 2 is the sequential chart of the control signal S1～S3 in Fig. 1.
The electricity that Fig. 3 occurs for the impact that proceeds by external parasitic capacitances during waveform chamfering by gate drive circuit
Press the schematic diagram of the phenomenon that plunges.
Fig. 4 is the schematic diagram of the gate drive circuit of the preferred embodiment according to the present invention.
Fig. 5 is the sequential chart of the control signal S1～S5 in Fig. 4.
The schematic diagram that Fig. 6 will not be affected and change for top rake waveform by the external parasitic capacitances of gate drive circuit.
Fig. 7 is the schematic diagram of the gate drive circuit of another preferred embodiment according to the present invention.
Fig. 8 is the sequential chart of the control signal S1～S4 in Fig. 7.
The schematic diagram that Fig. 9 will not be affected and change for top rake waveform by the external parasitic capacitances of gate drive circuit.
Figure 10 is the schematic diagram of the gate drive circuit How It Works of another preferred embodiment according to the present invention.
Figure 11 is the schematic diagram of the gate drive circuit How It Works of another preferred embodiment according to the present invention.
Primary clustering symbol description
S10～S19, S20～S29 steps
1st, 4,7 gate drive circuit
M1～M7 the first transistors～the 7th transistor
The control signals of S1～S5 first～the 5th control signal
The contacts of N1～N3 first～the 3rd contact
During T0, T4 normal operation
Between T1 precharge phases
During T2 waveform chamferings
T3 non-overlapped periods
VGH the first gate drive voltages
VGL the second gate drive voltages
VSS common ground terminal voltages
The voltage of the contacts of VGHP first
VBIAS biases the voltage of pin
PB biases pin
RE non-essential resistances
CP external capacitives
CG internal capacitances
RLOAD load resistances
CLOAD load capacities
OUTPUT output ends
△ V falling quantity of voltages
Specific embodiment
A preferred embodiment of the invention is a kind of gate drive circuit.In this embodiment, gate drive
Circuit is applied to display panels, and to produce gate a plurality of gate line on display panels is outputed voltage signal to.
Fig. 4 is refer to, the schematic diagram of the gate drive circuit according to Fig. 4 in this specific embodiment.As shown in figure 4, lock
Pole drive circuit 4 includes bias pin PB, the first transistor M1, transistor seconds M2, third transistor M3, the 4th transistor M4
And the 5th transistor M5.
Bias pin PB is respectively coupled to non-essential resistance RE and external capacitive CP.Wherein, non-essential resistance RE is coupled to bias and connects
Between pin PB and common ground terminal voltage VSS；External capacitive CP be also coupled to bias pin PB and common ground terminal voltage VSS it
Between.In fact, external capacitive CP can be a parasitic capacitance, non-essential resistance RE can be a variable resistor, but be not limited.
The first transistor M1 is coupled between the first gate drive voltage VGH and the first contact N1, wherein the first contact N1
Output end OUTPUT of coupling gate drive circuit 4.Transistor seconds M2 is respectively coupled to the second contact N2 and the 3rd contact N3, its
In the second contact N2 couple the first contact N1 and the 3rd contact N3 coupling bias pin PB.
Third transistor M3, the 4th transistor M4 and the 5th transistor M5 are connected in parallel to each other, and wherein third transistor M3 is relative
The second contact N2 and the 3rd contact N3 is arranged and is respectively coupled in transistor seconds M2；4th transistor M4 is relative to the second crystal
Pipe M2 arranges and is also respectively coupled to the second contact N2 and the 3rd contact N3；5th transistor M5 is arranged relative to transistor seconds M2
And also it is respectively coupled to the second contact N2 and the 3rd contact N3.
It should be noted that, in this embodiment, the first transistor M1, third transistor M3, the 4th transistor M4 and the 5th
Transistor M5 is P-type transistor and transistor seconds M2 is N-type transistor, but is not limited.The first transistor M1, second
Transistor M2, third transistor M3, the 4th transistor M4 and the 5th transistor M5 gate respectively be subject to the first control signal S1,
The control of the second control signal S2, the 3rd control signal S3, the 4th control signal S4 and the 5th control signal S5 and it is selective at
In the state being turned on and off.
In fact, as shown in figure 4, gate drive circuit 4 also includes internal capacitance CG.One end coupling of internal capacitance CG
To between the first contact N1 and the second contact N2 and internal capacitance CG the other end couple the second gate drive voltage VGL, wherein
Second gate drive voltage VGL is less than the first gate drive voltage VGH.
Additionally, as shown in figure 4, gate drive circuit 4 also includes the 6th transistor M6 and the 7th transistor M7, wherein
Six transistor M6 are P-type transistors and the 7th transistor M7 is N-type transistors.6th transistor M6 and the 7th transistor
M7 is serially connected between the first contact N1 and the second gate drive voltage VGL, and the 6th transistor M6 and the 7th transistor M7
Gate is controlled by the second gate drive voltage VGL.Output end OUTPUT of gate drive circuit 4 is located at the 6th transistor M6
Between the 7th transistor M7, and the load resistance RLOAD outside the coupling of output end OUTPUT.As for outside load capacity
CLOAD is then coupled between load resistance RLOAD and common ground terminal voltage VSS.
Then, Fig. 5 is refer to, Fig. 5 is the first control signal S1, the second control signal S2, the 3rd control signal in Fig. 4
The sequential chart of S3, the 4th control signal S4 and the 5th control signal S5.
As shown in figure 5, during normal operation in T0, the normal operation of gate drive circuit 4 and the first transistor M1 is maintained
Under (ON) state of unlatching, and transistor seconds M2, third transistor M3, the 4th transistor M4 and the 5th transistor M5 are maintained
Under (OFF) state of closing.
Enter T1 between precharge phase during T0 immediately during gate drive circuit 4 terminates normal operation.In between precharge phase
In T1, the first transistor M1 is still maintained under unlatching (ON) state and transistor seconds M2 is still maintained under closing (OFF) state,
Then can sequentially respectively by closing (OFF) state of script as third transistor M3, the 4th transistor M4 and the 5th transistor M5
It is changed into unlatching (ON) state.
Specifically third transistor M3, the 4th transistor M4 and the 5th transistor M5, in this embodiment is simultaneously
It is non-" while " unlatching (ON) state is changed into by closing (OFF) state of script, but be separated by a time difference " sequentially " by
Closing (OFF) state of script is changed into unlatching (ON) state, and its Main Function is：When T1 between precharge phase is had just enter into,
Only third transistor M3 is to open in the middle of third transistor M3, the 4th transistor M4 and the 5th transistor M5, other two
Transistor M4 and M5 are then to close, that is, the P-type number of transistors opened is less and impedance increases and produces current limliting, therefore energy
All P-type transistors unlatching simultaneously in prior art is avoided to cause the electric charge on the inside and outside electric capacity of gate drive circuit 4 each other
Voltage dips (Voltage Drop) phenomenon caused by neutralization.
T2 during entering waveform chamfering immediately when gate drive circuit 4 terminates T1 between precharge phase.In the waveform chamfering phase
Between in T2, the first transistor M1 can be changed into closing (OFF) state and transistor seconds M2 meetings by unlatching (ON) state of script
Unlatching (ON) state is changed into by closing (OFF) state of script, it is brilliant as third transistor M3, the 4th transistor M4 and the 5th
Body pipe M5 then can be maintained under the unlatching of script (ON) state.
Enter non-overlapped period T3 during T2 immediately during gate drive circuit 4 terminates waveform chamfering.In non-overlapped period
In T3, the first transistor M1 can be maintained under the closing of script (OFF) state, and transistor seconds M2 then can be by the unlatching of script
(ON) state is changed into closing (OFF) state, then all can as third transistor M3, the 4th transistor M4 and the 5th transistor M5
Closing (OFF) state is changed into by unlatching (ON) state of script.
T4 during being again introduced into normal operation immediately when gate drive circuit 4 terminates non-overlapped period T3.In normal fortune
During work in T4, the normal operation of gate drive circuit 4 and the first transistor M1 can be changed into by closing (OFF) state of script and hold
(ON) state is opened, then all can be maintained as transistor seconds M2, third transistor M3, the 4th transistor M4 and the 5th transistor M5
Under closing (OFF) state of script.Remaining can analogize according to above-mentioned, separately not repeat in this.
It should be noted that, as shown in fig. 6, between precharge phase in T1, the voltage of gate output voltage signal is equal to first
Gate drive voltage VGH；When T1 terminates and during into T2 during waveform chamfering between precharge phase, the electricity of gate output voltage signal
Pressure can start to increase and decline with the time from the first gate drive voltage VGH of script；T2 terminates simultaneously during waveform chamfering
During into non-overlapped period T3, the voltage of gate output voltage signal is had dropped to (under the first gate drive voltage VGH- voltages
Drop amount △ V), wherein falling quantity of voltages △ V is less than (first gate drive voltage VGH- the second gate drive voltage VGL).Then,
In non-overlapped period T3, the voltage of gate output voltage signal can again by (the first gate drive voltage VGH- falling quantity of voltages
△ V) continue to drop to the second gate drive voltage VGL till.
Next, refer to Fig. 7, in another preferred embodiment of the present invention, gate drive circuit 7 includes bias
Pin PB, the first transistor M1, transistor seconds M2, third transistor M3 and the 4th transistor M4.
Bias pin PB is respectively coupled to non-essential resistance RE and external capacitive CP.Wherein, non-essential resistance RE is coupled to bias and connects
Between pin PB and common ground terminal voltage VSS；External capacitive CP be also coupled to bias pin PB and common ground terminal voltage VSS it
Between.In fact, external capacitive CP can be a parasitic capacitance, non-essential resistance RE can be a variable resistor, but be not limited.
The first transistor M1 is coupled between the first gate drive voltage VGH and the first contact N1, wherein the first contact N1
Output end OUTPUT of coupling gate drive circuit 4.Transistor seconds M2 is respectively coupled to the second contact N2 and the 3rd contact N3, its
In the second contact N2 couple the first contact N1 and the 3rd contact N3 coupling bias pin PB.
Specifically, third transistor M3 arranges and is respectively coupled to the second contact N2 relative to transistor seconds M2
With the 3rd contact N3.4th transistor M4 is coupled between the first gate drive voltage VGH and bias pin PB.
In this embodiment, the first transistor M1, third transistor M3 and the 4th transistor M4 are P-type transistor and
Two-transistor M2 is N-type transistor, but is not limited.The first transistor M1, transistor seconds M2, third transistor M3,
The gate of four transistor M4 and the 5th transistor M5 is subject to respectively the first control signal S1, the second control signal S2, the 3rd control
Signal S3, the control of the 4th control signal S4 and the 5th control signal S5 and the selective state in being turned on and off.
In fact, as shown in fig. 7, gate drive circuit 7 also includes internal capacitance CG.One end coupling of internal capacitance CG
To between the first contact N1 and the second contact N2 and internal capacitance CG the other end couple the second gate drive voltage VGL, wherein
Second gate drive voltage VGL is less than the first gate drive voltage VGH.
Additionally, as shown in fig. 7, gate drive circuit 7 also includes the 5th transistor M5 and the 6th transistor M6, wherein
Five transistor M5 are P-type transistors and the 6th transistor M6 is N-type transistors.5th transistor M5 and the 6th transistor
M6 is serially connected between the first contact N1 and the second gate drive voltage VGL, and the 5th transistor M5 and the 6th transistor M6
Gate is controlled by the second gate drive voltage VGL.Output end OUTPUT of gate drive circuit 7 is located at the 5th transistor M5
Between the 6th transistor M6, and the load resistance RLOAD outside the coupling of output end OUTPUT.As for outside load capacity
CLOAD is then coupled between load resistance RLOAD and common ground terminal voltage VSS.
Then, Fig. 8 is refer to, Fig. 8 is the first control signal S1, the second control signal S2, the 3rd control signal in Fig. 7
The sequential chart of S3 and the 4th control signal S4.
As shown in figure 8, during normal operation in T0, the normal operation of gate drive circuit 7 and the first transistor M1 is maintained
Under (ON) state of unlatching, and transistor seconds M2, third transistor M3 and the 4th transistor M4 are maintained at closing (OFF) shape
Under state.
Enter T1 between precharge phase during T0 immediately during gate drive circuit 7 terminates normal operation.In between precharge phase
In T1, the first transistor M1 is still maintained under unlatching (ON) state and transistor seconds M2 and third transistor M3 are all still maintained at
Under (OFF) state of closing, then sequentially respectively unlatching can be changed into by closing (OFF) state of script as the 4th transistor M4
(ON) state.
Specifically, this embodiment by be coupled to the first gate drive voltage VGH and bias pin PB it
Between the 4th transistor M4 be changed into unlatching (ON) state to carry out preliminary filling to external capacitive CP by closing (OFF) state of script
Electricity, is then all maintained under closing (OFF) state so that in external capacitive CP as transistor seconds M2 and third transistor M3
Electric charge can not possibly with the electric charge in internal capacitance CG and external load electric capacity CLOAD one another and, therefore existing skill can be prevented effectively from
Voltage dips phenomenon in art occurs.
T2 during entering waveform chamfering immediately when gate drive circuit 7 terminates T1 between precharge phase.In the waveform chamfering phase
Between in T2, the first transistor M1 and the 4th transistor M4 can be changed into closing (OFF) state by unlatching (ON) state of script
And transistor seconds M2 and third transistor M3 can be changed into unlatching (ON) state by closing (OFF) state of script.
Enter non-overlapped period T3 during T2 immediately during gate drive circuit 7 terminates waveform chamfering.In non-overlapped period
In T3, the first transistor M1 and the 4th transistor M4 can be maintained under the closing of script (OFF) state, transistor seconds M2 and
Third transistor M3 then can be changed into closing (OFF) state by unlatching (ON) state of script.
T4 during being again introduced into normal operation immediately when gate drive circuit 7 terminates non-overlapped period T3.In normal fortune
During work in T4, the normal operation of gate drive circuit 7 and the first transistor M1 can be changed into by closing (OFF) state of script and hold
(ON) state is opened, as transistor seconds M2, third transistor M3 and the 4th transistor M4 the closing of script then can be all maintained at
(OFF) under state.Remaining can analogize according to above-mentioned, separately not repeat in this.
It should be noted that, as shown in figure 9, between precharge phase in T1, the voltage of gate output voltage signal is equal to first
Gate drive voltage VGH；When T1 terminates and during into T2 during waveform chamfering between precharge phase, the electricity of gate output voltage signal
Pressure can start to increase and decline with the time from the first gate drive voltage VGH of script；T2 terminates simultaneously during waveform chamfering
During into non-overlapped period T3, the voltage of gate output voltage signal is had dropped to (under the first gate drive voltage VGH- voltages
Drop amount △ V), wherein falling quantity of voltages △ V is less than (first gate drive voltage VGH- the second gate drive voltage VGL).Then,
In non-overlapped period T3, the voltage of gate output voltage signal can again by (the first gate drive voltage VGH- falling quantity of voltages
△ V) continue to drop to the second gate drive voltage VGL till.
Another preferred embodiment of the invention is a kind of gate drive circuit How It Works.In this embodiment
In, gate drive circuit How It Works are applied to the gate drive circuit of display panels to operate.Gate drive circuit
Comprising bias pin, the first transistor, transistor seconds, third transistor, the 4th transistor and the 5th transistor.Wherein,
One transistor, third transistor, the 4th transistor and the 5th transistor are P-type transistor and transistor seconds is N-type crystal
Pipe.
Bias pin is respectively coupled to non-essential resistance and external capacitive.The first transistor be coupled to the first gate drive voltage with
Between first contact.First contact couples the output end of gate drive circuit.Transistor seconds is respectively coupled to the second contact and
Three contacts.Second contact couples the first contact and the 3rd contact coupling bias pin.
Additionally, gate drive circuit can further include internal capacitance.One end of internal capacitance be coupled to the first contact with
Between second contact and its other end couples second gate drive voltage, wherein the second gate drive voltage is less than the drive of the first gate
Dynamic voltage.
Figure 10 is refer to, the schematic diagram of the gate drive circuit How It Works according to Figure 10 in this embodiment.Such as Figure 10
Shown, gate drive circuit How It Works are comprised the steps of：
(S10) the method is connected in parallel to each other third transistor, the 4th transistor and the 5th transistor and both with respect to second
Transistor arranges and is respectively coupled to the second contact and the 3rd contact；
(S12) interior during the normal operation of gate drive circuit, gate drive circuit normal operation and the method are maintained
The first transistor maintains respectively transistor seconds, third transistor, the 4th transistor and the 5th transistor under opening
Under closed mode；
(S14) it is interior in the precharge phase of gate drive circuit, the method maintain the first transistor under opening and
Transistor seconds is maintained under closed mode, and by third transistor, the 4th transistor and the 5th transistor sequentially respectively by closing
Closed state is changed into opening；
(S16) interior during the waveform chamfering of gate drive circuit, the method is changed the first transistor by opening
Opening is changed into by closed mode for closed mode and by transistor seconds, and maintain respectively third transistor, the 4th
Transistor and the 5th transistor are under opening；
(S18) within the non-overlapped period of gate drive circuit, the method maintains the first transistor under closed mode, and
Transistor seconds is changed into into closed mode and respectively by third transistor, the 4th transistor and the 5th crystal by opening
Pipe is changed into closed mode by opening；
(S19) after gate drive circuit terminates non-overlapped period, during gate drive circuit turns again to normal operation,
The first transistor is changed into opening by the method by closed mode, and maintain respectively transistor seconds, third transistor, the
Four transistors and the 5th transistor are under closed mode.
Another preferred embodiment of the invention is also a kind of gate drive circuit How It Works.In this embodiment
In, gate drive circuit How It Works are applied to the gate drive circuit of display panels to operate.Gate drive circuit
Comprising bias pin, the first transistor, transistor seconds, third transistor and the 4th transistor.Bias pin is respectively coupled to outer
Portion's resistance and external capacitive.The first transistor is coupled between the first gate drive voltage and the first contact.First contact is coupled
The output end of gate drive circuit.Transistor seconds is respectively coupled to the second contact and the 3rd contact.Second contact coupling first connects
Point and the 3rd contact coupling bias pin.The first transistor, third transistor and the 4th transistor are P-type transistor and second
Transistor is N-type transistor.
Figure 11 is refer to, the schematic diagram of the gate drive circuit How It Works according to Figure 11 in this embodiment.Such as Figure 11
Shown, gate drive circuit How It Works are comprised the steps of：
(S20) third transistor is arranged and is respectively coupled to the second contact and the 3rd contact relative to transistor seconds and incite somebody to action
4th transistor couples are between the first gate drive voltage and bias pin；
(S22) during the normal operation of gate drive circuit, gate drive circuit normal operation and the method maintain the
One transistor maintains respectively transistor seconds, third transistor and the 4th transistor under closed mode under opening；
(S24) it is interior in the precharge phase of gate drive circuit, the method maintain the first transistor under opening and
Transistor seconds and third transistor are maintained respectively under closed mode, and the 4th transistor is changed into into unlatching by closed mode
State；
(S26) interior during the waveform chamfering of gate drive circuit, the method is respectively by the first transistor and the 4th crystal
Pipe is changed into closed mode and respectively transistor seconds and third transistor is changed into into unlatching by closed mode by opening
State；
(S28) within the non-overlapped period of gate drive circuit, the method maintains respectively the first transistor and the 4th crystal
Transistor seconds and third transistor are changed into closed mode by pipe by opening respectively under closed mode；
(S29) after gate drive circuit terminates non-overlapped period, during gate drive circuit turns again to normal operation,
The first transistor is changed into opening by the method by closed mode, and maintain respectively transistor seconds, third transistor and
4th transistor is under closed mode.
Compared to prior art, gate drive circuit of the invention and its How It Works can be prevented effectively from existing skill
Voltage dips (Voltage Drop) phenomenon produced during waveform chamfering is carried out in art so that gate drive of the invention
Top rake waveform obtained by circuit and its How It Works will not be subject to the shadow of the size of the external parasitic capacitances of gate drive circuit
Ring and change.
By the above detailed description of preferred embodiments, it is intended to more clearly describe the feature of the present invention and spirit, and
Not scope of the invention is any limitation as with above-mentioned disclosed preferred embodiment.On the contrary, its objective is to wish
Being arranged in the category of the claim to be applied of the invention for various changes and tool equality can be covered.
Claims (24)
1. a kind of gate drive circuit, is applied to a display panels, it is characterised in that the gate drive circuit is included：
One bias pin, is respectively coupled to a non-essential resistance and an external capacitive；
One the first transistor, is coupled between one first gate drive voltage and one first contact, wherein the first contact coupling
One output end of the gate drive circuit；
One transistor seconds, is respectively coupled to one second contact and one the 3rd contact, and wherein second contact couples first contact
And the 3rd contact couple the bias pin；
One third transistor, arranges and is respectively coupled to second contact and the 3rd contact relative to the transistor seconds；
One the 4th transistor, arranges and is also respectively coupled to second contact and the 3rd contact relative to the transistor seconds；With
And
One the 5th transistor, arranges and is also respectively coupled to second contact and the 3rd contact relative to the transistor seconds；
Wherein, the first transistor, the third transistor, the 4th transistor and the 5th transistor be P-type transistor and
The transistor seconds is N-type transistor；The third transistor, the 4th transistor and the 5th transistor are connected in parallel to each other；In this
One precharge phase of gate drive circuit is interior, and the first transistor is maintained under opening and the transistor seconds is maintained at
Under closed mode, the third transistor, the 4th transistor and the 5th transistor are sequentially changed into out by closed mode respectively
Open state.
2. gate drive circuit as claimed in claim 1, it is characterised in that when the gate drive circuit terminates the precharge phase
Between and it is interior during entering a top rake, the first transistor is changed into closed mode by opening and the transistor seconds is by closing
State is changed into opening, and the third transistor, the 4th transistor and the 5th transistor are maintained under opening.
3. gate drive circuit as claimed in claim 1, it is characterised in that when the gate drive circuit enters the precharge phase
Between before, the gate drive circuit normal operation and the first transistor is maintained under opening, the transistor seconds, this
Three transistors, the 4th transistor and the 5th transistor are maintained under closed mode.
4. gate drive circuit as claimed in claim 2, it is characterised in that when the gate drive circuit terminates the waveform chamfering
Period is simultaneously entered in a non-overlapped period, and the first transistor is maintained under closed mode, and the transistor seconds is by opening
It is changed into closed mode, the third transistor, the 4th transistor and the 5th transistor are changed into closing by opening
State.
5. gate drive circuit as claimed in claim 4, it is characterised in that when the gate drive circuit terminates the non-overlapped phase
Between after, the gate drive circuit normal operation and the first transistor is changed into opening by closed mode, second crystal
Pipe, the third transistor, the 4th transistor and the 5th transistor are maintained under closed mode.
6. gate drive circuit as claimed in claim 1, it is characterised in that further include：
One internal capacitance, its one end is coupled between first contact and second contact and its other end couples one second gate
Driving voltage, wherein the second gate drive voltage are less than the first gate drive voltage.
7. a kind of gate drive circuit How It Works, to operate the gate drive circuit for being applied to a display panels,
Characterized in that, the gate drive circuit includes a bias pin, a first transistor, a transistor seconds, one the 3rd crystal
Pipe, one the 4th transistor and one the 5th transistor, the bias pin is respectively coupled to a non-essential resistance and an external capacitive, and this first
Between one first gate drive voltage and one first contact, first contact couples the gate drive circuit to transistor couples
One output end, the transistor seconds is respectively coupled to one second contact and one the 3rd contact, and second contact couples first contact
And the 3rd contact couple the bias pin, the first transistor, the third transistor, the 4th transistor and the 5th crystal
Pipe is P-type transistor and the transistor seconds is N-type transistor, and the gate drive circuit How It Works are comprised the steps of：
The third transistor, the 4th transistor and the 5th transistor are connected in parallel to each other and are set both with respect to the transistor seconds
Put and be respectively coupled to second contact and the 3rd contact；And
It is interior in a precharge phase of the gate drive circuit, maintain the first transistor under opening and maintain this second
Transistor under closed mode, and by the third transistor, the 4th transistor and the 5th transistor sequentially respectively by closing
State is changed into opening.
8. gate drive circuit How It Works as claimed in claim 7, it is characterised in that further comprise the steps of：
When the gate drive circuit terminate between the precharge phase and during entering a waveform chamfering it is interior, by the first transistor by opening
The state of opening is changed into closed mode and the transistor seconds is changed into into opening by closed mode, and maintain respectively this
Three transistors, the 4th transistor and the 5th transistor are under opening.
9. gate drive circuit How It Works as claimed in claim 7, it is characterised in that further comprise the steps of：
Before the gate drive circuit is entered between the precharge phase, the gate drive circuit normal operation and maintain this first brilliant
Body pipe maintains respectively the transistor seconds, the third transistor, the 4th transistor and the 5th crystal under opening
Pipe is under closed mode.
10. gate drive circuit How It Works as claimed in claim 8, it is characterised in that further comprise the steps of：
During the gate drive circuit terminates the waveform chamfering and enter a non-overlapped period in, maintain the first transistor in
Under closed mode, and by the transistor seconds by opening be changed into closed mode and respectively by the third transistor, should
4th transistor and the 5th transistor are changed into closed mode by opening.
11. gate drive circuit How It Works as claimed in claim 10, it is characterised in that further comprise the steps of：
After the gate drive circuit terminates the non-overlapped period, the gate drive circuit normal operation and by the first transistor
Opening is changed into by closed mode, and is maintained the transistor seconds, the third transistor, the 4th transistor respectively and is somebody's turn to do
5th transistor is under closed mode.
12. gate drive circuit How It Works as claimed in claim 7, it is characterised in that the gate drive circuit is further
Comprising an internal capacitance, one end of the internal capacitance is coupled between first contact and second contact and its other end coupling
One second gate drive voltage, the second gate drive voltage is less than the first gate drive voltage.
A kind of 13. gate drive circuits, are applied to a display panels, it is characterised in that the gate drive circuit is included：
One bias pin, is respectively coupled to a non-essential resistance and an external capacitive；
One the first transistor, is coupled between one first gate drive voltage and one first contact, wherein the first contact coupling
One output end of the gate drive circuit；
One transistor seconds, is respectively coupled to one second contact and one the 3rd contact, and wherein second contact couples first contact
And the 3rd contact couple the bias pin；
One third transistor, arranges and is respectively coupled to second contact and the 3rd contact relative to the transistor seconds；And
One the 4th transistor, is coupled between the first gate drive voltage and the bias pin；
Wherein, the first transistor, the third transistor and the 4th transistor are P-type transistor and the transistor seconds is
N-type transistor；It is interior in a precharge phase of the gate drive circuit, the first transistor be maintained under opening and this
Two-transistor and the third transistor are maintained under closed mode, and the 4th transistor is changed into unlatching shape by closed mode
State.
14. gate drive circuits as claimed in claim 13, it is characterised in that when the gate drive circuit terminates the precharge
Period is simultaneously interior during entering a waveform chamfering, and the first transistor and the 4th transistor are changed into closing shape by opening
State and the transistor seconds and the third transistor are changed into opening by closed mode.
15. gate drive circuits as claimed in claim 13, it is characterised in that when the gate drive circuit enters the precharge
Before period, the gate drive circuit normal operation and the first transistor is maintained under opening, the transistor seconds, should
Third transistor and the 4th transistor are maintained under closed mode.
16. gate drive circuits as claimed in claim 14, it is characterised in that cut when the gate drive circuit terminates the waveform
During angle and enter in a non-overlapped period, the first transistor and the 4th transistor are maintained under closed mode, this
Two-transistor and the third transistor are changed into closed mode by opening.
17. gate drive circuits as claimed in claim 16, it is characterised in that to terminate this non-overlapped when the gate drive circuit
After period, the gate drive circuit normal operation and the first transistor is changed into opening by closed mode, this is second brilliant
Body pipe, the third transistor and the 4th transistor are maintained under closed mode.
18. gate drive circuits as claimed in claim 13, it is characterised in that further include：
One internal capacitance, its one end is coupled between first contact and second contact and its other end couples one second gate
Driving voltage, wherein the second gate drive voltage are less than the first gate drive voltage.
A kind of 19. gate drive circuit How It Works, to operate the gate drive circuit for being applied to a display panels,
Characterized in that, the gate drive circuit includes a bias pin, a first transistor, a transistor seconds, one the 3rd crystal
Pipe and one the 4th transistor, the bias pin is respectively coupled to a non-essential resistance and an external capacitive, and the first transistor is coupled to
Between one first gate drive voltage and one first contact, first contact couples an output end of the gate drive circuit, should
Transistor seconds is respectively coupled to one second contact and one the 3rd contact, and second contact couples first contact and the 3rd contact
Couple the bias pin, the first transistor, the third transistor and the 4th transistor are P-type transistor and this is second brilliant
Body pipe is N-type transistor, and the gate drive circuit How It Works are comprised the steps of：
The third transistor is arranged and is respectively coupled to second contact and the 3rd contact relative to the transistor seconds；
By the 4th transistor couples between the first gate drive voltage and the bias pin；And
It is interior in a precharge phase of the gate drive circuit, maintain the first transistor under opening and maintain to be somebody's turn to do respectively
4th transistor is changed into unlatching shape by transistor seconds and the third transistor under closed mode by closed mode
State.
20. gate drive circuit How It Works as claimed in claim 19, it is characterised in that further comprise the steps of：
When the gate drive circuit terminate between the precharge phase and during entering a waveform chamfering it is interior, respectively by the first transistor
And the 4th transistor closed mode is changed into and respectively by the transistor seconds and the third transistor by closing by opening
Closed state is changed into opening.
21. gate drive circuit How It Works as claimed in claim 19, it is characterised in that further comprise the steps of：
Before the gate drive circuit is entered between the precharge phase, the gate drive circuit normal operation and maintain this first brilliant
Body pipe maintains respectively the transistor seconds, the third transistor and the 4th transistor in closed mode under opening
Under.
22. gate drive circuit How It Works as claimed in claim 20, it is characterised in that further comprise the steps of：
During the gate drive circuit terminates the waveform chamfering and within a non-overlapped period, the first crystal is maintained respectively
Manage and the 4th transistor is under closed mode, and respectively by the transistor seconds and the third transistor by opening transformation
For closed mode.
23. gate drive circuit How It Works as claimed in claim 22, it is characterised in that further comprise the steps of：
After the gate drive circuit terminates the non-overlapped period, the gate drive circuit normal operation and by the first transistor
Opening is changed into by closed mode, and maintain respectively the transistor seconds, the third transistor and the 4th transistor in
Under closed mode.
24. gate drive circuit How It Works as claimed in claim 19, it is characterised in that the gate drive circuit is further
Comprising an internal capacitance, one end of the internal capacitance is coupled between first contact and second contact and its other end coupling
One second gate drive voltage, the second gate drive voltage is less than the first gate drive voltage.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201562242443P | 2015-10-16 | 2015-10-16 | |
| US62/242,443 | 2015-10-16 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106601196A true CN106601196A (en) | 2017-04-26 |
| CN106601196B CN106601196B (en) | 2019-05-21 |
Family
ID=58555489
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201511004839.3A Active CN106601196B (en) | 2015-10-16 | 2015-12-29 | Gate drive circuit and its operation method |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN106601196B (en) |
| TW (1) | TWI587262B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1355520A (en) * | 2000-11-28 | 2002-06-26 | 凌阳科技股份有限公司 | Programmable driver circuit |
| US20060125759A1 (en) * | 2004-12-09 | 2006-06-15 | Samsung Electronics Co., Ltd. | Output buffer of a source driver in a Liquid Crystal Display having a high slew rate and a method of controlling the output buffer |
| US20060279356A1 (en) * | 2005-05-31 | 2006-12-14 | Samsung Electronics | Source driver controlling slew rate |
| US20070115243A1 (en) * | 2005-11-21 | 2007-05-24 | Samsung Electronics Co., Ltd. | Precharging circuits for a signal line of an Liquid Crystal Display (LCD) in which the precharge voltage is based on the magnitude of a gray-scale voltage corresponding to image data and related LCD systems, drivers, and methods |
| US20120169709A1 (en) * | 2010-12-31 | 2012-07-05 | Seung Kyu Lee | Gate driving circuit and display device including the same |
-
2015
- 2015-11-24 TW TW104139026A patent/TWI587262B/en active
- 2015-12-29 CN CN201511004839.3A patent/CN106601196B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1355520A (en) * | 2000-11-28 | 2002-06-26 | 凌阳科技股份有限公司 | Programmable driver circuit |
| US20060125759A1 (en) * | 2004-12-09 | 2006-06-15 | Samsung Electronics Co., Ltd. | Output buffer of a source driver in a Liquid Crystal Display having a high slew rate and a method of controlling the output buffer |
| US20060279356A1 (en) * | 2005-05-31 | 2006-12-14 | Samsung Electronics | Source driver controlling slew rate |
| US20070115243A1 (en) * | 2005-11-21 | 2007-05-24 | Samsung Electronics Co., Ltd. | Precharging circuits for a signal line of an Liquid Crystal Display (LCD) in which the precharge voltage is based on the magnitude of a gray-scale voltage corresponding to image data and related LCD systems, drivers, and methods |
| US20120169709A1 (en) * | 2010-12-31 | 2012-07-05 | Seung Kyu Lee | Gate driving circuit and display device including the same |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201715500A (en) | 2017-05-01 |
| CN106601196B (en) | 2019-05-21 |
| TWI587262B (en) | 2017-06-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104835442B (en) | Shift register and its driving method, gate driving circuit and display device | |
| CN102945651B (en) | Shift register, grid driving circuit and display device | |
| CN103761937B (en) | Shifting register unit, gate driving circuit, driving method of gate driving circuit and display device | |
| CN104485065B (en) | Shifting register, driving method and gate driving circuit | |
| CN107564491B (en) | A kind of shutdown discharge circuit, driving method, driving circuit and display device | |
| CN105390116B (en) | Gate driving circuit | |
| CN105427799B (en) | Shifting deposit unit, shift register, gate driving circuit and display device | |
| CN108877627A (en) | Shift register cell and driving method, gate driving circuit, display device | |
| CN105405387B (en) | Shift register cell and its driving method, gate driving circuit and display device | |
| CN107578741A (en) | Shift register cell and its driving method, gate driving circuit, display device | |
| CN105632565B (en) | Shift register and its driving method, gate driving circuit and display device | |
| CN107464521A (en) | Shift register cell, gate driving circuit and driving method, display device | |
| CN103000155B (en) | Shifting register unit, array substrate gate driving device and display device | |
| CN105261341B (en) | A kind of gate driving circuit and display device | |
| CN107068106A (en) | Shift register cell, driving method, gate driving circuit and display device | |
| CN104658498B (en) | Shifting register and gate driving circuit | |
| CN110264937B (en) | Gate drive circuit, test method thereof and display device | |
| CN103258500A (en) | Shifting registering unit and display device | |
| CN102136245B (en) | Shift register | |
| CN105637590A (en) | Shift register and display device | |
| CN103854622B (en) | A kind of gate driver circuit | |
| CN106847162B (en) | Gate driving unit, driving method, gate driving circuit and display device | |
| CN114038385B (en) | Gate driver and display device | |
| CN104575354A (en) | Grid driving circuit and driving method thereof | |
| CN108538237A (en) | A kind of gate driving circuit, method and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |