CN106598742B - SSD master control internal load balancing system and method - Google Patents
SSD master control internal load balancing system and method Download PDFInfo
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- CN106598742B CN106598742B CN201611217235.1A CN201611217235A CN106598742B CN 106598742 B CN106598742 B CN 106598742B CN 201611217235 A CN201611217235 A CN 201611217235A CN 106598742 B CN106598742 B CN 106598742B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
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- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a system and a method for balancing internal load of SSD master control, wherein the balancing system comprises a host interface: the host computer is responsible for receiving commands and data from the host computer, and simultaneously returning responses to the host computer and transmitting data to the host computer; NFC: the device is responsible for finishing command interaction and data transmission between the SSD master control and the NAND Flash; IO command equalization Engine: the system is responsible for distributing an IO command request from the host interface to the CPU for processing and simultaneously forwarding a response from the CPU to the host interface; a plurality of CPUs: the system is used for scheduling and processing the IO commands distributed by the IO command balancing engine and controlling data transmission. The invention solves the problems of chip area and power consumption in the design of a hardware-biased system, and also solves the problem of time delay increase caused by multi-CPU processing in the common software system scheme.
Description
Technical Field
The invention relates to SSD master control, in particular to an internal load balancing system and method for the SSD master control.
Background
The SSD master control is a key component of the SSD solid state disk, and the processing performance thereof determines the highest performance that the SSD solid state disk can achieve. In recent years, enterprise-level PCIe SSD host performance has entered millions of IOPS, and mainstream design vendors in the industry have generated two types of architectures in the process of continuously pursuing the very performance of SSD host: the hardware type is biased, FTL table item management of SSD master control is realized by logic RTL, and a CPU is mainly used for various exception handling; in the partial software type, the table item management is mainly realized by software, and a very strong CPU is adopted to support the algorithm.
The design of the hardware-biased system is characterized in that all main functions of the whole IO path, including FTL table item management, are realized by hardware logic gate circuits, and a CPU is mainly used for exception handling which rarely occurs. In the design mode, the main key functions are realized by adopting a hardware gate circuit, so that on one hand, the chip area is increased, the chip cost is increased, and on the other hand, the chip power consumption is increased. Meanwhile, the technical complexity of the design is very high, the stable period is long, and more technical risks and commercial risks can be brought to the product.
The design of the partial software type system is characterized in that hardware is mainly responsible for data access, and a CPU is responsible for controlling the interaction and data transmission of scheduling IO commands among hardware modules. Because the CPU participates in more IO processing, a processing resource bottleneck is usually encountered while pursuing the highest IOPS, thereby limiting the maximum IOPS specification of the system.
In summary, the problems that the power consumption is too high, the stable period is too long, and the technical threshold is high cannot be avoided due to the hardware type table item management design; the main problem of the software type is that the CPU resources are not enough, and the bottleneck of the CPU resources is usually limited, so that the maximum performance cannot be achieved.
In order to break through the bottleneck problem of CPU resources, the current software type mainstream scheme is mainly solved by increasing the number of CPUs in a chip. The main process of IO processing is divided into a plurality of sub-processes, each sub-process is processed by 1 CPU independently, and all CPUs finish the processing of the whole IO together, so that the purpose of improving the performance of the whole system is achieved. The method needs information interaction between CPUs, and the interaction times depend on the decomposed sub-processes. If the number of the decomposed sub-processes reaches to a single CPU is too small, the purpose of increasing CPU resources cannot be achieved; and too much decomposition results in too much interaction between CPUs, the total internal consumption of the CPUs is increased, and the time delay of each IO is increased.
Disclosure of Invention
The invention aims to solve the technical problem that the prior art is not enough, and provides an SSD master control internal load balancing system and method, which solve the problems of chip area and power consumption in the design of a hardware-biased system and simultaneously solve the problem of time delay increase caused by multi-CPU processing in the scheme of a common software-type system.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows: an SSD master internal load balancing system, comprising:
host interface: the host computer is responsible for receiving commands and data from the host computer, and simultaneously returning responses to the host computer and transmitting data to the host computer;
NFC: the device is responsible for finishing command interaction and data transmission between the SSD master control and the NAND Flash;
IO command equalization Engine: the system is responsible for distributing an IO command request from the host interface to the CPU for processing and simultaneously forwarding a response from the CPU to the host interface;
a plurality of CPUs: the system is used for scheduling and processing the IO commands distributed by the IO command balancing engine and controlling data transmission.
The IO command equalization engine comprises:
CMD Slot: the hardware RAM resource is used for storing the CMD context information and matching the command request with the response; (ii) a CMD context information, namely IO command context;
a processing engine: the system is used for managing CPU resources and CMD Slot resources and selecting a proper CPU for the IO command;
IO Router: the CPU is used for selecting a target CPU for the IO command according to the processing engine and distributing the IO command to the corresponding CPU through the multiplexer/demultiplexer;
multiplexer/demultiplexer: the system is used for distributing the IO commands to different CPUs and multiplexing the IO responses processed by the CPUs to the processing engine for further processing.
The process of distributing the IO command by the IO command balancing engine comprises the following steps:
1) after receiving the IO command, judging whether CMD Slot resources still exist, and if so, entering a step 2); otherwise, ending the processing, namely suspending the current IO command;
2) traversing the IO command being processed recorded by the next CMD Slot;
3) if the IO command to be processed and the IO command being processed recorded by the CMD Slot have an access lba (logical Block address) address conflict, selecting a CPU corresponding to the CMD Slot to process the IO command to be currently processed, and simultaneously allocating a new CMD Slot resource to store the context of the IO command, and entering step 4); otherwise, distributing new CMD Slot resources to the IO command to be processed currently, selecting the CPU with the least number of IO commands to be processed currently to process the IO command to be processed currently, and entering step 4);
4) forwarding the IO command to be processed to the selected CPU through the IO Router;
5) recording context information of the current IO command in the CMD Slot, and adding 1 to the number of the IO commands processed by the selected CPU;
6) and (6) ending.
The step of multiplexing the response processed by each CPU to the processing engine for further processing comprises:
1) the multiplexer/demultiplexer receives the IO response sent by the CPU;
2) subtracting 1 from the number of IO processes of the corresponding CPU, and releasing CMD Slot resources corresponding to the IO responses;
3) the processing engine forwards the IO response to the host interface and judges whether a pending IO command to be processed is in the waiting queue; if yes, reading and processing the IO command in the waiting queue, and entering the step 4); otherwise, entering step 4);
4) and (6) ending.
The invention also provides a method for balancing the SSD master control internal load by using the system, which mainly comprises the following implementation processes: IO commands are distributed among CPUs through an IO command balancing engine, each CPU independently processes the whole IO commands distributed to the CPU, and the CPUs are not mutually interacted.
The method for ensuring mutual non-interaction among CPUs comprises the following steps:
1) if the access LBA address conflict exists between the current IO command to be processed and the currently processed IO command recorded by the CMD Slot, allocating a new CMD Slot resource to the current IO command to be processed, selecting a CPU corresponding to the current CMD Slot resource to process the current IO command to be processed, and simultaneously allocating a new CMD Slot resource to store the current IO command context, and entering step 2); otherwise, distributing new CMD Slot resources to the IO command to be processed currently, selecting the CPU with the least number of IO commands to be processed currently to process the IO command to be processed currently, and entering the step 2);
2) and forwarding the IO command to be processed currently to the selected CPU for processing.
Compared with the prior art, the invention has the beneficial effects that: the invention distributes IO commands among a plurality of CPUs by utilizing an IO command load balancing engine in the SSD master control, the CPUs are not interacted with each other, IO processing among the CPUs is ensured to be really independent and not interfered with each other through an IO address conflict mechanism of the internal IO command load balancing engine, the problems of chip area and power consumption in the design of a hardware-biased system are solved, and the problem of time delay increase caused by multi-CPU processing in the common software system scheme is solved. By using the IO balance engine, the invention can process each IO independently and completely by using the multiple CPUs while processing the IO command by using the multiple CPU resources, thereby effectively avoiding the time delay increase caused by the expense of message interaction between the CPUs to a single IO command; according to the SSD master control system, the CPUs independently complete the same function and do not influence each other. The number of the CPU resources managed by the IO balance engine and the CPU resources of the actual physical layout can be simply configured, and the SSD master control chip with various performance specifications can be designed without changing the IO path and the processing flow.
Drawings
FIG. 1 is a block diagram of an integrated SSD master internal load balancing of the present invention;
FIG. 2 is a schematic diagram of an IO command balancing engine according to the present invention;
FIG. 3 is a timing diagram of an IO dispatch response of the present invention;
FIG. 4 is a flowchart illustrating the IO equalization engine distributing IO commands in accordance with the present invention;
FIG. 5 is a flow chart of the IO equalization engine processing IO command response of the present invention.
Detailed Description
The invention utilizes an IO command balancing engine to be responsible for distributing the IO commands from the HIF interface to each internal CPU, and each CPU is responsible for processing the IO received by the CPU. Each CPU has a unique number within the system.
Referring to fig. 1, the functions of the modules of the present invention are as follows:
HIF: host Interface, which is responsible for receiving commands and data from the Host, and returning responses and transmitting data to the Host.
NFC: and the Nand Flash Controller is responsible for finishing command interaction and data transmission between the SSD main control and the Nand Flash.
And the IO Command balancing Engine is responsible for completing the distribution of the IO Command request from the HIF module to the internal CPU for processing and forwarding the response from the internal CPU to the HIF. The IO command balancing engine can flexibly configure the number of CPU resources used for processing the IO command in the system to adapt to different SSD master control performance requirements.
Data Path: the data path, the data transmission path between HIF and NFC, mainly includes data bus and DMA engine, etc.
Data RAM: the data buffer is used for data buffer in the data transmission process of the data path.
CPUx: and the system is responsible for scheduling processing and controlling data transmission of the IO commands distributed by the IO command balancing engine. Each CPU performs the same computation and control functions.
As shown in fig. 2, the IO command balancing engine is responsible for selecting a suitable CPU for processing an IO for the IO, forwarding the IO to the CPU, and recording context information including an IO address range, a destination CPU identifier, the number of commands currently being processed by the destination CPU, and the like.
CMD Slot: and the Command Slot is used for storing the space of the IO Command context. The IO command context recorded by the CMD Slot comprises a CMD Slot valid identifier, an IO identifier and an IO address range.
Process Engine: and the processing engine is responsible for managing the CPU resources and the CMD Slot resources and selecting proper CPU resources for the IO command according to the strategy.
IO Router, according to the target CPU selected by the Process Engine for IO, distributes IO to the corresponding CPU through Demux.
Mux/Demux multiplexer/demultiplexer responsible for distributing IO commands to different CPUs and multiplexing the responses processed by the respective CPUs for further processing by the Process Engine.
The invention distributes the IO command among a plurality of CPUs by utilizing the IO command load balancing engine in the SSD master control, and the CPUs are not interacted with each other. According to the SSD master control, IO processing among CPUs is guaranteed to be truly independent and not interfered with each other through an IO address conflict mechanism of an internal IO command load balancing engine. Different performance requirements can be met by simply configuring the CPU resources managed by the IO command balancing engine. The IO command equalizer engine can detect whether address conflict exists between the IO to be distributed and processed by the current equalization processor and the IO being processed by each CPU. The IO command equalizer engine can distribute the IO to be distributed to the CPU corresponding to the IO with the conflict address for processing. The IO Command equalizer engine records the IO context information which is processed before and after in a Command Slot mode, wherein the IO context information comprises a target CPU number, an IO address range and the like. In the control message interacted between the IO Command equalizer engine and the CPU, a Command Slot number is carried to associate an IO request message which is distributed to the CPU by the equalization engine and an IO response message which is sent to the equalization engine by the CPU. And the IO command load balancing engine records the number of the IOs currently processed by each CPU, and selects the CPU with the minimum IO processing number to process the IO currently to be processed.
Claims (6)
1. An SSD master internal load balancing system, comprising:
host interface: the host computer is responsible for receiving commands and data from the host computer, and simultaneously returning responses to the host computer and transmitting data to the host computer;
NFC: the device is responsible for finishing command interaction and data transmission between the SSD master control and the NAND Flash;
IO command equalization Engine: the system is responsible for distributing an IO command request from the host interface to the CPU for processing and simultaneously forwarding a response from the CPU to the host interface; the IO command balancing engine includes a CMD Slot: the CMD context information is used for matching the command request with the response; CMD context information, namely IO command context;
a plurality of CPUs: the system is used for scheduling and processing the IO commands distributed by the IO command balancing engine and controlling data transmission.
2. The SSD master internal load balancing system of claim 1, wherein the IO command balancing engine further comprises:
a processing engine: the system is used for managing CPU resources and CMD Slot resources and selecting a proper CPU for the IO command;
IO Router: the CPU is used for selecting a target CPU for the IO command according to the processing engine and distributing the IO command to the corresponding CPU through the multiplexer/demultiplexer;
multiplexer/demultiplexer: the system is used for distributing the IO commands to different CPUs and multiplexing the IO responses processed by the CPUs to the processing engine for further processing.
3. The SSD master internal load balancing system of claim 2, wherein the process of the IO command balancing engine distributing the IO commands comprises:
1) after receiving the IO command, judging whether CMD Slot resources still exist, and if so, entering a step 2); otherwise, ending the processing, namely suspending the current IO command;
2) traversing the IO command being processed recorded by the next CMD Slot;
3) if the IO command to be processed conflicts with the currently processed IO command recorded in the CMD Slot in the LBA access address, selecting the CPU corresponding to the CMD Slot to process the current IO command to be processed, simultaneously allocating a new CMD Slot resource to store the context of the current IO command, and entering step 4); otherwise, distributing new CMD Slot resources to the IO command to be processed currently, selecting the CPU with the least number of IO commands to be processed currently to process the IO command to be processed currently, and entering step 4);
4) forwarding the IO command to be processed to the selected CPU through the IO Router;
5) recording context information of the current IO command in the CMD Slot, and adding 1 to the number of the IO commands processed by the selected CPU;
6) and (6) ending.
4. The SSD master internal load balancing system of claim 2, wherein the step of multiplexing the response processed by each CPU to the processing engine for further processing comprises:
1) the multiplexer/demultiplexer receives the IO response sent by the CPU;
2) subtracting 1 from the number of IO processes of the corresponding CPU, and releasing CMD Slot resources corresponding to the IO responses;
3) the processing engine forwards the IO response to the host interface and judges whether a pending IO command to be processed is in the waiting queue; if yes, reading and processing the IO command in the waiting queue, and entering the step 4); otherwise, entering step 4);
4) and (6) ending.
5. A method for balancing SSD master internal load by using the system of any one of claims 1 to 4, the method is mainly implemented by the following steps: IO commands are distributed among CPUs through an IO command balancing engine, each CPU independently processes the whole IO commands distributed to the CPU, and the CPUs are not mutually interacted.
6. The method of claim 5, wherein the method for ensuring that CPUs do not interact with each other comprises the steps of:
1) if the access LBA address conflict exists between the current IO command to be processed and the currently processed IO command recorded by the CMD Slot, allocating a new CMD Slot resource to the current IO command to be processed, selecting a CPU corresponding to the current CMD Slot resource to process the current IO command to be processed, and simultaneously allocating a new CMD Slot resource to store the current IO command context, and entering step 2); otherwise, distributing new CMD Slot resources to the IO command to be processed currently, selecting the CPU with the least number of IO commands to be processed currently to process the IO command to be processed currently, and entering the step 2);
2) and forwarding the IO command to be processed currently to the selected CPU for processing.
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| KR101486987B1 (en) * | 2008-05-21 | 2015-01-30 | 삼성전자주식회사 | Semiconductor memory device including nonvolatile memory and commnand scheduling method for nonvolatile memory |
| US8069300B2 (en) * | 2008-09-30 | 2011-11-29 | Micron Technology, Inc. | Solid state storage device controller with expansion mode |
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