CN106597388A - FGPA realization method for one-dimensional detection of averaging slide windows on two sides - Google Patents
FGPA realization method for one-dimensional detection of averaging slide windows on two sides Download PDFInfo
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- CN106597388A CN106597388A CN201611045228.8A CN201611045228A CN106597388A CN 106597388 A CN106597388 A CN 106597388A CN 201611045228 A CN201611045228 A CN 201611045228A CN 106597388 A CN106597388 A CN 106597388A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/28—Details of pulse systems
- G01S7/285—Receivers
- G01S7/292—Extracting wanted echo-signals
- G01S7/2923—Extracting wanted echo-signals based on data belonging to a number of consecutive radar periods
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
Abstract
The invention provides a FGPA realization method for one-dimensional detection of averaging slide windows on two sides. The method comprises the following steps of: 1) inputting an original data and setting radar working parameters; 2) treating the original data inputted in the step 1); and 3) comparing and verifying a treating result acquired in the step 2). According to the invention, the problems of high working repetition frequency, more processing points and insufficient processing speed of a DSP (Digital Signal Processor) chip of a radar signal processing system can be effectively solved; the FGPA design is used for realizing the one-dimensional detection of averaging the slide windows on two sides; a practical project has verified that the effect is excellent, practicability and universality are higher and the method has a certain guiding significance for the future similar design.
Description
Technical field
The present invention relates to radar signal processing field, and in particular to a kind of both sides sliding window is averaged the FPGA realities of one-dimensional detection
Existing method.
Background technology
For Radar Signal Processing System of today, the processing framework of DSP, most of radar signals are generally added using FPGA
Process to adopt and first do distance to pulse pressure, then do the processing mode for carrying out two-dimensional detection after orientation pulse pressure is accumulated again, FPGA does
Data are passed to DSP by complete distance to after pulse pressure and accumulation, and by DSP detection and follow-up process are carried out.
But very fast for the radar in the present invention, antenna rotation rate, wave beam is narrower, and the result after accumulation can't detect target,
So the method that one-dimensional detection is directly carried out to pulse pressure result using adjusting the distance, is obtained in that preferable Detection results.For doing
The Radar Signal Processing System of two-dimensional detection algorithm, tens even hundreds of radar repetition periods carry out one-time detection, detect
Cycle is longer, relatively low for the rate request that algorithm is realized；And for the present invention in one-dimensional detection, need each repetition period
One-time detection is carried out, detection cycle is short, detection points are big, for the requirement of processing speed is far above two-dimensional detection.With FPGA
The continuous development of designing technique and the continuous expansion of chip-scale, realizing that sophisticated signal Processing Algorithm becomes one kind with FPGA must
Right trend, compared to DSP, FPGA has very big advantage in speed and the aspect of resource two.
Due to large scale integrated circuit, the particularly high speed development of PLD FPGA, radar signal of today
Processing system, more and more carries out the signal processing Interface Controller and algorithm design of complexity using FPGA.FPGA has inside
Resource is more, stable and reliable in work, fireballing advantage, for the concrete condition in the present invention, if realizing one-dimensional inspection using DSP
Survey, there is following difficulty：Each repetition period will adjust the distance and carry out one-dimensional detection to pulse pressure result, and detection cycle is short, data
Amount is excessive, and such substantial amounts of data are detected in the so short time, also to carry out other data processings simultaneously, processes
Speed is that DSP is difficult to bear.
The content of the invention
For the problems referred to above, the present invention is according to one-dimensional detection ultimate principle, there is provided a kind of both sides sliding window is made even homogeneous position inspection
The FPGA implementation method of survey, the method effectively solve carry out one detection Radar Signal Processing System detection cycle it is short,
Detection data amount contradiction inadequate with dsp chip processing speed greatly, through checking in concrete engineering, actually detected result with
Theoretical simulation result is consistent, and indices have reached the requirement of Radar Signal Processing, and effect is preferable.
According to an aspect of the invention, there is provided a kind of both sides sliding window is averaged the FPGA implementation method of one-dimensional detection,
Methods described includes：
Step 1：Input initial data, and radar running parameter is configured：
The step according to one-dimensional detection ultimate principle, with matlab guinea pig signal processing real work flow processs, by original
Beginning data input, and the setting of parameter is operated to radar according to practical situation.
Step 2：The initial data of step 1 input is processed；
Step 3：Contrast verification is carried out to the result of step 2：
The step is contrasted the result of FPGA with theoretical simulation result, so as to verify the correct of FPGA design
Property.
Further, in the step 1, the initial data of input is baseband signal, and the radar running parameter of setting has
Body is as follows：Sample rate is 40MHz, and baseband signal bandwidth includes 20MHz and two kinds of 10MHz, and the signal of wherein bandwidth 20MHz includes
Two kinds of 2us pulsewidths and 20us pulsewidths, the signal pulsewidth of bandwidth 10MHz is 80us.
Further, in the step 2, the initial data of step 1 input is processed specially：
Initial data to being input into enters row distance pulse pressure computing, and the data after pulse pressure of then adjusting the distance computing carry out one-dimensional inspection
Survey.
Further, the data after pulse pressure of adjusting the distance computing carry out one-dimensional detection and are specifically divided into four steps：2.1st, to away from
Data after pulse pressure computing carry out modulus process, and 2.2, background cell data accumulation is carried out to the data after modulus process,
2.3rd, the result of background cell data accumulation is processed so as to obtain fiducial value, 2.4, modulus are processed after modulus value and institute
State fiducial value to be compared.
Further, 2.1, the data after pulse pressure of adjusting the distance computing carry out modulus and process to be specially：
It is 32 floating-point formats to have carried out the data after pulse pressure computing, and each data is each 32 floating-points of real part imaginary part
Number；Need to carry out following three step in FPGA：First real part and imaginary part carry out respectively power operation, then real part and imaginary part power
Result be added, finally to be added result carry out evolution, the result for obtaining is 32 floating point real numbers, i.e. each pulse pressure
The modulus value of data.
Further, after modulus are processed, the modulus value of each the pulse pressure data for obtaining is stored in ram and is kept in so as in step
It is compared with fiducial value in 2.4.
Further, 2.2, carry out background cell data accumulation to the data after modulus process to be specially：By each point back of the body
The data of scape unit carry out additive operation, because one has 8192 point datas, need computing the 1st successively to the 8th point
Data sum, the 2nd to the 9th point data and the 3rd to the 10th point data sum, until the 8185th to the 8192nd point data
Sum, totally 8185 value of calculation；To enable FPGA to realize stream treatment, following methods are taken：Add due to needing to do 3 steps altogether
Method, therefore call 3 adders；The input of first adder is respectively modulus value and original after the modulus of original 8192
Modulus value after one clock cycle of 8192 modulus value time delays beginning, so both additions can be obtained by the 1st modulus value and the 2nd mould
Sum of value, the 2nd modulus value and the 3rd modulus value and, until the 8191st modulus value and the 8192nd modulus value and, totally 8191
Value；By this principle, the input of second adder is respectively 8191 values and the output 8191 of first adder output
Value after value two clock cycle of time delay, so both additions can be obtained by the sum of the 1st to the 4th modulus value, the 2nd to the 5th
The sum of modulus value, until the sum of the 8189 to 8192nd modulus value, totally 8189 are worth；The input of the 3rd adder is respectively
8189 values of two adders output and the values of 8189 value four clock cycle of time delay are exported, so both additions just can be with
Obtain the sum of the 1st to the 8th modulus value, the sum of the 2nd to the 9th modulus value, until the sum of the 8185 to 8192nd modulus value, totally 8185
Individual value of calculation；
Because the data at two ends only have unilateral background cell in 8192 point datas, middle data just have both sides background list
Unit, the background cell of first point is remove the 20 point protection units in right side the 22nd point to 29 points, until the 29th point just has
The background cell of both sides, similar, the only unilateral background cell of the point data of right-hand member 28 and the point data of left end 28；
Take following methods ask for each point background cell and：Recall an adder, input is respectively above-mentioned the
8185 values that three adders are obtained and by the value after this 49 clock cycle of 8185 value time delays, the result for obtaining is cast out
In front and back each 21 values, just obtain 8192 values, the background cell data of the as the 1st to the 8192nd point data it is cumulative with.
Further, 2.3, the result to background cell data accumulation is processed is specially so as to obtain fiducial value：It is right
Background cell data accumulation result averaged, is then multiplied, so as to obtain fiducial value with detection threshold.
Further, 2.4, the modulus value after modulus is compared specially with the fiducial value：Call inside FPGA
Comparator, two inputs of comparator are respectively 8192 points of modulus value and corresponding fiducial value；If modulus value is more than or equal to and compares
Value, then retain modulus value；Otherwise, if modulus value is less than fiducial value, the modulus value of the position is replaced with 0；The modulus value pair being retained
The data answered are the target data being detected.
According to above-mentioned technical proposal, beneficial effects of the present invention include：
1st, the present invention is based on one-dimensional Cleaning Principle, according to project reality, targetedly devises suitable this project
The both sides sliding window detection method that is averaged, and the predetermined design with FPGA programming realizations, by theoretical simulation, FPGA code work(
Can emulate and board level test, demonstrate the correctness of the design, index has reached requirement, completes to bandwidth 20MHz, pulsewidth
2us, bandwidth 20MHz, pulsewidth 20us, bandwidth 10MHz, the one-dimensional detection of tri- kinds of baseband signals of pulsewidth 80us.
2nd, the present invention effectively solves Radar Signal Processing System work repetition greatly, processes at many and dsp chip of counting
The contradiction of reason underspeed, with FPGA design the one-dimensional detection that both sides sliding window is averaged is realized, and is entered in Practical Project
Checking is gone, has achieved good effect, with stronger practicality and versatility, later similar designs have been had certain
Directive significance.
Description of the drawings
Fig. 1 is bandwidth 20MHz, pulsewidth 2us baseband signal pulse pressure result；
Fig. 2 is bandwidth 20MHz, the one-dimensional testing result of pulsewidth 2us baseband signal；
Fig. 3 is bandwidth 20MHz, pulsewidth 2us baseband signal FPGA functional simulation result；
Fig. 4 is bandwidth 20MHz, pulsewidth 20us baseband signal pulse pressure result；
Fig. 5 is bandwidth 20MHz, the one-dimensional testing result of pulsewidth 20us baseband signal；
Fig. 6 is bandwidth 20MHz, pulsewidth 20us baseband signal FPGA functional simulation result；
Fig. 7 is bandwidth 10MHz, pulsewidth 80us baseband signal pulse pressure result；
Fig. 8 is bandwidth 10MHz, the one-dimensional testing result of pulsewidth 80us baseband signal；
Fig. 9 is bandwidth 10MHz, pulsewidth 80us baseband signal FPGA functional simulation result；
Figure 10 is method of the present invention flow chart.
Specific embodiment
The one-dimensional detection ultimate principle that the present invention is averaged according to both sides sliding window, has built the phantom of system, and
The design in FPGA is realized.Through the actual verification in some emphasis models, preferable effect is achieved, with stronger reality
With property and versatility, there is very strong directive significance to later similar designs.
Fig. 1～3 are the results to bandwidth 20MHz, pulsewidth 2us baseband signal, and wherein Fig. 1 and Fig. 2 is respectively theoretical
On pulse pressure and testing result, Fig. 3 is the functional simulation result of FPGA design；Fig. 4～6 are to bandwidth 20MHz, pulsewidth 20us base
The result of band signal, wherein Fig. 4 and Fig. 5 are respectively theoretic pulse pressure and testing result, and Fig. 6 is the function of FPGA design
Simulation result；Fig. 7～9 are the results to bandwidth 10MHz, pulsewidth 80us baseband signal, and wherein Fig. 7 and Fig. 8 is respectively reason
By upper pulse pressure and testing result, Fig. 9 is the functional simulation result of FPGA design.Method bag in the specific embodiment of the invention
Include：Step 1：Input initial data, and parameter is configured；Step 2：Input data is processed；Step 3：To design
Carry out contrast verification.
Below just with reference to Fig. 1 to Fig. 9 to said method in each step be specifically introduced.
Step 1：Input initial data, and parameter is configured
In the step 1, the data of input are baseband signal, arrange radar running parameter as follows：Sample rate 40MHz,
Baseband signal bandwidth is 20MHz, and two kinds of 10MHz, the wherein signal of bandwidth 20MHz include two kinds of 2us pulsewidths and 20us pulsewidths,
The signal pulsewidth of 10MHz is 80us, altogether 3 kinds of signals.
Parameter setting is finished, and according to the facilities of parameter, the design of row distance pulse pressure is entered first.The present invention is apart from pulse pressure point
Number is 8192 points.Row distance pulse pressure is entered to the data in sampling gate, because pulse pressure points are 8192 points, data in sampling gate
The data of polishing to 8192 points are carried out first FFT computings by the part zero padding less than 8192 points, are then multiplied by arteries and veins to FFT result
Pressure matching factor, then carries out IFFT computings, and finally IFFT results are normalized, and obtains 8192 pulse pressure results,
Floating-point format, real part imaginary part is each 32.This result is the input of one-dimensional detection in the present invention.For the arteries and veins of 3 kinds of signals
Pressure processing mode is identical.
Fig. 1, Fig. 4 and Fig. 7 are respectively the result after three kinds of signal pulse pressure modulus, intercept Partial Pulse Compression data, are easy to observation,
Transverse axis is pulse pressure points, and vertical pivot is pulse pressure result amplitude.8192 point data amplitudes after pulse pressure are not 0, so needing to arteries and veins
Pressure result is detected, will retained more than the detection of the pulse pressure result of thresholding, less than the pulse pressure result tax 0 of thresholding.With most of thunder
Up to signal processing unlike, the present invention has only carried out a step pitch descriscent pulse pressure, the accumulation without orientation, so referred to as one-dimensional
Detection.
Step 2：Input data is processed
In the step 2, the pulse pressure result to being input into carries out one-dimensional detection, and heretofore described one-dimensional detection is adopted
The method being averaged with both sides sliding window：8192 pulse pressure result pointwises are detected, the pulse pressure result at two ends only has one side
There are protection location and background cell, 20 points of protection location, the back of the body in protection location and background cell, middle pulse pressure result both sides
8 points of scape unit；Accumulating operation is carried out to the background cell of each pulse pressure result, after accumulated value is averaging again with detection door
Limit is multiplied, and the result for obtaining is compared with original pulse pressure amplitude, if original pulse pressure amplitude is more than or equal to the point back of the body
The result of scape unit, then respective point be detected, retain original amplitude, if original pulse pressure amplitude be less than the background cell
Result, then respective point assigned 0.This is the one-dimensional Cleaning Principle that both sides sliding window is averaged.
Further, the data after pulse pressure of adjusting the distance computing carry out one-dimensional detection and are specifically divided into four steps：2.1st, to away from
Data after pulse pressure computing carry out modulus process, and 2.2, background cell data accumulation is carried out to the data after modulus process,
2.3rd, the result of background cell data accumulation is processed so as to obtain fiducial value, 2.4, modulus are processed after modulus value and institute
State fiducial value to be compared.
Realize that this design includes 4 steps with FPGA in the present invention, using FPGA streamlined process is carried out.1st step is to ask
Mould process, carries out respectively power operation to the real part and imaginary part of pulse pressure result first, and then real part enters with the result of imaginary part power
Row is added, and finally the result to being added carries out evolution, and the result for obtaining is 32 floating point real numbers, the i.e. mould of each pulse pressure data
Value.Each step is both needed to call corresponding IP kernel, completes in FPGA internal arithmetic clock down-flow waters, and the result of computing will carry out two steps
Process, good modulus value is stored in ram and is kept in by the first step as initial data, and second step carries out data to ask for background cell
The process of meansigma methodss, two-step pretreatment for same group of data, totally 8192 points.
2nd step is background cell data accumulation, the data of each point background cell is carried out into additive operation, because one is total
8192 point datas, so need computing the 1st successively to the 8th point data sum, the 2nd to the 9th point data and, the 3rd to the
10 point data sums, until the 8185th to the 8192nd point data sum, totally 8185 value of calculation.3 are called in FPGA
Adder core, the input exported as next adder of each adder, first adder is calculated the 1st modulus value
With the 2nd modulus value, the 2nd modulus value and the 3rd modulus value, until the 8191st modulus value and the 8192nd modulus value and, totally 8191
Individual value；Second adder is calculated the sum of the 1st to the 4th modulus value, the sum of the 2nd to the 5th modulus value, until the 8189th arrives
The sum of 8192 modulus value, totally 8189 are worth；3rd adder is calculated the sum of the 1st to the 8th modulus value, the 2nd to the 9th mould
The sum of value, until the sum of the 8185 to 8192nd modulus value, totally 8185 value of calculation.Following methods are finally taken to ask for each point
Background cell and.An adder core is recalled, input is respectively 8185 results that above-mentioned 3rd adder is obtained, then
This 8185 value 49 clock cycle of time delay are input into as another, the result for obtaining casts out each 21 values in front and back, just
To 8192 value, the background cell of the as the 1st to the 8192nd point data and.
3rd step is multiplied for accumulation result with detection threshold, and detection threshold value is encapsulated by host computer according to practical situation, sends
To FPGA, FPGA calls the multiplier core of inside, and good background cell data and carries out a step multiplication, and the result for obtaining is just
Can compare with being previously mentioned the original modulus value being temporarily stored in ram and carrying out detection.Wherein, the detection threshold value is needed for actual
The detection threshold value wanted and the product of averaged coefficient.Due to having carried out encapsulation process herein, two steps are synthesized into a step, because
The step of this saves process and process time.
4th step compares for data, and two inputs for calling FPGA internal comparator IP kernels, comparator are respectively at 8192 points
Modulus value and corresponding fiducial value；If modulus value is more than or equal to fiducial value, retain modulus value；Otherwise, if modulus value is less than fiducial value,
Then the modulus value of the position is replaced with 0；The corresponding data of modulus value being retained are the target data being detected.
FPGA code is write using Verilog language, after the completion of written in code, test file is write, QuestaSim is used
6.5a software carries out functional simulation, functional simulation result such as Fig. 3, Fig. 6 for obtaining, shown in Fig. 9.
Fig. 3, Fig. 6, Fig. 9 correspond to respectively 2us pulsewidths, 20us pulsewidths, the FPGA design emulation knot of three kinds of signals of 80us pulsewidths
Really.Wherein p_result_I is pulse pressure real part, and p_result_Q is pulse pressure result imaginary part, and p_result_valid is pulse pressure
As a result useful signal.Jiance_data_valid is the target data useful signal for detecting, and jiance_data is detection number
According to the target data being detected retains original pulse pressure result modulus value, and undetected part is directly assigned 0, jiance_loca and is
Test point position, is that the impact point for detecting is counted from 1 to 8192, jiance_num.
Step 3：Contrast verification is carried out to design
In the step 3, the functional simulation result after the completion of FPGA design is contrasted with notional result, Liang Zhejie
Fruit is consistent, it was demonstrated that the correctness of FPGA design.
The FPGA design simulation result of three kinds of signals is contrasted with notional result respectively.Pulsewidth 2us signal such as Fig. 2 and
Shown in Fig. 3, according to the notional result of Fig. 2, the 1999th in 8192 pulse pressure data to the 2003rd point is detected, and remaining point is assigned
0；According to the result that the FPGA design of Fig. 3 is obtained, the 1999th to the 2003rd point is detected, and remaining point is assigned 0, the target for detecting
Count as 5, it is identical with notional result.Pulsewidth 20us signal as shown in Figure 5 and Figure 6, according to the notional result of Fig. 5,
The the 1998th to the 2004th point in 8192 pulse pressure data is detected, and remaining point is assigned 0；Obtained according to the FPGA design of Fig. 6
As a result, the 1998th to the 2004th point is detected, and remaining point is assigned 0, and the target points for detecting are 7, complete with notional result
It is identical.Pulsewidth 80us signal as shown in Figure 8 and Figure 9, according to the notional result of Fig. 8, arrive by the 1996th in 8192 pulse pressure data
2006th point is detected, and remaining point is assigned 0；According to the result that the FPGA design of Fig. 9 is obtained, the 1996th to the 2006th point tested
Go out, remaining point is assigned 0, the target points for detecting are 11, identical with notional result.
It can be seen from the introduction of above-mentioned specific embodiment, the present invention is that one kind FPGA design realizes that both sides sliding window is made even
The one-dimensional method for detecting this Radar Signal Processing committed step, implementation process is simple, and is verified by actual tests, effect
Substantially, it is easy to accomplish；The invention is applied to majority carries out the Radar Signal Processing System of one-dimensional detection, can be according to disparity items
Concrete condition, require for different background cells and protection location, be packaged into the design module of parameter flexible and selectable, realize
The modularity of design and generalization, are substantially shorter the design cycle.
Above-mentioned specific embodiment is only used for explaining and illustrate technical scheme, but can not constitute will to right
The restriction of the protection domain asked.It will be apparent to those skilled in the art that doing any letter on the basis of technical scheme
New technical scheme, will fall under the scope of the present invention obtained from the deformation or replacement of list.
Claims (9)
1. a kind of both sides sliding window is averaged the FPGA implementation method of one-dimensional detection, it is characterised in that methods described includes：
Step 1：Input initial data, and radar running parameter is configured：
The step according to one-dimensional detection ultimate principle, with matlab guinea pig signal processing real work flow processs, by original number
According to input, and the setting of parameter is operated to radar according to practical situation；
Step 2：The initial data of step 1 input is processed；
Step 3：Contrast verification is carried out to the result of step 2：
The step is contrasted the result of FPGA with theoretical simulation result, so as to verify the correctness of FPGA design.
2. the method for claim 1, it is characterised in that in the step 1, the initial data of input is base band letter
Number, the radar running parameter of setting is specific as follows：Sample rate is 40MHz, and baseband signal bandwidth includes 20MHz and two kinds of 10MHz,
Wherein the signal of bandwidth 20MHz includes two kinds of 2us pulsewidths and 20us pulsewidths, and the signal pulsewidth of bandwidth 10MHz is 80us.
3. the method for claim 1, it is characterised in that in the step 2, enters to the initial data of step 1 input
Row process is specially：
Initial data to being input into enters row distance pulse pressure computing, and the data after pulse pressure of then adjusting the distance computing carry out one-dimensional detection.
4. method as claimed in claim 3, it is characterised in that it is concrete that the data after pulse pressure of adjusting the distance computing carry out one-dimensional detection
It is divided into four steps：2.1st, the data after pulse pressure of adjusting the distance computing carry out modulus process, and 2.2, the data after modulus process are entered
Row background cell data accumulation, 2.3, the result to background cell data accumulation processed so as to obtain fiducial value, 2.4, will
Modulus value after modulus process is compared with the fiducial value.
5. method as claimed in claim 4, it is characterised in that 2.1, the data after pulse pressure of adjusting the distance computing carry out modulus process
Specially：
It is 32 floating-point formats to have carried out the data after pulse pressure computing, and each data is each 32 floating numbers of real part imaginary part；
Need to carry out following three step in FPGA：First real part and imaginary part carry out respectively power operation, then real part and imaginary part power
As a result it is added, finally the result to being added carries out evolution, and the result for obtaining is 32 floating point real numbers, i.e. each pulse pressure number
According to modulus value.
6. method as claimed in claim 5, it is characterised in that after modulus process, by the modulus value of each the pulse pressure data for obtaining
It is stored in ram and keeps in be compared with fiducial value in step 2.4.
7. method as claimed in claim 4, it is characterised in that 2.2, background cell data are carried out to the data after modulus process
It is cumulative to be specially：The data of each point background cell are carried out into additive operation, because one has 8192 point datas, is needed
Successively computing the 1st is to the 8th point data sum, the 2nd to the 9th point data and, the 3rd to the 10th point data sum, until
8185th to the 8192nd point data sum, totally 8185 value of calculation；To enable FPGA to realize stream treatment, take with lower section
Method：Due to needing to do 3 step additions altogether, therefore call 3 adders；The input of first adder is respectively original
Modulus value after 8192 modulus and the modulus value after original one clock cycle of 8192 modulus value time delays, so both additions can
With obtain the 1st modulus value and the 2nd modulus value and, the 2nd modulus value and the 3rd modulus value and, until the 8191st modulus value and
The sum of the 8192nd modulus value, totally 8191 are worth；By this principle, it is defeated that the input of second adder is respectively first adder
8191 values for going out and the value after output two clock cycle of 8191 value time delays, so both additions can be obtained by the 1st and arrive
The sum of the 4th modulus value, the sum of the 2nd to the 5th modulus value, until the sum of the 8189 to 8192nd modulus value, totally 8189 are worth；3rd
The input of individual adder is respectively 8189 values of second adder output and output four clock weeks of 8189 value time delays
The value of phase, so both be added and can be obtained by the sum of the 1st to the 8th modulus value, the sum of the 2nd to the 9th modulus value, until the
The sum of 8185 to 8192 modulus value, totally 8185 value of calculation；
Because the data at two ends only have unilateral background cell in 8192 point datas, middle data just have both sides background cell, the
The background cell of one point is remove the 20 point protection units in right side the 22nd point to 29 points, until the 29th point just has both sides
Background cell, similar, the only unilateral background cell of the point data of right-hand member 28 and the point data of left end 28；
Take following methods ask for each point background cell and：An adder is recalled, input is respectively above-mentioned 3rd
8185 values that adder is obtained and by the value after this 49 clock cycle of 8185 value time delays, before and after the result for obtaining is cast out
Each 21 values, just obtain 8192 values, the background cell data of the as the 1st to the 8192nd point data it is cumulative with.
8. the method as any one of claim 4-7, it is characterised in that 2.3, the result to background cell data accumulation
Processed and be specially so as to obtain fiducial value：To background cell data accumulation result averaged, then with detection threshold
It is multiplied, so as to obtain fiducial value.
9. the method as any one of claim 4-8, it is characterised in that 2.4, compare the modulus value after modulus with described
Value is compared specially：Call the comparator inside FPGA, two inputs of comparator are respectively 8192 points of modulus value and right
The fiducial value answered；If modulus value is more than or equal to fiducial value, retain modulus value；Otherwise, if modulus value is less than fiducial value, the position
Modulus value with 0 replace；The corresponding data of modulus value being retained are the target data being detected.
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