CN106570230A

CN106570230A - Robinson filtering design method based on FPGA (Field Programmable Gate Array)

Info

Publication number: CN106570230A
Application number: CN201610919283.9A
Authority: CN
Inventors: 郑鑫
Original assignee: Luoyang Institute of Electro Optical Equipment AVIC
Current assignee: Luoyang Institute of Electro Optical Equipment AVIC
Priority date: 2016-10-21
Filing date: 2016-10-21
Publication date: 2017-04-19

Abstract

The invention relates to a Robinson filtering design method based on an FPGA (Field Programmable Gate Array). Six FIFO (First In First Out) memories are sequentially connected, input data indatabus is read out sequentially through the six FIFOs, each piece of clock input data and data read out by six FIFOs form seven rows of data in the same line and with adjacent images, seven pieces of data sequentially enter corresponding registers for comparing sizes, each clock generates the maximum value at the same moment, and compared with a current pixel value, a filter result is output. Robinson filtering achieved by the invention is in horizontal and vertical directions, the size is 7 by 7 pixels, and a template is 24 pixels at an edge; and all hardwares work in a pixel clock synchronous state, primary comparison of two register numerical values is only generated in each clock period, and clock frequency is favorably improved. The Robinson filtering design method has the characteristics of interface simplicity, real-time performance and universality and is suitably used for achieving a Robinson filter function in the FPGA.

Description

The method for designing that a kind of Robinson based on FPGA is filtered

Technical field

The invention belongs to electronic design technology, is related to the method for designing that a kind of Robinson based on FPGA is filtered.

Background technology

Robinson filtering is a kind of non-linear non-parameter type wave filter, also known as protection band filtering.Its formula is：

f_Robinson(i, j) denotation coordination (i, j) pixel Robinson filter result, f_pre(i, j) denotation coordination (i, j)

Pixel initial data, Z_iRepresent each pixel data of the template chosen.

Robinson filtering is usually used in the detection of Small object, it may be determined that the protection band of a size, internal information retain, Only filtering is compared with the pixel at edge.

In prior art, Robinson filtering belongs to theoretical research, although has been reported that and can realize in FPGA, but not See in open source literature, the practical situation of Robinson filtering can not be retrieved.

The content of the invention

Technical problem to be solved

In place of the deficiencies in the prior art, the present invention proposes the design that a kind of Robinson based on FPGA is filtered Method

Technical scheme

The method for designing that a kind of Robinson based on FPGA is filtered, it is characterised in that step is as follows：

Step 1：6 FIFO memories are set up, input data writes the 1st FIFO, read from the 1st FIFO and write the again 2 FIFO, read from the 2nd FIFO and write the 3rd FIFO again, and the rest may be inferred, until reading from the 6th FIFO；

Step 2：The same column data of adjacent 7 row of data formation image that each clock input data and 6 FIFO read, 7 Individual data sequentially enter correspondence depositor and compare size；

Step 3：Each clock produces 9 maximums, correspond to respectively the 1st row, the 7th row, the 1st row, the 2nd row, the 3rd row, the 4th Row, the 5th row, the 6th row, the 7th row；

Step 4：1st row of each clock generation synchronization, the 7th row, the 1st row, the maximum of the 7th row, with current picture Plain value compares, and exports filter result.

The Robinson is filtered into horizontal vertical direction, and size is 7 × 7 pixels, and template is 24 pixels at edge.

Beneficial effect

The method for designing that a kind of Robinson based on FPGA proposed by the present invention is filtered, using 6 FIFO memories according to Secondary connection, input data indatabus are read from 6 FIFO according to this, the data that each clock input data and 6 FIFO read The same column data of adjacent 7 row of image is formed, 7 data sequentially enter correspondence depositor and compare size, and each clock produces same The maximum at moment, is compared with current pixel value, exports filter result.The Robinson that the present invention is realized is filtered into level and hangs down Nogata is to size is 7 × 7 pixels, and template is 24 pixels at edge.Synchronous regime of whole hardware efforts in pixel clock, The one-level that each clock cycle only has 2 register values compares, and is conducive to improving clock frequency.

Interface of the present invention is simple, the characteristics of with real-time, versatility, it is adaptable to realize that in FPGA Robinson is filtered Function.

Description of the drawings

Fig. 1 is the main hardware structure schematic diagram of the present invention；

Fig. 2 is the corresponding relation figure of maximum value register and pixel.

Specific embodiment

In conjunction with embodiment, accompanying drawing, the invention will be further described：

The embodiment of the present invention：The Robinson of realization is filtered into horizontal vertical direction, and size is 7 × 7 pixels, and template is side 24 pixels of edge.

Synchronous regime of whole hardware efforts in pixel clock, each clock cycle only have the one-level of 2 register values Relatively.This hardware designs are conducive to being operated under higher clock frequency.

6 FIFO memories are sequentially connected, and input data indatabus writes the 1st FIFO, read from the 1st FIFO The 2nd FIFO is write again, is read from the 2nd FIFO and is write the 3rd FIFO again, the rest may be inferred, until reading from the 6th FIFO.

The same column data of adjacent 7 row of data formation image that each clock input data and 6 FIFO read, 7 data Sequentially enter correspondence depositor and compare size.Each clock produces 9 maximums, correspond to respectively the 1st row, the 7th row, the 1st row, the 2 row, the 3rd row, the 4th row, the 5th row, the 6th row, the 7th row.Each clock produce the 1st row of synchronization, the 7th row, the 1st row, the 7th The maximum of row, is compared with current pixel value, exports filter result.

Embodiment is designed using VHDL program：

VHDL program

This program is compiled in Xilinx ISE 13.2 and is passed through.

Claims

1. the method for designing that a kind of Robinson based on FPGA is filtered, it is characterised in that step is as follows：

Step 1：6 FIFO memories are set up, input data writes the 1st FIFO, read from the 1st FIFO and write the 2nd again FIFO, reads from the 2nd FIFO and writes the 3rd FIFO again, and the rest may be inferred, until reading from the 6th FIFO；

Step 2：The same column data of adjacent 7 row of data formation image that each clock input data and 6 FIFO read, 7 numbers Compare size according to correspondence depositor is sequentially entered；

Step 3：Each clock produces 9 maximums, correspond to respectively the 1st row, the 7th row, the 1st row, the 2nd row, the 3rd row, the 4th row, 5th row, the 6th row, the 7th row；

Step 4：1st row of each clock generation synchronization, the 7th row, the 1st row, the maximum of the 7th row, with current pixel value Relatively, export filter result.

2. according to claim 1, it is characterised in that：The Robinson is filtered into horizontal vertical direction, and size is 7 × 7 Pixel, 24 pixels of the template for edge.