CN1065659C - Plate and column type semiconductor package having heat sink - Google Patents
Plate and column type semiconductor package having heat sink Download PDFInfo
- Publication number
- CN1065659C CN1065659C CN96114083A CN96114083A CN1065659C CN 1065659 C CN1065659 C CN 1065659C CN 96114083 A CN96114083 A CN 96114083A CN 96114083 A CN96114083 A CN 96114083A CN 1065659 C CN1065659 C CN 1065659C
- Authority
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- China
- Prior art keywords
- heat sink
- flat board
- encapsulation
- lead
- plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 239000002184 metal Substances 0.000 claims abstract description 8
- 238000005538 encapsulation Methods 0.000 claims description 14
- 150000001875 compounds Chemical class 0.000 claims description 4
- 239000003822 epoxy resin Substances 0.000 claims description 4
- 229920000647 polyepoxide Polymers 0.000 claims description 4
- 239000011810 insulating material Substances 0.000 claims description 3
- 238000004513 sizing Methods 0.000 claims description 2
- 230000005764 inhibitory process Effects 0.000 claims 1
- 238000005452 bending Methods 0.000 abstract description 4
- 238000009434 installation Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 229920006336 epoxy molding compound Polymers 0.000 description 4
- 238000000465 moulding Methods 0.000 description 2
- 238000007634 remodeling Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- AOSZTAHDEDLTLQ-AZKQZHLXSA-N (1S,2S,4R,8S,9S,11S,12R,13S,19S)-6-[(3-chlorophenyl)methyl]-12,19-difluoro-11-hydroxy-8-(2-hydroxyacetyl)-9,13-dimethyl-6-azapentacyclo[10.8.0.02,9.04,8.013,18]icosa-14,17-dien-16-one Chemical compound C([C@@H]1C[C@H]2[C@H]3[C@]([C@]4(C=CC(=O)C=C4[C@@H](F)C3)C)(F)[C@@H](O)C[C@@]2([C@@]1(C1)C(=O)CO)C)N1CC1=CC=CC(Cl)=C1 AOSZTAHDEDLTLQ-AZKQZHLXSA-N 0.000 description 1
- 229940126657 Compound 17 Drugs 0.000 description 1
- 229940125898 compound 5 Drugs 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
- H01L21/4882—Assembly of heatsink parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
An improved plate and column type semiconductor package has a heat sink embedded in a plate, which prevents bending of leads or paddle. The plate includes a plurality of leads and a heat sink which are embedded therein, whereby the mounting of the semiconductor package on the printed circuit board is made easier. A semiconductor chip is attached to the heat sink of the plate and a plurality of metal wires electrically connects a plurality of the leads of the plate and the semiconductor chip.
Description
The present invention relates to a kind of semiconductor packages, particularly a kind of have a heat sink plate semiconductor packages.
Quad-flat-pack (QFP) is a kind of semiconductor packages, and Fig. 1 shows the structure of this conventional quad-flat-pack.This flat packaging comprises: semiconductor chip 3; The installation sheet 2 of semiconductor chip 3 is installed on it; Lead frame 1 with many go between 1A and 1B of the both sides that are positioned at installation sheet 2; And the lead-in wire 1A of electric connecting wire framework 1 and the many metal connecting lines 4 of semiconductor chip 3.Epoxy molding compound 5 basic sealed lead frames 1, and have predetermined thickness.The outer lead 1B that above-mentioned lead-in wire 1A and 1B are divided into lead 1A and stretch out from the epoxy molding compound.
The manufacture method of conventional semiconductor packages comprises the following steps: the first step, forms the lead frame 1 that comprises lead-in wire and installation sheet 2; In second step, chip 3 is installed on the installation sheet 2 of lead frame 1; The 3rd step, with many metal connecting lines 4, electric connecting wire framework 1 and semiconductor chip 3; The 4th step is with moulded resin compound sealed lead frame 1.After this, order is carried out pre-shaping step and forming step.Then semiconductor packages is installed on the printed circuit board (PCB), when giving the semiconductor chip making alive, just can be with information stores in wherein, and therefrom read these information.
Yet, because installation sheet 2 can be because of some generation inclination of pressure of epoxy resin compound in the molding process process, so conventional semiconductor packages is unsatisfactory.Because lead-in wire reaches the outside behind molding process, lead-in wire can be easy to bending because of the external impact force that adds thereon.Therefore, the reliability decrease of semiconductor packages.
In addition, be difficult in the semiconductor packages of accurately aiming at and be equipped with the many lead-in wires that stretch out on the printed circuit board (PCB).And when being added to voltage on the chip, at the semiconductor chip duration of work, the temperature of semiconductor packages rises, and the heat that produces owing to the temperature rising can not be dispersed into the outside effectively, so can cause incorrect work of chip and mistake.
The purpose of this invention is to provide a kind of heat sink plate semiconductor packages that has, can prevent to go between or the bending of installation sheet.
Another object of the present invention provides a kind of heat sink plate semiconductor packages that has, and can easily install on printed circuit board (PCB).
A further object of the present invention provides a kind of heat sink plate semiconductor packages that has, and can prevent owing to heat increases the incorrect work that causes and effectively distributes the heat that produces in the semiconductor packages.
A further object of the invention is to boost productivity by reducing manufacturing technology steps.
Can partly realize these and other advantage by the first embodiment of the present invention, this embodiment is one and has heat sink plate semiconductor packages, comprising: wherein be embedded with many lead-in wires and heat sink flat board; Attached to the semiconductor chip on flat board heat sink; Be used for the many metal connecting lines that lead-in wire is electrically connected with semiconductor chip with flat board; And the epoxy molding compound of seal plate predetermined portions.
Having heat sink plate semiconductor packages according to another embodiment of the present invention comprises: wherein be embedded with many lead-in wires and a heat sink cylindricality flat board, wherein surperficial on the lower surface direction from it, be formed with the groove of desired depth and pre-sizing; Attached to the semiconductor chip on flat board heat sink; Be used for the many metal connecting lines that lead-in wire is electrically connected with semiconductor chip with flat board; And be added to lid on the dull and stereotyped upper surface.
Below explanation can partly show other advantage of the present invention, purpose and other characteristics, and those skilled in the art by following test or can clearer these advantages of the present invention by putting into practice the present invention, purpose and characteristics.Appended claims specifically noted scheme can realize purpose of the present invention and obtain advantage of the present invention.
Describe the present invention below with reference to accompanying drawings in detail, identical mark is represented identical parts in each accompanying drawing:
Fig. 1 is the longitudinal sectional drawing of conventional semiconductor packages;
Fig. 2 is the perspective view of whole column frame of the present invention and encapsulation base;
Fig. 3 is the perspective view of the heat sink plate semiconductor packages of having of the first embodiment of the present invention;
Fig. 4 is the perspective view of the heat sink plate semiconductor packages of having of the second embodiment of the present invention; And
Fig. 5 is the perspective view of the heat sink plate semiconductor packages of having of the third embodiment of the present invention.
Improved plate and column type semiconductor package be equipped with one heat sink, it can more easily dissipate the heat that produces in the semiconductor packages.With wherein being embedded with many lead-in wires and heat sink whole column frame, make semiconductor packages, can improve the productivity ratio of semiconductor packages.Plate encapsulation base scales off from whole column frame at regular intervals.
Fig. 2 shows the flat board of whole column frame of the present invention and cutting-out.As shown in the drawing, whole column frame 10 comprises: the cylindrical bodies 11 that predetermined length (l) is arranged; Be buried in the cylindricality heat sink 13 of the core of main body 11; And many lead-in wires 12 that are provided with at heat sink 13 periphery.Heat sink 13 are exposed to the upper surface and the lower surface of main body 11, and the predetermined portions of lead-in wire 12 is exposed to the surface of main body 11 with predetermined thickness (d).In the figure, chain-dotted line is represented the cutting part of main body 11.
Column type main body 11 is generally made by insulating material.Cylindrical bodies 11 is made shape square or that other is suitable, for example circular.Obviously, the present invention also can adopt other shape.Cut this integral body column frame 10 at the predetermined space place, for example at 1mm, 1.5mm and 2.0mm place.The whole column frame 10 that downcuts becomes flat board, is used to make semiconductor packages.Many lead-in wires 12 that are buried in the whole column frame 10 also are buried in the whole column frame 10 of cutting-out.The upper and lower and heat sink 13 of lead-in wire 12 all is exposed on the surface of main body 11.
Fig. 3 represents the plate semiconductor packages that having of the first embodiment of the present invention is heat sink.As shown in the drawing, semiconductor chip 15 is installed on heat sink 13, with metal connecting line 14 electric bond semiconductor chips 15 and many lead-in wires 12.The molded line of label 16 expressions.By the sealing and the curing of epoxy molding compound, the top (not shown) of seal plate 11b.
Fig. 4 represents the plate semiconductor packages that having of the second embodiment of the present invention is heat sink.As shown in the drawing, by grinding or the top predetermined position of the dull and stereotyped 11B that polishing scales off from whole column frame 10, form groove 11A.After this, carry out described semiconductor chip mounting process of previous embodiment and wire bonding technique.With epoxy resin compound 17 seal groove 11A, then form semiconductor packages, thereby can make the semiconductor packages thinner than the first embodiment of the present invention.
Fig. 5 represents the plate semiconductor packages that having of the third embodiment of the present invention is heat sink.With the epoxy resin compound in lid 11C replacement the foregoing description.Sheet is cut whole column frame 10 just can obtain covering 11C.There is difference in thickness to a certain degree between dull and stereotyped 11B and lid 11C.
In addition, in another example of the present invention, can make integral post shape frame be connected (not shown), or in another embodiment, the lower surface of integral post shape frame directly is connected with the lower surface of printed circuit board (PCB) with the lower surface of substrate figure.
After being installed to the semiconductor packages that said structure is arranged on the printed circuit board (PCB), when giving the semiconductor packages making alive, the semiconductor chip work in the semiconductor packages, thus from chip, read predetermined information and predetermined information is write chip.
Of the present invention have heat sink plate and column type semiconductor packages can prevent the bending that goes between.In addition, because outside many lead-in wires and upper and lower surface plate or the column type semiconductor packages be exposed to, so chip can more easily be installed on substrate.In addition, can realize laminate-type structure, so maintenance easily.
Since the heat sink upper and lower surface that is exposed to flat board or cylindricality semiconductor packages, thus can more effectively be dispersed into the outside to the heat in the encapsulation, so can avoid the incorrect work of chip.Compare with conventional semiconductor package fabrication, can reduce manufacturing process, reduce manufacturing cost, boost productivity.
Although disclose the preferred embodiments of the present invention in order to illustrate, those skilled in the art can make various remodeling, additional and replacement to the present invention under the situation that does not break away from scope and spirit essence described in the appended claims of the present invention.
The foregoing description only is illustrative, does not limit the present invention.The semiconductor packages that can easily the solution of the present invention be used for other type.Those of ordinary skill in the art can be used for instruction of the present invention other device that those requirements were easier to and made more simply semiconductor packages.Explanation of the present invention is just illustrative, not the scope of requirement for restriction book.Those skilled in the art can make many replacements, remodeling and variation to the present invention.
Claims (13)
1. one kind has heat sink plate semiconductor packages, comprising:
Wherein be embedded with many lead-in wires and heat sink flat board;
Attached to the semiconductor chip on flat board heat sink;
Be used for the many metal connecting lines that lead-in wire is electrically connected with semiconductor chip with flat board; And
The epoxy resin film inhibition and generation compound of seal plate predetermined portions.
2. encapsulation as claimed in claim 1 is characterized in that: described flat board is made by insulating material.
3. encapsulation as claimed in claim 1 is characterized in that: described flat board has circular surface.
4. encapsulation as claimed in claim 1 is characterized in that: described flat board has square face.
5. encapsulation as claimed in claim 1 is characterized in that: described many lead-in wires and the described heat sink dull and stereotyped upper and lower surface that is exposed to.
6. encapsulation as claimed in claim 5 is characterized in that: described lead-in wire is exposed to dull and stereotyped side.
7. encapsulation as claimed in claim 1 is characterized in that: described flat board is included in from it the groove that the surface has desired depth and size on the direction of lower surface.
8. one kind has heat sink plate semiconductor packages, comprising:
Wherein be embedded with many lead-in wires and a heat sink cylindricality flat board, wherein, be formed with the groove of desired depth and pre-sizing surperficial on the direction of lower surface from it;
Attached to the semiconductor chip on heat sink;
The many metal connecting lines that lead-in wire is electrically connected with semiconductor chip with flat board; And
Be added to the lid on the dull and stereotyped upper surface.
9. encapsulation as claimed in claim 8 is characterized in that: described flat board is made by insulating material.
10. encapsulation as claimed in claim 8 is characterized in that: described flat board has circular surface.
11. encapsulation as claimed in claim 8 is characterized in that: described flat board has square face.
12. encapsulation as claimed in claim 8 is characterized in that: described many lead-in wires and the described heat sink dull and stereotyped upper and lower surface that is exposed to.
13. encapsulation as claimed in claim 12 is characterized in that: described lead-in wire is exposed to dull and stereotyped side.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950067332A KR100206880B1 (en) | 1995-12-29 | 1995-12-29 | Culumn type package, having heatsink |
| KR67332/1995 | 1995-12-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1156903A CN1156903A (en) | 1997-08-13 |
| CN1065659C true CN1065659C (en) | 2001-05-09 |
Family
ID=19447659
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN96114083A Expired - Lifetime CN1065659C (en) | 1995-12-29 | 1996-12-26 | Plate and column type semiconductor package having heat sink |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2819282B2 (en) |
| KR (1) | KR100206880B1 (en) |
| CN (1) | CN1065659C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7265167B2 (en) | 2002-11-12 | 2007-09-04 | Nitto Denko Corporation | Epoxy resin composition for semiconductor encapsulation, and semiconductor device using the same |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI233188B (en) | 2003-10-07 | 2005-05-21 | United Microelectronics Corp | Quad flat no-lead package structure and manufacturing method thereof |
| CN100369241C (en) * | 2003-10-13 | 2008-02-13 | 联华电子股份有限公司 | Packaging structure of cubic flat pin-free type chips and packaging process thereof |
| CN102437824B (en) * | 2011-12-05 | 2015-03-11 | 北京大学 | Direct-cooling type high integrated level charge sensitive pre-amplifier |
| CN105914191B (en) * | 2016-06-20 | 2018-03-16 | 深圳市宏钢机械设备有限公司 | A kind of integrated antenna package of water-cooling |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0545007A1 (en) * | 1991-11-29 | 1993-06-09 | STMicroelectronics S.r.l. | A semiconductor device structure having a heat-sink and a plastics body, and highly reliable means of electrical connection to the heat-sink |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2612455B2 (en) * | 1987-09-30 | 1997-05-21 | イビデン株式会社 | Substrate for mounting semiconductor elements |
-
1995
- 1995-12-29 KR KR1019950067332A patent/KR100206880B1/en not_active IP Right Cessation
-
1996
- 1996-12-24 JP JP8342950A patent/JP2819282B2/en not_active Expired - Fee Related
- 1996-12-26 CN CN96114083A patent/CN1065659C/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0545007A1 (en) * | 1991-11-29 | 1993-06-09 | STMicroelectronics S.r.l. | A semiconductor device structure having a heat-sink and a plastics body, and highly reliable means of electrical connection to the heat-sink |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7265167B2 (en) | 2002-11-12 | 2007-09-04 | Nitto Denko Corporation | Epoxy resin composition for semiconductor encapsulation, and semiconductor device using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100206880B1 (en) | 1999-07-01 |
| CN1156903A (en) | 1997-08-13 |
| JP2819282B2 (en) | 1998-10-30 |
| KR970053677A (en) | 1997-07-31 |
| JPH09186273A (en) | 1997-07-15 |
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