CN106558495B - Fin formula field effect transistor and forming method thereof - Google Patents
Fin formula field effect transistor and forming method thereof Download PDFInfo
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- CN106558495B CN106558495B CN201510631734.4A CN201510631734A CN106558495B CN 106558495 B CN106558495 B CN 106558495B CN 201510631734 A CN201510631734 A CN 201510631734A CN 106558495 B CN106558495 B CN 106558495B
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- 238000000034 method Methods 0.000 title claims abstract description 78
- 230000005669 field effect Effects 0.000 title claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- 238000000926 separation method Methods 0.000 claims abstract description 24
- 238000009413 insulation Methods 0.000 claims abstract description 16
- 239000000463 material Substances 0.000 claims description 127
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 113
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 73
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 68
- 229910052710 silicon Inorganic materials 0.000 claims description 68
- 239000010703 silicon Substances 0.000 claims description 68
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 47
- 238000005530 etching Methods 0.000 claims description 44
- 230000004888 barrier function Effects 0.000 claims description 24
- 239000002210 silicon-based material Substances 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 12
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 8
- 229910052986 germanium hydride Inorganic materials 0.000 claims description 8
- 238000009826 distribution Methods 0.000 claims description 7
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 257
- 230000037230 mobility Effects 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 125000006850 spacer group Chemical group 0.000 description 5
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 208000027418 Wounds and injury Diseases 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 208000014674 injury Diseases 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of fin formula field effect transistor and forming method thereof, wherein method includes: offer semiconductor substrate, and the semiconductor substrate surface has separation layer；It is formed in the insulation surface without strain fin unit and strain fin unit, described have multiple discrete without strain fin without strain fin unit, and the strain fin unit is with multiple discrete strain fins.The method improves the performance of fin formula field effect transistor.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of fin formula field effect transistor and forming method thereof.
Background technique
MOS transistor is one of most important element in modern integrated circuits.The basic structure of MOS transistor includes: half
Conductor substrate；Source region and position positioned at the gate structure of semiconductor substrate surface, in the semiconductor substrate of gate structure side
Drain region in the semiconductor substrate of the gate structure other side.The working principle of MOS transistor is: by applying electricity in gate structure
Pressure adjusts and generates switching signal by the electric current of gate structure bottom channel.
With the development of semiconductor technology, the MOS transistor of traditional plane formula dies down to the control ability of channel current,
Cause serious leakage current.And fin formula field effect transistor (Fin FET) is a kind of emerging multi-gate device, generally comprises protrusion
In the fin of semiconductor substrate surface, the top surface of fin and the gate structure of sidewall surfaces described in covering part are located at grid
Source region in the fin of pole structure side and the drain region in the fin of the gate structure other side.
However, the performance for the fin formula field effect transistor that the prior art is formed is to be improved.
Summary of the invention
Problems solved by the invention is to provide a kind of fin formula field effect transistor and forming method thereof, passes through and adjusts strain
Whether there is or not come realize strain fin carrier mobility and without strain fin carrier it is of different sizes so that different fins pair
There is the fin formula field effect transistor answered different electric properties to meet different functional requirements such as driving voltage and power consumption.
To solve the above problems, the present invention provides a kind of forming method of fin formula field effect transistor, comprising: offer is partly led
Body substrate, the semiconductor substrate surface have separation layer；It is formed in the insulation surface without strain fin unit and strain
Fin unit, described have multiple discrete without strain fin without strain fin unit, and the strain fin unit is with multiple
Discrete strain fin.
Optionally, described without strain fin and to strain the material of fin be monocrystalline silicon or described without strain fin and strain
The material of fin is monocrystalline SiGe.
Optionally, formed it is described without strain fin and strain fin the step of are as follows: the insulation surface formed monocrystalline
Silicon material layer；The single crystal silicon material layer is etched until exposing the insulation surface, forms multiple discrete monocrystalline silicon layers
And the first groove and the second groove between the monocrystalline silicon layer；After first recess sidewall forms side wall, to institute
It states and fills full fin material layer in the first groove and the second groove；Etch the fin material in first groove and the second groove
Layer is formed without strain fin and strain fin, described without strain fin and the discrete distribution of the strain fin；Remove the monocrystalline
Silicon layer and side wall.
Optionally, when the material without strain fin and strain fin is monocrystalline SiGe, in first groove
Fin material layer after etching is formed without fin is strained, and the fin material layer in second groove after etching forms strain fin
Portion.
Optionally, when the material without strain fin and strain fin is monocrystalline silicon, etching in first groove
Fin material layer afterwards forms strain fin, and the fin material layer in second groove after etching is formed without strain fin.
Optionally, described without strain fin includes no strained silicon fin and without strained SiGe fin, the strain fin packet
Include strained silicon fin and strained SiGe fin, the no strained silicon fin, without strained SiGe fin, strained silicon fin and strained Germanium
The vertical distribution in silicon fin part.
Optionally, formed it is described without strain fin and strain fin the step of are as follows: the insulation surface formed monocrystalline
Silicon material layer；The single crystal silicon material layer is etched until exposing the insulation surface, forms multiple discrete monocrystalline silicon layers
And the first groove and the second groove between the monocrystalline silicon layer；After first recess sidewall forms side wall, to institute
It states and fills full monocrystalline germanium silicon layer in the first groove and the second groove；The monocrystalline silicon layer is etched, is formed without strained silicon fin；Etching
Monocrystalline germanium silicon layer in first groove is formed without strained SiGe fin；The monocrystalline germanium silicon layer in second groove is etched,
It forms strained SiGe fin and sacrifices strained SiGe fin；In the no strained silicon fin, without strained SiGe fin, strained SiGe
Fin and side wall and the top surface formation barrier layer for sacrificing strained SiGe fin；Remove sacrifice strained SiGe fin side
Behind the barrier layer of side wall, in the sacrifice strained SiGe fin sidewall selectivity epitaxial growing strain silicon fin；Remove the side
Wall, barrier layer and sacrifice strained SiGe fin.
Optionally, the technique for forming the monocrystalline germanium silicon layer is selective epitaxial growth process, specific process parameter are as follows: adopt
Gas is SiH4、GeH4, HCl and H2, SiH4Flow be 1sccm~1000sccm, GeH4Flow be 1sccm~
The flow of 1000sccm, HCl are 1sccm~1000sccm, H2Flow be 0.1slm~50slm, chamber pressure be 1torr~
500torr, temperature are 600 degrees Celsius~1100 degrees Celsius.
Optionally, the technological parameter of strained silicon fin described in selective epitaxial growth are as follows: the gas used is SiH4、HCl
And H2, SiH4Flow be 1sccm~1000sccm, the flow of HCl is 1sccm~1000sccm, H2Flow be 0.1slm~
50slm, chamber pressure are 1torr~500torr, and temperature is 600 degrees Celsius~1100 degrees Celsius.
Optionally, the material of the side wall is unformed SiGe.
The present invention also provides a kind of fin formula field effect transistors, comprising: semiconductor substrate；Separation layer is partly led positioned at described
Body substrate surface；Without strain fin unit, be located at the insulation surface, it is described without strain fin unit have it is multiple discrete
Without strain fin；Fin unit is strained, the insulation surface is located at, the strain fin unit has multiple discrete strains
Fin.
Optionally, the material without strain fin and strain fin is monocrystalline SiGe.
Optionally, the material without strain fin and strain fin is monocrystalline silicon.
Optionally, described without strain fin includes no strained silicon fin and without strained SiGe fin, the strain fin packet
Include strained silicon fin and strained SiGe fin, the no strained silicon fin, without strained SiGe fin, strained silicon fin and strained Germanium
The vertical distribution in silicon fin part.
Compared with prior art, technical solution of the present invention has the advantage that
(1) due to form without strain fin unit and strain fin unit, it is described without strain fin unit have it is multiple
Discrete without strain fin, the strain fin unit has multiple discrete strain fins, with answering in the strain fin
Become, can be improved the carrier mobility in strain fin, so that the carrier mobility ratio of the strain fin is without strain fin
The carrier mobility in portion is big, so that whether there is or not to realize the carrier mobility of strain fin and without strain fin by adjusting strain
The carrier in portion is of different sizes, so that having without the different fin formula field effect transistors that strain fin and strain fin are correspondingly formed
Different electrology characteristics, such as driving voltage, power consumption, thus meet cannot functional requirement.
(2) further, using insulation surface be initially formed multiple discrete monocrystalline silicon layers and be located at the monocrystalline silicon
The first groove and the second groove between layer, after first recess sidewall forms side wall, the first groove of Xiang Suoshu and second
Full fin material layer is filled in groove, is then etched the fin material layer in the first groove and the second groove, is formed identical material
Without strain fin and strain fin, i.e., formed in a set of processing procedure identical material without strain fin and strain fin, relatively
In the technique without strain fin and strain fin for making identical material using different processing procedures respectively, the compatibility of technique is improved
Property.
(3) further, multiple discrete monocrystalline silicon layers and the first groove between the monocrystalline silicon layer are initially formed
With the second groove, full monocrystalline is filled after first recess sidewall forms side wall, in the first groove of Xiang Suoshu and the second groove
Germanium silicon layer；After etching the monocrystalline silicon layer, formed without strained silicon fin；Etch the monocrystalline germanium silicon layer in first groove, shape
At no strained SiGe fin；The monocrystalline germanium silicon layer in second groove is etched, strained SiGe fin is formed and sacrifices strained Germanium
Silicon fin portion；Then in the strained silicon fin for sacrificing the sidewall selectivity epitaxial growth of strained SiGe fin side.I.e. by
In a set of processing procedure, formed without strained silicon fin, without strained SiGe fin, strained SiGe fin and strained silicon fin, relative to point
Processing procedure that Shi Yong be not different makes the work without strained silicon fin, without strained SiGe fin, strained SiGe fin and strained silicon fin
Skill improves the compatibility of technique.
Detailed description of the invention
Fig. 1 to Fig. 9 is the structural schematic diagram of fin formula field effect transistor forming process in first embodiment of the invention；
Figure 10 and Figure 12 is the structural schematic diagram of fin formula field effect transistor forming process in second embodiment of the invention；
Figure 13 to Figure 19 is the structural schematic diagram of fin formula field effect transistor forming process in third embodiment of the invention.
Specific embodiment
As described in background, the performance for the fin formula field effect transistor that the prior art is formed is to be improved.
The study found that fin or nothing of the fin of the fin formula field effect transistor formed in the prior art using strain
The fin of strain needs to form the fin of the carrier with different mobilities in the fin formula field effect transistor of different zones,
The fin of single type strain is not able to satisfy has different mobilities big by adjusting the presence or absence of strain to realize in different fins
Small requirement.And the fin and strainless fin with strain are formed in fin formula field effect transistor, adjusting can be passed through
The presence or absence of strain corresponds to the different fins of different mobility size carriers to be formed, so that without strain fin and strain fin pair
The different fin formula field effect transistors that should be formed have different electrology characteristics, such as driving voltage, power consumption.How to be answered by adjusting
Become the presence or absence of come realize semiconductor substrate surface formed different fins have different mobility sizes be urgently to be resolved ask
Topic.
One embodiment of the invention provides a kind of forming method of fin formula field effect transistor, formed without strain fin unit and
Strain fin unit, described have multiple discrete without strain fin without strain fin unit, and the strain fin unit has
Multiple discrete strain fins realize the carrier mobility of strain fin by adjusting the presence or absence of strain and without strain fin
Carrier it is of different sizes so that without strain fin and straining the different fin formula field effect transistors that are correspondingly formed of fin and having not
Same electrology characteristic.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
First embodiment
Fig. 1 to Fig. 9 is the structural schematic diagram of fin formula field effect transistor forming process in first embodiment of the invention.
In the present embodiment, formed without strain fin unit and strain fin unit, it is described without strain fin unit have it is more
A discrete without strain fin, the strain fin unit has multiple discrete strain fins.And formed strain fin and
Material without strain fin is identical.
With reference to Fig. 1, provide substrate, the substrate include semiconductor substrate 100, positioned at 100 surface of semiconductor substrate every
Absciss layer 101 and single crystal silicon material layer 110 positioned at 101 surface of separation layer.
The material of the separation layer 101 is insulation oxide.
In the present embodiment, the substrate is silicon-on-insulator (SOI) structure, first offer body semiconductor layer, then monocrystalline
Silicon material layer 110 and semiconductor substrate 100 in body semiconductor layer by forming separation layer 101, the oxide such as buried, from institute
It states and is separated in body semiconductor layer.
With reference to Fig. 2, the single crystal silicon material layer 110 (with reference to Fig. 1) is etched until exposing 101 surface of separation layer,
Form multiple discrete monocrystalline silicon layers 111 and the first groove 120 and the second groove 121 between the monocrystalline silicon 111.
Specifically, first forming patterned first mask layer 130, the figure on 110 surface of single crystal silicon material layer
The first mask layer 130 changed defines the position of monocrystalline silicon layer 111；It is exposure mask with patterned first mask layer 130, etching
The single crystal silicon material layer 110 forms monocrystalline silicon layer 111, the first groove 120 and second up to exposing 101 surface of separation layer
Groove 121.
The material of first mask layer 130 is silicon nitride or silicon oxynitride.
In the present embodiment, Fig. 2 shows first grooves 120 and second groove 121 can in actual process
To form multiple first grooves 120 and multiple second grooves 121.
With reference to Fig. 3, in the side wall and bottom shape of 111 top surface of monocrystalline silicon layer, the first groove 120 and the second groove 121
At spacer material layer 140.
In the present embodiment, due to there is no removal to schedule the first mask layer 130 of 111 position of monocrystalline silicon layer, the side wall material
The bed of material 140 also covers the first mask layer 130.
The material of the spacer material layer 140 is unformed SiGe.
The technique for forming spacer material layer 140 is depositing operation, such as plasma activated chemical vapour deposition technique.
With reference to Fig. 4, the side wall material on 111 surface of monocrystalline silicon layer, 121 bottom of the first groove 120 and the second groove is removed
The bed of material 140 (refers to Fig. 3), forms side wall 141 in the side wall of the first groove 120 and the second groove 121.
Spacer material layer 140 is etched using anisotropy dry carving technology, until exposing the surface and first of separation layer 101
The surface of mask layer 130 forms side wall 141 in the first groove 120 and 121 side wall of the second groove.
During etching spacer material layer 140, first mask layer 130 can protect monocrystalline silicon layer 111
Not by etching injury.
With reference to Fig. 5, the side wall 141 of 121 side wall of the second groove is removed.
Specifically, it is initially formed the second mask layer (not shown), the side of the second mask layer covering 120 side wall of the first groove
Wall 141, then using second mask layer as exposure mask, the side wall 141 of etching removal 121 side wall of the second groove；Etching removal the
After the side wall 141 of two grooves, 121 side wall, second mask layer is removed.
The material of second mask layer is photoresist.
The technique of the side wall 141 of etching removal 121 side wall of the second groove is dry carving technology or wet-etching technique.
During removing side wall 141 of 121 side wall of the second groove, first mask layer 130 can protect monocrystalline
Silicon layer 111 is not by etching injury.
In other embodiments, after forming monocrystalline silicon layer 111, can remove definition 111 position of monocrystalline silicon layer first is covered
Film layer 130.
With reference to Fig. 6, after the side wall 141 for removing 121 side wall of the second groove, filled out into the first groove 120 and the second groove 121
Full of fin material layer 150.
In the present embodiment, the material of the fin material layer 150 is monocrystalline SiGe.
In the present embodiment, the technique for forming the fin material layer 150 is selective epitaxial growth process, the gas of use
For SiH4、GeH4, HCl and H2, SiH4Flow be 1sccm~1000sccm, GeH4Flow be 1sccm~1000sccm, HCl
Flow be 1sccm~1000sccm, H2Flow be 0.1slm~50slm, chamber pressure be 1torr~500torr, temperature
It is 600 degrees Celsius~1100 degrees Celsius.
In the present embodiment, the material of fin material layer 150 is monocrystalline SiGe, the fin material grown in the first groove 120
The bed of material 150 and side wall 141 contact, and the material of the two is SiGe, therefore the fin material layer 150 in the first groove 120
Do not strain, and the fin material layer 150 in the second groove 121 is contacted with monocrystalline silicon layer 111, and the material of the two is not identical,
Lattice mismatches, therefore the fin material layer 150 in the second groove 121 has strain.
During forming fin material layer 150, first mask layer 130 can stop fin material layer 150 raw
It grows in 111 top surface of monocrystalline silicon layer.
After having grown the fin material layer 150, using flatening process, such as mechanical-chemistry grinding technique planarization first
The top surface of mask layer 130 and fin material layer 150 up to exposing monocrystalline silicon layer 111, removes the first mask layer 130
It removes, and the top surface of the top surface of fin material layer 150 and monocrystalline silicon layer 111 flushes.
With reference to Fig. 7, third mask layer 160, fin material in the first groove 120 are formed in 150 top surface of fin material layer
The third mask layer 160 of 150 top surface of the bed of material defines the position to be formed without strain fin, fin in the second groove 121
The third mask layer 160 of 150 top surface of material layer defines the position of strain fin to be formed.
The material of the third mask layer 160 is silicon nitride, silicon oxynitride or photoresist.In the present embodiment, the third
The material of mask layer 160 is photoresist.
It is exposure mask with third mask layer 160 with reference to Fig. 8, fin material layer 150 is etched using anisotropy dry carving technology
(with reference to Fig. 7) until exposing surface of separation layer 101, the fin material layer 150 in the first groove 120 after etching forms nothing and answers
Become fin 170, the fin material layer 150 in the second groove 121 after etching forms strain fin 171.
In the present embodiment, since the material of side wall 141 (referring to Fig. 7) and the material of fin material layer 150 are SiGe,
Also side wall 140 is removed together while etching fin material layer 150, simplifies technique.In other embodiments, Ke Yifen
The step of not performing etching fin material layer 150 and removal side wall 141.
In the present embodiment, monocrystalline silicon layer 111 (referring to Fig. 7) also etching is removed while etching fin material layer 150,
Simplify processing step；In other embodiments, it may is that after etching fin material layer 150, monocrystalline silicon layer 111 etched
After removal, or removal monocrystalline silicon layer 111, fin material layer 150 is etched.
In the present embodiment, while etching the fin in the fin material layer 150 and the second groove 121 in the first groove 120
Material layer 150.In other embodiments, the fin material layer 150 and the second groove in the first groove 120 can be etched step by step
Fin material layer 150 in 121 is formed step by step without strain fin 170 and strain fin 171.
With reference to Fig. 9, after etching fin material layer 150, removal third mask layer 160 (refers to Fig. 8).
The technique for removing third mask layer 160 is wet-etching technique or dry carving technology.
It should be noted that it is one that Fig. 9, which is shown without strain 170 quantity of fin, the quantity of strain fin 171 is one,
Only it is used as example.In actual process, quantity of the selection without strain fin 170 and strain fin 171 can according to need.
In the present embodiment, with reference to Fig. 9, the fin formula field effect transistor of formation includes: semiconductor substrate 100；Separation layer
101, it is located at 100 surface of semiconductor substrate；Positioned at 101 surface of separation layer without strain fin unit, the nothing is answered
Becoming fin unit has without strain fin 170；Strain fin unit positioned at 101 surface of separation layer, the strain fin
Unit has strain fin 171.
In the present embodiment, using being made in a set of processing procedure without strain fin 170 and strain fin 171, compare with a set of
Processing procedure has made strain fin 171, then with the production of another set of processing procedure without the technique for straining fin 170, or with a set of processing procedure
It has made without strain fin 170, the technique that strain fin 171 is then made of another set of processing procedure, has improved production strain fin
170 and without strain fin 171 processing compatibility.
Second embodiment
Figure 10 and Figure 12 is the structural schematic diagram of fin formula field effect transistor forming process in second embodiment of the invention.
The difference of second embodiment and first embodiment is: in a second embodiment, the material of fin material layer 150 is
Monocrystalline silicon, the fin material layer 150 in the first groove 120 are used to form strain fin, the fin material layer in the second groove 121
150 are used to form without strain fin.Identical part is no longer described in detail in second embodiment and first embodiment.
In the present embodiment, the material of fin material layer 150 is monocrystalline silicon, with reference to Fig. 6, the fin that is grown in the first groove 120
Portion's material layer 150 and side wall 141 contact, and the material of the two is not identical, and lattice mismatches, so that the fin in the first groove 120
Portion's material layer 150 has strain, and the fin material layer 150 in the second groove 121 is contacted with monocrystalline silicon layer 111, and the two
Material is that monocrystalline silicon, Lattice Matching, therefore the fin material layer 150 in the second groove 121 do not have strain.
In the present embodiment, the technique for forming fin material layer 150 is selective epitaxial growth process, specific technological parameter
Are as follows: the gas used is SiH4, HCl and H2, SiH4Flow be 1sccm~1000sccm, the flow of HCl be 1sccm~
1000sccm, H2Flow be 0.1slm~50slm, chamber pressure be 1torr~500torr, temperature be 600 degrees Celsius~
1100 degrees Celsius.
With reference to Figure 10, Figure 10 is the schematic diagram formed on the basis of Fig. 6, forms the in 150 top surface of fin material layer
Four mask layers 260, the 4th mask layer 260 of 150 top surface of fin material layer defines strain to be formed in the first groove 120
The position of fin, the 4th mask layer 260 of 150 top surface of fin material layer defines nothing to be formed and answers in the second groove 121
Become the position of fin.
The material of 4th mask layer 260 is silicon nitride, silicon oxynitride or photoresist.In the present embodiment, the described 4th
The material of mask layer 260 is photoresist.
With reference to Figure 11, with the 4th mask layer 260 for exposure mask, fin material layer 150 is etched using anisotropy dry carving technology
Until exposing the surface of separation layer 101, the fin material layer 150 in the first groove 120 after etching forms strain fin 173,
Fin material layer 150 in second groove 121 after etching is formed without strain fin 174.
In the present embodiment, since monocrystalline silicon layer 111 (referring to Figure 10) is identical with the material of fin material layer 150, etching
Also monocrystalline silicon layer 111 is removed together while fin material layer 150, simplifies processing step.It in other embodiments, can be with
The step of performing etching fin material layer 150 and removal monocrystalline silicon layer 111 respectively.
In the present embodiment, also side wall 141 (referring to Figure 10) etching is removed while etching fin material layer 150.?
In other embodiments, the step of fin material layer 150 can be performed etching respectively and remove side wall 141.
In the present embodiment, while etching the fin in the fin material layer 150 and the second groove 121 in the first groove 120
Material layer 150.In other embodiments, the fin material layer 150 and the second groove in the first groove 120 can be etched step by step
Fin material layer 150 in 121 forms strain fin 173 without strain fin 174 step by step.
With reference to Figure 12, after etching fin material layer 150, the 4th mask layer 260 (referring to Figure 11) of removal.
The technique for removing the 4th mask layer 260 is wet-etching technique or dry carving technology.
In the present embodiment, with reference to Figure 12, the fin formula field effect transistor of formation includes: semiconductor substrate 100；Separation layer
101, it is located at 100 surface of semiconductor substrate；Strain fin unit positioned at 101 surface of separation layer, the no strain
Fin unit has strain fin 173；It is described without strain fin positioned at 101 surface of separation layer without strain fin unit
Unit has without strain fin 174.
In the present embodiment, without strain fin 174 and strain fin 173, compared with a set of system using in the production of a set of processing procedure
Journey system is finished straining fin 173, then with the production of another set of processing procedure without the technique for straining fin 174, or with a set of processing procedure system
Finish without strain fin 174, the technique that strain fin 173 is then made of another set of processing procedure, improves production strain fin 173
With the processing compatibility without strain fin 174.
3rd embodiment
Figure 13 to Figure 19 is the structural schematic diagram of fin formula field effect transistor forming process in third embodiment of the invention.
The difference of 3rd embodiment and first embodiment, second embodiment is: formation includes that nothing is answered without strain fin
Become silicon fin portion and without strained SiGe fin, the strain fin of formation includes strained silicon fin and strained SiGe fin, and the nothing is answered
Become silicon fin portion, without strained SiGe fin, strained silicon fin and the discrete distribution of strained SiGe fin.I.e. in a set of processing procedure, formed
Without strained silicon fin, without strained SiGe fin, strained silicon fin and strained SiGe fin.
With reference to Figure 13, Figure 13 is the schematic diagram formed on the basis of Fig. 5, is filled out into the first groove 120 and the second groove 121
Full of monocrystalline germanium silicon layer 350.
The material of the monocrystalline germanium silicon layer 350 is monocrystalline SiGe.
In the present embodiment, the technique for forming the monocrystalline germanium silicon layer 350 is selective epitaxial growth process, specific technique
Parameter are as follows: the gas used is SiH4、GeH4, HCl and H2, SiH4Flow be 1sccm~1000sccm, GeH4Flow be
The flow of 1sccm~1000sccm, HCl are 1sccm~1000sccm, H2Flow be 0.1slm~50slm, chamber pressure is
1torr~500torr, temperature are 600 degrees Celsius~1100 degrees Celsius.
In the present embodiment, monocrystalline germanium silicon layer 350 and side wall 141 contact grown in the first groove 120, and the material of the two
It is SiGe, therefore do not strained in the monocrystalline germanium silicon layer 350 in the first groove 120, and the monocrystalline germanium in the second groove 121
Silicon layer 350 is contacted with monocrystalline silicon layer 111, and the material of the two is not identical, and lattice mismatches, therefore the list in the second groove 121
Brilliant germanium silicon layer 350 has strain.
During forming monocrystalline germanium silicon layer 350, first mask layer 130 can stop monocrystalline germanium silicon layer 350 raw
Grow the top surface in monocrystalline silicon layer 111.
After having grown monocrystalline germanium silicon layer 350, the first exposure mask is planarized using flatening process, such as mechanical-chemistry grinding technique
The top surface of layer 130 and monocrystalline germanium silicon layer 350 up to exposing monocrystalline silicon layer 111, is removed the first mask layer 130, and
The top surface of monocrystalline germanium silicon layer 350 and the top surface of monocrystalline silicon layer 111 flush.
After forming monocrystalline germanium silicon layer 350, monocrystalline silicon layer 111 is etched, is formed without strained silicon fin；Etch first groove
Monocrystalline germanium silicon layer 350 in 120 is formed without strained SiGe fin；The monocrystalline germanium silicon layer 350 in second groove 121 is etched,
It forms strained SiGe fin and sacrifices strained SiGe fin.
In the present embodiment, while monocrystalline silicon layer 111 and monocrystalline germanium silicon layer 350 are etched, simplify processing step, specifically, ginseng
Figure 14 is examined, forms the 5th mask layer 360 in the top surface of 350 top surface of monocrystalline germanium silicon layer and monocrystalline silicon layer 111, first is recessed
The 5th mask layer 360 of 350 top surface of monocrystalline germanium silicon layer defines the position of no strained SiGe fin to be formed in slot 120,
5th mask layer 360 of 350 top surface of monocrystalline germanium silicon layer in the second groove 121 define strained SiGe fin to be formed and
The position of strained SiGe fin is sacrificed, the 5th mask layer 360 of the top surface of monocrystalline silicon layer 111 defines no strain to be formed
The position in silicon fin portion, and define without strained SiGe fin, strained SiGe fin, sacrifice strained SiGe fin and without strained silicon fin
Position the discrete distribution of the 5th mask layer 360, the material of the 5th mask layer 360 is silicon nitride or silicon oxynitride.This reality
It applies in example, the material of the 5th mask layer 360 is silicon nitride.It is adopted with reference to Figure 15 with the 5th mask layer 360 for exposure mask
Monocrystalline silicon layer 111 and monocrystalline germanium silicon layer 350 are etched with anisotropy dry carving technology, until the surface of separation layer 101 is exposed, the
Monocrystalline germanium silicon layer 350 in one groove 120 after etching is formed without strained SiGe fin 371, the list in the second groove 121 after etching
Brilliant germanium silicon layer 350 forms strained SiGe fin 372 and sacrifices strained SiGe fin 373, and the monocrystalline silicon layer 111 after etching forms nothing
Strained silicon fin 370.
Due to monocrystalline silicon layer 111 material be the monocrystalline silicon without strain, formed without in strained silicon fin 370
Do not strain；Since the monocrystalline germanium silicon layer 350 in the first groove 120 does not strain, thus formed without in strained SiGe fin 371
Without strain；Due to having strain in the monocrystalline germanium silicon layer 350 in the second groove 121, the strained SiGe fin formed
372 and sacrifice strained SiGe fin 373 in have strain.
In the present embodiment, strained SiGe fin 372 and sacrifice strained SiGe fin 373 are by same second groove 121
The etching of monocrystalline germanium silicon layer 350 is formed；In other embodiments, strained SiGe fin 372 and sacrifice strained SiGe fin 373 can be with
It is formed by the etching of monocrystalline germanium silicon layer 350 in the second different grooves 121.
It should be noted that in other embodiments, monocrystalline silicon layer 111 and monocrystalline germanium silicon layer can be performed etching respectively
350 the step of, and the monocrystalline germanium silicon layer 350 in the first groove 120 and the second groove 121 can be etched step by step, different
It is formed in etch step without strained SiGe fin 371, strained SiGe fin 372 and sacrifices strained SiGe fin 373.
In the present embodiment, since the material of monocrystalline germanium silicon layer 350 and side wall 141 is SiGe, in etching monocrystalline
Also side wall 141 is removed together while germanium silicon layer 350.In other embodiments, monocrystalline germanium silicon layer can be performed etching respectively
350 and removal side wall 141 the step of.
With reference to Figure 16, form barrier layer, the barrier layer covering without strained silicon fin 370, without strained SiGe fin 371,
Strained SiGe fin 372 and the side wall and top surface for sacrificing strained SiGe fin 373.
For the convenience of description, the barrier layer is divided into two parts: positioned at no strained silicon fin 370, without strained Germanium silicon fin
Portion 371, strained SiGe fin 372 and the first barrier layer for sacrificing 373 top surface of strained SiGe fin, positioned at no strained silicon fin
Portion 370, the second barrier layer without strained SiGe fin 371, strained SiGe fin 372 and sacrifice 373 side wall of strained SiGe fin
380。
In the present embodiment, formed without strained silicon fin 370, without strained SiGe fin 371, strained SiGe fin 372 and sacrificial
After domestic animal strained SiGe fin 373, the 5th mask layer 360 is remained, regard the 5th mask layer 360 as the first barrier layer.Meanwhile only
It needs in no strained silicon fin 370, without strained SiGe fin 371, strained SiGe fin 372 and sacrifice strained SiGe fin 373
Side wall forms the second barrier layer 380.
The material on second barrier layer 380 is silicon nitride or silicon oxynitride.
The step of forming the second barrier layer 380 are as follows: form covering 101 surface of separation layer and without strained silicon fin 370, nothing
Second resistance of strained SiGe fin 371, the top surface of strained SiGe fin 372 and sacrifice strained SiGe fin 373 and side wall
Obstructing material layer (not shown)；The second barrier material layer is etched using anisotropy dry carving technology until exposing separation layer
101 surface forms the second barrier layer 380.
With reference to Figure 17, the barrier layer of 373 side side wall of strained SiGe fin is sacrificed in removal, is then sacrificing strained Germanium silicon fin
Sidewall selectivity epitaxial growing strain silicon fin 374 behind the removal barrier layer in portion 373.
The step of barrier layer of 373 side side wall of strained SiGe fin, is sacrificed in removal are as follows: forms covering 101 table of separation layer
Face and without strained silicon fin 370, the side wall without strained SiGe fin 371 and strained SiGe fin 372 and top surface and sacrificial
The photoresist layer of 373 other side side wall of domestic animal strained SiGe fin；Using the photoresist layer as exposure mask, strained Germanium is sacrificed in etching removal
The barrier layer of 373 side side wall of silicon fin portion.
In the present embodiment, the technological parameter of selective epitaxial growth strained silicon fin 374 are as follows: the gas used is SiH4、
HCl and H2, SiH4Flow be 1sccm~1000sccm, the flow of HCl is 1sccm~1000sccm, H2Flow be
0.1slm~50slm, chamber pressure are 1torr~500torr, and temperature is 600 degrees Celsius~1100 degrees Celsius.
Since the material for sacrificing strained SiGe fin 373 is different with the material of strained silicon fin 374, lattice is mismatched, because
This, has strain in the strained silicon fin 374 of formation.
The barrier layer is removed after forming strained silicon fin 374 with reference to Figure 18.
In the present embodiment, the barrier layer is removed using wet-etching technique.
With reference to Figure 19, after removing the barrier layer, strained SiGe fin 373 (referring to Figure 18) is sacrificed in removal.
The step of strained SiGe fin 373, is sacrificed in removal are as follows: forms photoresist layer, the photoresist layer covering is without strained silicon
Fin 370, without strained SiGe fin 371, the top of strained SiGe fin 372 and strained silicon fin 374 and the side that exposes
Wall；Using the photoresist layer as exposure mask, strained SiGe fin 373 is sacrificed in removal.
The technique that strained SiGe fin 373 is sacrificed in removal is anisotropy dry carving technology.
It should be noted that in other embodiments, can first remove and sacrifice strained SiGe fin 373, described in rear removal
Protective layer.
It should also be noted that in the present embodiment, only illustrate no strained silicon fin 370, without strained SiGe fin 371, answer
Become a kind of situation of the arrangement mode of germanium silicon fin portion 372 and strained silicon fin 374.In other embodiments, no strained silicon fin
370, the arrangement mode without strained SiGe fin 371, strained SiGe fin 372 and strained silicon fin 374 can in any combination, no
It is described in detail again.
In the present embodiment, with reference to Figure 19, the fin formula field effect transistor of formation includes: semiconductor substrate 100；Separation layer
101, it is located at 100 surface of semiconductor substrate；Without strain fin unit, it is located at the insulation surface 101, the no strain
Fin unit has multiple discrete without strain fin, and described without strain fin includes no strained silicon fin 370 and without strained Germanium
Silicon fin portion 371；Fin unit is strained, 101 surface of separation layer is located at, the strain fin unit has multiple discrete answer
Become fin, the strain fin includes strained silicon fin 374 and strained SiGe fin 372, the no strained silicon fin 370, nothing
Strained SiGe fin 371, strained silicon fin 374 and the discrete distribution of strained SiGe fin 372.
In the present embodiment, made of a set of processing procedure without strained silicon fin 370, without strained SiGe fin 371, strained SiGe
Fin 372 and strained silicon fin 374 make without strained silicon fin 370, without strained SiGe fin 371 compared to of different processing procedures, answer
The technique for becoming germanium silicon fin portion 372 and strained silicon fin 374, improves processing compatibility.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (7)
1. a kind of forming method of fin formula field effect transistor characterized by comprising
Semiconductor substrate is provided, the semiconductor substrate surface has separation layer；
The insulation surface formed without strain fin unit and strain fin unit, it is described without strain fin unit have it is more
A discrete without strain fin, the strain fin unit has multiple discrete strain fins；
It is formed using the first manufacturing process or the second manufacturing process described without strain fin and strain fin；
It is described without strain fin and when strain fin when being formed using the first manufacturing process, it is formed described without strain fin and strain
The step of fin are as follows: form single crystal silicon material layer in the insulation surface；The single crystal silicon material layer is etched until exposing
The insulation surface forms multiple discrete monocrystalline silicon layers and the first groove between the monocrystalline silicon layer and second recessed
Slot；Full fin material layer is filled after first recess sidewall forms side wall, in the first groove of Xiang Suoshu and the second groove；It carves
The fin material layer in first groove and the second groove is lost, is formed without strain fin and strain fin, it is described without strain fin
Portion and the discrete distribution of the strain fin；Remove the monocrystalline silicon layer and side wall；
It is described without strain fin and when strain fin when being formed using the second manufacturing process, it is formed described without strain fin and strain
The step of fin are as follows: form single crystal silicon material layer in the insulation surface；The single crystal silicon material layer is etched until exposing
The insulation surface forms multiple discrete monocrystalline silicon layers and the first groove between the monocrystalline silicon layer and second recessed
Slot；Full monocrystalline germanium silicon layer is filled after first recess sidewall forms side wall, in the first groove of Xiang Suoshu and the second groove；It carves
The monocrystalline silicon layer is lost, is formed without strained silicon fin；The monocrystalline germanium silicon layer in first groove is etched, is formed without strained SiGe
Fin；The monocrystalline germanium silicon layer in second groove is etched, strained SiGe fin is formed and sacrifices strained SiGe fin；Described
No strained silicon fin, side wall and top surface shape without strained SiGe fin, strained SiGe fin and sacrifice strained SiGe fin
At barrier layer；After removing the barrier layer for sacrificing strained SiGe fin side side wall, in sacrifice strained SiGe fin side
Wall selective epitaxial growth strained silicon fin；It removes the side wall, barrier layer and sacrifices strained SiGe fin.
2. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that use the first technique system
Journey forms described without strain fin and strain fin；It is described without strain fin and to strain the material of fin be monocrystalline silicon or described
It is monocrystalline SiGe without strain fin and the material for straining fin.
3. the forming method of fin formula field effect transistor according to claim 2, which is characterized in that when described without strain fin
When the material of portion and strain fin is monocrystalline SiGe, the fin material layer in first groove after etching is formed without strain fin
Portion, the fin material layer in second groove after etching form strain fin.
4. the forming method of fin formula field effect transistor according to claim 2, which is characterized in that when described without strain fin
When the material of portion and strain fin is monocrystalline silicon, the fin material layer in first groove after etching forms strain fin, institute
The fin material layer in the second groove after etching is stated to be formed without strain fin.
5. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that in the second manufacturing process
In, formed the monocrystalline germanium silicon layer technique be selective epitaxial growth process, specific process parameter are as follows: the gas used for
SiH4、GeH4, HCl and H2, SiH4Flow be 1sccm~1000sccm, GeH4Flow be 1sccm~1000sccm, HCl's
Flow is 1sccm~1000sccm, H2Flow be 0.1slm~50slm, chamber pressure is 1torr~500torr, and temperature is
600 degrees Celsius~1100 degrees Celsius.
6. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that in the second manufacturing process
In, the technological parameter of strained silicon fin described in selective epitaxial growth are as follows: the gas used is SiH4, HCl and H2, SiH4Stream
Amount is 1sccm~1000sccm, and the flow of HCl is 1sccm~1000sccm, H2Flow be 0.1slm~50slm, chamber pressure
It is by force 1torr~500torr, temperature is 600 degrees Celsius~1100 degrees Celsius.
7. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that the material of the side wall
For unformed SiGe.
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