CN106558347B - Programming test method of phase change memory - Google Patents
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Abstract
The invention provides a phase change memoryThe phase change memory comprises a transistor and a phase change storage resistance unit, wherein the drain electrode of the transistor is electrically connected with the phase change storage resistance unit, and the method comprises the following steps: step S1: applying a direct current voltage on a grid electrode of the transistor to turn on the transistor, and applying a pulse voltage on a drain electrode of the transistor to carry out an operation step on the phase change memory; step S2: applying a DC voltage V to the gate of the transistorGTo turn on the transistor and simultaneously apply a DC voltage V to the drainDTo perform a read operation and measure the resistance of the phase change memory resistance cell. The method enables the voltage to drop on the drain electrode of the transistor, so that the transistor has larger load resistance, current flows from the transistor to the phase change material layer, and the resistance of the phase change memory resistance unit is measured.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a programming test method of a phase change memory.
Background
With the development of information technology, especially the popularization of mobile phones and other portable electronic devices, the application of nonvolatile memory chips has penetrated the aspects of modern human life. Flash Memory (Flash Memory) has been developed over the past decade as a typical non-volatile Memory, but floating gate based Flash Memory technology has experienced difficulties in scaling down after semiconductor technology has entered the 22nm node. At this time, the Phase Change Random Access Memory (PCRAM) technology is widely used because it has great advantages over the flash Memory technology in many aspects such as cell area, read/write speed, read/write times, and data retention time.
Among other things, one of the key roles of the PCRAM is to suppress operating power. Where amorphous operation current is an important parameter characterizing PCRAM energy consumption, monitoring phase change memory operation and amorphous operation power in a test structure is very important for character processing capability. The current for amorphous operation and the resistance of the phase change material are the main electrical parameters for designing the power supply of the device. Obtaining such data is therefore critical to the design of the chip.
At present, the test structure comprises a transistor and a phase change material connected with a drain electrode of the transistor, and for a PCRAM memory chip, a voltage pulse is applied to the drain electrode, and the voltage drop is caused in a phase change memory resistance unit due to the fact that the resistance value of the phase change memory resistance unit is too large, and the transistor does not realize the idea of opening. For the test structure, a pulsed voltage was applied to the 1T1R device since no pulsed current was generated by the device. However, the 1T1R test yield profile shows that almost all data operations fail, even with an output current of 1T greater than 3 mA.
Therefore, there is a need for improvements in current PCRAM testing methods to eliminate the various problems presented above.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In order to overcome the existing problems, the invention provides a programming test method of a phase change memory, wherein the phase change memory comprises a transistor and a phase change storage resistance unit, the drain electrode of the transistor is electrically connected with the phase change storage resistance unit, and the method comprises the following steps:
a programming test method of a phase change memory, the phase change memory including a transistor and a phase change storage resistance unit, a drain of the transistor being electrically connected to the phase change storage resistance unit, the method comprising:
step S1: applying a direct current voltage on a grid electrode of the transistor to turn on the transistor, and applying a pulse voltage on a drain electrode of the transistor to carry out an operation step on the phase change memory;
step S2: applying a DC voltage V to the gate of the transistorGTo turn on the transistor and simultaneously apply a DC voltage V to the drainDTo perform a read operation and measure the resistance of the phase change memory resistance cell.
Optionally, in the step S1, the substrate of the transistor and the source of the transistor are grounded.
Optionally, the step S2 includes:
step S21: measuring the current on the drain and according to the DC voltage V applied on the drainDCalculating the total resistance of the phase change memory;
step S22: measuring the resistance of the transistor alone;
step S23: and subtracting the single resistance of the transistor from the total resistance of the phase change memory to obtain the resistance of the phase change memory resistance unit.
Alternatively, in step S22, the resistance of the transistor alone is obtained by measuring the resistance of a reference transistor that is identical to the transistor in the phase change memory.
Optionally, the steps S1 and S2 are executed in a loop, and the dc voltage V on the gate is continuously increased during each loopGAnd determining the state of the phase change memory resistance cell according to the resistance of the phase change memory resistance cell obtained in the step S2.
Optionally, the step S2 further includes a step of measuring an amorphous operation current of the phase change memory.
Optionally, the step of measuring the amorphous state operation current of the phase change memory comprises:
measuring I of a reference transistor identical to the transistor in the phase change memoryD-VGA graph;
according to the V in the step S2DAnd said VGAt the placeThe following formula ID-VDFind the V on the graphDAnd said VGCorresponding current IDSince the resistance of the phase change material entering the molten state is very low, I isDAn amorphous state operating current may be approximated.
Optionally, the phase change memory resistance unit includes at least an upper electrode and a lower electrode and a phase change material layer between the upper electrode and the lower electrode.
In order to solve the problems in the prior art, the invention provides a programming test method of a phase change memory, in the method, voltage is applied to a grid electrode of a transistor to turn on the transistor, direct current voltage is applied to a drain electrode, and a substrate of the transistor is grounded; calculating the total resistance of the phase change memory by measuring the current on the drain electrode and according to the direct current voltage applied on the drain electrode; measuring the resistance of the transistor alone; and finally, subtracting the independent resistance of the transistor from the total resistance of the phase change memory to obtain the resistance of the phase change memory resistance unit.
The method avoids the problem that the voltage drops on the phase change storage resistor unit and the transistor is not turned on due to overlarge resistance of the phase change storage resistor unit, and the voltage drops on the drain electrode of the transistor, so that the transistor has a large load resistance, current flows from the transistor to the phase change material layer, and the resistance of the phase change storage resistor unit is measured.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. There are shown in the drawings, embodiments and descriptions thereof, which are used to explain the principles and apparatus of the invention. In the drawings, there is shown in the drawings,
FIG. 1 is a schematic structural diagram illustrating a programming test method of a phase change memory according to an embodiment of the invention;
FIG. 2 is a diagram illustrating voltages in a programming test method of a phase change memory according to an embodiment of the invention;
FIG. 3 is a yield distribution diagram of a programming test method of a phase change memory, wherein A is the yield distribution diagram of the programming test method of the phase change memory in the present invention, and B is the yield distribution diagram of the programming test method of the phase change memory in the prior art;
FIG. 4 is a flowchart illustrating a programming test method of the phase change memory according to an embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
Example one
In order to solve the problems in the prior art, the present invention provides a programming test method for a phase change memory, which is further described below with reference to the accompanying drawings. Fig. 1 is a schematic structural diagram illustrating a programming test method of a phase change memory according to an embodiment of the invention; FIG. 2 is a diagram illustrating voltages in a programming test method of a phase change memory according to an embodiment of the invention; fig. 3 is a yield distribution diagram of a programming test method of a phase change memory, wherein a is the yield distribution diagram of the programming test method of the phase change memory in the present invention, and B is the yield distribution diagram of the programming test method of the phase change memory in the prior art.
The invention discloses a programming test method of a phase change memory, wherein the phase change memory comprises a transistor and a phase change memory resistance unit (PCR), the drain electrode of the transistor is electrically connected with the phase change memory resistance unit, and the method comprises the following steps:
step S1: applying a direct current voltage on a grid electrode of the transistor to turn on the transistor, and applying a pulse voltage on a drain electrode of the transistor to carry out an operation step on the phase change memory;
step S2: applying a DC voltage V to the gate of the transistorGTo turn on the transistor and simultaneously apply a DC voltage V to the drainDTo perform a read operation and measure the resistance of the phase change memory resistance cell.
In the phase change memory, the transistor may be a transistor commonly found in the art, for example, the transistor includes a semiconductor substrate, a gate structure located on the semiconductor substrate, and basic elements such as a source end and a drain end located at two ends of the gate structure, and may also include other conventional elements, which are not described herein again.
As shown in fig. 1, VD is the voltage applied to the drain, VS is the voltage applied to the source, and VDs is the voltage between the drain and the source. In fig. 2, where Vb is the dc voltage and Vds pulse is the voltage between the drain and source.
Wherein the phase change memory resistance unit includes:
the semiconductor device comprises a semiconductor substrate 100, wherein a semiconductor device, a metal interconnection structure and an isolation structure are contained in the semiconductor substrate 100;
the lower electrode 101 is positioned in the semiconductor substrate 100, the surface of the lower electrode 101 is flush with the surface of the semiconductor substrate 100, and the lower electrode 101 is electrically connected with a semiconductor device or a metal interconnection structure in the semiconductor substrate 100;
a first dielectric layer 102 on the semiconductor substrate 100; a small electrode 103 positioned in the first dielectric layer 102, wherein the small electrode 103 is electrically connected with the lower electrode 101, the cross-sectional area of the small electrode 103 is smaller than that of the lower electrode 101, and the surface of the small electrode 103 is flush with the surface of the first dielectric layer 102;
a phase change material layer 105 on the small electrode 103; a transition metal layer 106 located on the phase change material layer 105, wherein the transition metal layer 106 functions as an adhesive and a thermal insulator;
an upper electrode 107 located on the transition metal layer 106, wherein the upper electrode 107 is connected with an external circuit; a second dielectric layer 104 covering the phase change material layer 105, the transition metal layer 106 and the upper electrode 107, wherein a surface of the second dielectric layer 104 is flush with a surface of the upper electrode 107, as shown in the right-side diagram of fig. 1.
It should be noted that the structure of the phase change memory in the present invention is merely exemplary and is not limited to the example.
In the invention, the problem that in the prior art, when a grid is opened, a voltage pulse is applied to a drain electrode, and the resistance value of a phase change storage resistor unit is too large, so that the voltage drop is caused in the phase change storage resistor unit, and a transistor is not opened is solved, therefore, a direct current voltage is applied to the grid electrode of the transistor to conduct the transistor, and a substrate and a source electrode of the transistor are grounded, as shown in fig. 1.
The operation comprises an operation step and a reading step, wherein in the operation step, a direct current voltage is applied to a grid electrode of the transistor to turn on the transistor, and a pulse voltage is applied to a drain electrode of the transistor; at a place whereThe phase change memory operation is followed by a read step in which a direct current voltage V is applied to the gate of the transistorGTo turn on the transistor and simultaneously apply a DC voltage V to the drainDTo perform a read operation.
The method can drop voltage on the drain of the transistor, so that the transistor has larger load resistance, thereby realizing that current flows from the transistor to the phase change material layer, then measuring the current on the drain, and further realizing the measurement of the resistance of the phase change memory resistance unit, and specifically comprises the following steps:
(1) according to the DC voltage V on the drainDAnd the current on the drain electrode, calculating the total resistance R of the phase change memoryT+RRWherein said R isTIs the resistance of a transistor, said RRThe resistance of the phase change memory resistance unit.
The measuring instrument and the measuring method for the resistance and the current can be selected from instruments and methods commonly used in the art, are not limited to a certain instrument, and are not further described herein.
(2) Measuring the resistance R of the transistor aloneT. Wherein the resistance RTThe method of (2) may be such that the resistance R of the transistor alone is obtained by measuring the resistance of a reference transistor identical to the transistor in the phase change memoryT。
Wherein, the completely same means that the transistor and the reference transistor have the same size and structure to ensure that the transistor and the reference transistor also have completely the same resistance, thereby indirectly measuring the resistance R of the transistor aloneT。
(3) Setting the total resistance R of the phase change memoryT+RRMinus the resistance R of the transistor aloneTObtaining the resistance R of the phase change storage resistance unitR。
In the method, the dc voltage applied to the gate completely wraps up the pulse voltage on the drain, and the wrapping means that the period of applying the pulse voltage to the drain is included in the period of applying the dc voltage to the gate, that is, the dc voltage may be applied to the gate earlier than the pulse voltage on the drain or simultaneously, and the end point of applying the voltage to the gate is later than the end point of applying the pulse voltage on the drain.
Further, the steps S1 and S2 are executed in a loop, and the dc voltage V on the gate is continuously increased during each loopGAnd determining the state of the phase-change memory resistance cell according to the resistance of the phase-change memory resistance cell obtained in the step S2, for example, the phase-change material layer is in an amorphous state with a low starting voltage and a small current, and may change into a molten state with the increasing voltage.
In order to solve the problems in the prior art, the invention provides a programming test method of a phase change memory, in the method, a direct current voltage is applied to a grid electrode of a transistor to turn on the transistor, a direct current voltage is applied to a drain electrode, and a substrate of the transistor is grounded; calculating the total resistance of the phase change memory by measuring the current on the drain electrode and according to the direct current voltage on the drain electrode; measuring the resistance of the transistor alone; and finally, subtracting the independent resistance of the transistor from the total resistance of the phase change memory to obtain the resistance of the phase change memory resistance unit.
The method avoids the problem that the resistance value of the phase change storage resistor unit is too large, so that the voltage drops on the phase change storage resistor unit, and the transistor is not opened, so that the voltage drops on the drain electrode of the transistor, the transistor has a large load resistor, the current flows from the transistor to the phase change material layer, the measurement of the resistance of the phase change storage resistor unit is realized, and the yield of the programming test method of the phase change memory is greatly improved by the method, wherein A is the yield distribution diagram of the programming test method of the phase change memory, B is the yield distribution diagram of the programming test method of the phase change memory in the prior art, wherein the yield in the diagram A is mostly 100%, and the yield in the diagram B is mostly 0%.
FIG. 4 is a flow chart illustrating a method for programming test of the phase change memory according to one embodiment of the present invention, the method comprising:
step S1: applying a direct current voltage on a grid electrode of the transistor to turn on the transistor, and applying a pulse voltage on a drain electrode of the transistor to carry out an operation step on the phase change memory;
step S2: applying a DC voltage V to the gate of the transistorGTo turn on the transistor and simultaneously apply a DC voltage V to the drainDTo perform a read operation and measure the resistance of the phase change memory resistance cell.
Example two
In order to solve the problems in the prior art, the present invention provides a method for programming and testing a phase change memory, which is further described below with reference to the accompanying drawings. Fig. 1 is a schematic structural diagram illustrating a programming test method of a phase change memory according to an embodiment of the invention; FIG. 2 is a diagram illustrating voltages in a programming test method of a phase change memory according to an embodiment of the invention; fig. 3 is a yield distribution diagram of a programming test method of a phase change memory, wherein a is the yield distribution diagram of the programming test method of the phase change memory in the present invention, and B is the yield distribution diagram of the programming test method of the phase change memory in the prior art.
The invention discloses a programming test method of a phase change memory, wherein the phase change memory comprises a transistor and a phase change storage resistor unit, the drain electrode of the transistor is electrically connected with the phase change storage resistor unit, and the method comprises the following steps:
the invention discloses a programming test method of a phase change memory, wherein the phase change memory comprises a transistor and a phase change storage resistor unit, the drain electrode of the transistor is electrically connected with the phase change storage resistor unit, and the method comprises the following steps:
step S1: applying a direct current voltage on a grid electrode of the transistor to turn on the transistor, and applying a pulse voltage on a drain electrode of the transistor to carry out an operation step on the phase change memory;
step S2: applying a DC voltage V to the gate of the transistorGTo turn on the transistor and simultaneously apply a DC voltage V to the drainDTo perform a read operation and measure the resistance of the phase change memory resistance cell.
In the phase change memory, the transistor may be a transistor commonly found in the art, for example, the transistor includes a semiconductor substrate, a gate structure located on the semiconductor substrate, and basic elements such as a source end and a drain end located at two ends of the gate structure, and may also include other conventional elements, which are not described herein again.
Wherein the phase change memory resistance unit includes:
the semiconductor device comprises a semiconductor substrate 100, wherein a semiconductor device, a metal interconnection structure and an isolation structure are contained in the semiconductor substrate 100;
the lower electrode 101 is positioned in the semiconductor substrate 100, the surface of the lower electrode 101 is flush with the surface of the semiconductor substrate 100, and the lower electrode 101 is electrically connected with a semiconductor device or a metal interconnection structure in the semiconductor substrate 100;
a first dielectric layer 102 on the semiconductor substrate 100; a small electrode 103 positioned in the first dielectric layer 102, wherein the small electrode 103 is electrically connected with the lower electrode 101, the cross-sectional area of the small electrode 103 is smaller than that of the lower electrode 101, and the surface of the small electrode 103 is flush with the surface of the first dielectric layer 102;
a phase change material layer 105 on the small electrode 103; a transition metal layer 106 located on the phase change material layer 105, wherein the transition metal layer 106 functions as an adhesive and a thermal insulator;
an upper electrode 107 located on the transition metal layer 106, wherein the upper electrode 107 is connected with an external circuit; a second dielectric layer 104 covering the phase change material layer 105, the transition metal layer 106 and the upper electrode 107, wherein a surface of the second dielectric layer 104 is flush with a surface of the upper electrode 107, as shown in the right-side diagram of fig. 1.
It should be noted that the structure of the phase change memory in the present invention is merely exemplary and is not limited to the example.
In the invention, the problem that in the prior art, when a grid is opened, a voltage pulse is applied to a drain electrode, and the resistance value of a phase change storage resistor unit is too large, so that the voltage drop is caused in the phase change storage resistor unit, and a transistor is not opened is solved, therefore, a direct current voltage is applied to the grid electrode of the transistor to conduct the transistor, and a substrate and a source electrode of the transistor are grounded, as shown in fig. 1.
The operation comprises an operation step and a reading step, wherein in the operation step, a direct current voltage is applied to a grid electrode of the transistor to turn on the transistor, and a pulse voltage is applied to a drain electrode of the transistor;
performing a read step in which a direct current voltage V is applied to the gate of the transistor after the phase change memory is operatedGTo turn on the transistor and simultaneously apply a DC voltage V to the drainDTo perform a read operation and to measure an amorphous operation current of the phase change memory.
The method can drop voltage on the drain of the transistor, so that the transistor has larger load resistance, thereby realizing that current flows from the transistor to the phase-change material layer, then measuring the current on the drain, and further realizing the amorphous state operation current of the phase-change memory resistance unit, and specifically comprises the following steps:
(1) measuring I of a reference transistor identical to the transistor in the phase change memoryD-VGGraph is shown.
Wherein, the completely same means that the transistor and the reference transistor have the same size and structure to ensure that the transistor and the reference transistor also have completely the same resistance, thereby indirectly measuring the resistance R of the transistor aloneT。
The measuring instrument and the measuring method for the resistance and the current can be selected from instruments and methods commonly used in the art, are not limited to a certain instrument, and are not further described herein.
(2) According to the V in the step S2DAnd said VGIn the said ID-VDFind the V on the graphDAnd said VGCorresponding current IDSince the resistance of the phase change material entering the molten state is very low, I isDAn amorphous state operating current may be approximated.
The method avoids the problem that the voltage drops on the phase change storage resistor unit due to overlarge resistance of the phase change storage resistor unit, and the transistor is not opened, and enables the voltage to drop on the drain electrode of the transistor, so that the transistor has a large load resistor, current flows from the transistor to the phase change material layer, amorphous state operation current measurement of the phase change storage resistor unit is achieved, and necessary parameters are provided for design and preparation of the phase change memory.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (7)
1. A programming test method of a phase change memory, the phase change memory including a transistor and a phase change storage resistance unit, a drain of the transistor being electrically connected to the phase change storage resistance unit, the method comprising:
step S1: applying a direct current voltage on a grid electrode of the transistor to turn on the transistor, and applying a pulse voltage on a drain electrode of the transistor to carry out an operation step on the phase change memory;
step S2: at the gate of the transistorApplying a DC voltage VGTo turn on the transistor and simultaneously apply a DC voltage V to the drainDTo perform a read operation and measure the resistance of the phase change memory resistance cell;
the step S2 includes:
step S21: measuring the current on the drain and according to the DC voltage V applied on the drainDCalculating the total resistance of the phase change memory;
step S22: measuring the resistance of the transistor alone;
step S23: and subtracting the single resistance of the transistor from the total resistance of the phase change memory to obtain the resistance of the phase change memory resistance unit.
2. The method according to claim 1, wherein the substrate of the transistor and the source of the transistor are grounded in the step S1.
3. The method according to claim 1, wherein the resistance of the transistor alone is obtained in step S22 by measuring the resistance of a reference transistor identical to the transistor in the phase change memory.
4. The method of claim 1, wherein the steps S1 and S2 are performed in a loop, and the DC voltage V on the gate is continuously increased during each loopGAnd determining the state of the phase change memory resistance cell according to the resistance of the phase change memory resistance cell obtained in the step S2.
5. The method according to claim 1, wherein step S2 further comprises the step of measuring the amorphous state operation current of the phase change memory.
6. The method of claim 5, wherein measuring the amorphous state operating current of the phase change memory comprises:
measuring I of a reference transistor identical to the transistor in the phase change memoryD-VGA graph;
according to the V in the step S2DAnd said VGIn the said ID-VDFind the V on the graphDAnd said VGCorresponding current IDTo obtain the amorphous operation current.
7. The method of claim 1, wherein the phase change memory resistive cell comprises at least an upper electrode and a lower electrode and a layer of phase change material between the upper electrode and the lower electrode.
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| CN101562050A (en) * | 2008-01-07 | 2009-10-21 | 旺宏电子股份有限公司 | Phase change memory dynamic resistance test and manufacturing methods |
| CN102354537A (en) * | 2011-07-06 | 2012-02-15 | 华中科技大学 | Method and system for testing chip of phase change memory |
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| CN105336378A (en) * | 2014-07-03 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Phase change memory unit test structure and method and phase change memory |
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| CN101562050A (en) * | 2008-01-07 | 2009-10-21 | 旺宏电子股份有限公司 | Phase change memory dynamic resistance test and manufacturing methods |
| CN102354537A (en) * | 2011-07-06 | 2012-02-15 | 华中科技大学 | Method and system for testing chip of phase change memory |
| CN102831935A (en) * | 2012-05-18 | 2012-12-19 | 华中科技大学 | Pulse I-V (intravenous) characteristic testing method and device of phase change memory unit |
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