CN106548979A - The engraving method of stacking inoranic membrane - Google Patents
The engraving method of stacking inoranic membrane Download PDFInfo
- Publication number
- CN106548979A CN106548979A CN201611236937.4A CN201611236937A CN106548979A CN 106548979 A CN106548979 A CN 106548979A CN 201611236937 A CN201611236937 A CN 201611236937A CN 106548979 A CN106548979 A CN 106548979A
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- inoranic membrane
- layer
- stacking
- etching
- laminated
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters
Abstract
The present invention provides a kind of engraving method of stacking inoranic membrane, it is etched to being laminated inoranic membrane by the way of dry ecthing is combined with wet etching, form the photoresist layer of patterning first on stacking inoranic membrane, with the photoresist layer as shielding layer, dry ecthing is carried out to being laminated inoranic membrane, when the silica bottom layer of basecoat in the stacking inoranic membrane is etched into, stop dry ecthing, then wet etching is carried out to remaining silica bottom layer using buffer oxide etch liquid, the pattern of correspondence photoresist layer forms via on the stacking inoranic membrane；The uniformity of each region etch effect on same substrate can be improved, it is to avoid prior art each region when formation via especially deep hole on inoranic membrane is laminated etches phenomenon that is uneven and etching into lower membrane to be occurred.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of engraving method of stacking inoranic membrane.
Background technology
Thin film transistor (TFT) (Thin Film Transistor, TFT) is current liquid crystal indicator (Liquid Crystal
Display, LCD) and active matrix drive type organic electroluminescence display device and method of manufacturing same (Active Matrix Organic Light-
Emitting Diode, AMOLED) in main driving element, the display performance of direct relation panel display apparatus.
Whether LCD or AMOLED include a tft array substrate.In the manufacturing process of tft array substrate, make
With etching gas, using organic membrane such as photoresists as mask, to silicon oxide (SiO2) film and silicon nitride (SiNx) film stacking
The dry etching process that film is etched, wherein, etching gas is to silicon oxide film and silicon nitride film relative to the selection to photoresist
Etching is high, i.e., have selective wet etching to silicon oxide film and silicon nitride film, such that it is able in silicon oxide film and silicon nitride film
The via of pattern form is formed on stacked film.For example, the step of making at present thin film transistor (TFT) is generally, the shape successively on substrate
Into grid, gate insulation layer, active layer, drain electrode, source electrode and passivation layer, photoresist (PR) layer is deposited over the passivation layer, by light
Photoresist layer carries out dry ecthing to passivation layer, obtains via over the passivation layer according to the pattern of photoresist layer, wherein, the passivation layer
For the stacking inoranic membrane of silicon oxide film and silicon nitride film, the gate insulation layer is silicon nitride film.
However, due to the limitation of prior art, in actual production process, as shown in figure 1, not same district on same substrate
Domain passes through the speed of 107 dry ecthings of passivation layer of 109 pairs of stacking inoranic membranes of photoresist layer and differs, so as to cause etched thickness
Inhomogeneities；In wherein Fig. 1, a-quadrant corresponds to the slower region of dry etching rate, at the end of dry ecthing, to passivation layer
The depth of 107 etchings not enough and does not form via in passivation layer 107；In Fig. 1, B regions are corresponding to the moderate area of dry etching rate
Domain, at the end of dry ecthing, the depth etched to passivation layer 107 suitably and just forms via on passivation layer 107；C in Fig. 1
Region corresponds to dry etching rate region faster, and at the end of dry ecthing, not only on passivation layer 107, etching defines via
The gate insulation layer 103 of the silicon nitride material of lower floor is accordingly etched into also, then corresponding to the uneven situation of above-mentioned dry ecthing, especially
When being larger for thickness stacking inoranic membrane and needing to be formed on via of the deeper depth more than 1 μm, above-mentioned etching
Uneven situation becomes apparent from, accordingly, it would be desirable to improve to the engraving method of existing stacking inoranic membrane.
In addition, wet etching is also indispensable technique in tft array substrate processing, in wet etching process, usual profit
The oxide layer portion not covered by photoresistance is removed with buffer oxide etch liquid (Buffered Oxide Etch, BOE), so as to
Reach the purpose of etching.The composition of above-mentioned BOE etching solutions is Fluohydric acid., ammonium fluoride and water.
The content of the invention
It is an object of the invention to provide a kind of engraving method of stacking inoranic membrane, is combined with wet etching using dry ecthing
Mode is etched to being laminated inoranic membrane, and prior art can be avoided each when formation via especially deep hole on inoranic membrane is laminated
Region etches phenomenon that is uneven and etching into lower membrane to be occurred.
For achieving the above object, the present invention provides a kind of engraving method of stacking inoranic membrane, comprises the steps：
Step 1, offer substrate, the substrate includes basement membrane and the stacking inoranic membrane on the basement membrane, described
Stacking inoranic membrane includes least one layer of silicon oxide layer and least one layer of silicon nitride layer；In the stacking inoranic membrane, the oxygen
By the silicon oxide layer of basecoat, intersecting is arranged SiClx layer successively upwards with silicon nitride layer, the oxidation of the basecoat
Silicon layer is silica bottom layer；
Step 2, form the photoresist layer of patterning on the stacking inoranic membrane, with the photoresist layer as shielding layer,
Dry ecthing is carried out to the stacking inoranic membrane, when the silica bottom layer of the stacking inoranic membrane is etched into, stops dry ecthing；
Step 3, offer buffer oxide etch liquid, are carried out to remaining silica bottom layer using buffer oxide etch liquid
Wet etching, on the stacking inoranic membrane, the pattern of correspondence photoresist layer forms via.
In the step 2, the material for carrying out adopted etching gas during dry ecthing relative to photoresist layer is to the stacking
The composition that the material of inoranic membrane has selective wet etching, the etching gas includes fluorinated hydrocarbon compound, oxygen and indifferent gas
Body, the noble gases be helium, argon, neon, krypton, one or more in xenon.
The buffer oxide etch liquid phase provided in the step 3 is for the material of the material to silicon oxide layer of photoresist layer
With selective wet etching, the composition of the buffer oxide etch liquid includes Fluohydric acid., ammonium fluoride and water.
The engraving method of described stacking inoranic membrane, in curved surface OLED display panel to the layer in requisition for sweep
The etching of folded inoranic membrane.
The engraving method of described stacking inoranic membrane, for being etched to the passivation layer of tft array substrate.
In the step 3, wet etching is carried out to the silica bottom layer by the way of spray.
In the step 2, the photoresist layer of patterning is formed using gold-tinted processing procedure, the gold-tinted processing procedure includes carrying out successively
Photoresist painting process, exposure process and developing procedure.
The depth of the via formed in the step 3 is more than 1 μm.
Beneficial effects of the present invention：The present invention provide a kind of stacking inoranic membrane engraving method, using dry ecthing with it is wet
The mode that etching is combined is etched to being laminated inoranic membrane, forms the photoresist layer of patterning first on stacking inoranic membrane, with
The photoresist layer be shielding layer, to be laminated inoranic membrane carry out dry ecthing, to etch into it is described stacking inoranic membrane in basecoat
Silica bottom layer when, stop dry ecthing, wet corrosion is carried out to remaining silica bottom layer using buffer oxide etch liquid then
Carve, on the stacking inoranic membrane, the pattern of correspondence photoresist layer forms via；Each region erosion on same substrate can be improved
Carve the uniformity of effect, it is to avoid prior art be laminated form via especially deep hole on inoranic membrane when the etching of each region it is uneven and
The phenomenon for etching into lower membrane occurs.
Description of the drawings
In order to be able to be further understood that the feature and technology contents of the present invention, refer to below in connection with the detailed of the present invention
Illustrate and accompanying drawing, but accompanying drawing only provides with reference to and illustrates to use, not for being any limitation as to the present invention.
In accompanying drawing,
Fig. 1 be using it is existing stacking inoranic membrane engraving method on the same substrate zones of different dry etching rate not
Schematic diagram that is same and causing etched thickness inequality；
Fig. 2 is the schematic flow sheet of the engraving method of the stacking inoranic membrane of the present invention；
The schematic diagram of the step of Fig. 3-4 is the engraving method of the stacking inoranic membrane of the present invention 2；
The schematic diagram of the step of Fig. 5 is the engraving method of the stacking inoranic membrane of the present invention 3.
Specific embodiment
Further to illustrate the technological means taken of the invention and its effect, below in conjunction with being preferable to carry out for the present invention
Example and its accompanying drawing are described in detail.
Fig. 2 is referred to, the present invention provides a kind of engraving method of stacking inoranic membrane, comprises the steps：
Step 1, substrate 10 is provided, the substrate 10 includes basement membrane 11, and being layered without on the basement membrane 11
Machine film 12, the stacking inoranic membrane 12 include least one layer of silicon oxide layer 121, and least one layer of silicon nitride layer 122；It is described
In stacking inoranic membrane 12, the silicon oxide layer 121 and silicon nitride layer 122 by the silicon oxide layer 121 of basecoat upwards successively
Intersecting is arranged, and the silicon oxide layer 121 of the basecoat is silica bottom layer 121 '.
Step 2, Fig. 3 and Fig. 4 is referred to, the photoresist layer 15 of patterning is formed on the stacking inoranic membrane 12, with institute
Photoresist layer 15 is stated for shielding layer, dry ecthing is carried out to the stacking inoranic membrane 12, to etching into the stacking inoranic membrane 12
During silica bottom layer 121 ', i.e., above described silica bottom layer 121 ', all of silicon oxide layer 121 and silicon nitride layer 122 be not by institute
State photoresist layer 15 covering part it is etched when, stop dry ecthing.
Specifically, in the step 2, carry out during dry ecthing adopted etching gas and be in existing dry etching process to oxygen
Silicon nitride material film and silicon nitride material film carry out the etching gas of dry ecthing, and the etching gas is relative to photoresist layer 15
Material generally includes fluoro hydrocarbonylation to the composition that the material of the stacking inoranic membrane 12 has selective wet etching, the etching gas
Compound, oxygen and noble gases, wherein, the noble gases be helium, argon, neon, krypton, one or more in xenon.
Specifically, in the step 2, the photoresist layer 15 of patterning, the gold-tinted processing procedure bag are formed using gold-tinted processing procedure
Include photoresist painting process, exposure process and the developing procedure for carrying out successively.
Step 3, refer to Fig. 5, there is provided buffer oxide etch liquid (BOE), using buffer oxide etch liquid to residue
Silica bottom layer 121 ' carry out wet etching, it is described stacking inoranic membrane 12 on correspondence photoresist layer 15 pattern formed via
125。
Specifically, to silicon oxide in the buffer oxide etch liquid for providing in the step 3 as existing wet etching process
Material membrane carries out the etching solution of selective etch, and the buffer oxide etch liquid phase is for the material of photoresist layer 15 is to oxidation
The composition that the material of silicon layer 121 has selective wet etching, the buffer oxide etch liquid includes Fluohydric acid., ammonium fluoride, He Shui.
Specifically, existing wet etching process is divided into two kinds of immersion type and fountain (Spray Mode), wherein fountain
Effect of the etching speed in the horizontal direction less than the etching speed in vertical direction can be realized, in order to avoid etched
Cause the size in the horizontal direction of via 125 larger as the etching speed in horizontal direction is excessive in journey, the present invention is excellent
Choosing carries out wet etching to the silica bottom layer 121 ' by the way of spray.
Specifically, easily there is each region etching using dry ecthing when formation via on inoranic membrane is laminated in prior art
Phenomenon that is uneven and etching into lower membrane occurs, especially when the hole depth excessively of required formation is this bad compared with when being more than 1 μm deeply
Phenomenon is especially apparent, therefore the engraving method of the stacking inoranic membrane of the present invention, for the bad of prior art, is applied especially to institute
The via 125 that need to be formed is deep hole, and its depth is more than in the middle of 1 μm of scene.
Specifically, the engraving method of stacking inoranic membrane of the invention, can be used for flexible (bendable) OLED and shows
Show on panel in requisition for sweep stacking inoranic membrane etching, by by OLED display panel in requisition for bending section
Etching away for the stacking inoranic membrane for dividing, can suppress the generation of OLED display panel fragmentation (Crack) phenomenon in BENDING PROCESS.
Specifically, the engraving method of stacking inoranic membrane of the invention, it is also possible to for entering to the passivation layer of tft array substrate
Row etching, the gate insulation layer of the silicon nitride material that can avoid lower floor is etched in etching process.
In sum, a kind of engraving method of stacking inoranic membrane that the present invention is provided, is combined with wet etching using dry ecthing
Mode be etched to being laminated inoranic membrane, form the photoresist layer of patterning on stacking inoranic membrane first, with the photoetching
Glue-line is shielding layer, carries out dry ecthing to being laminated inoranic membrane, to the silicon oxide for etching into basecoat in the stacking inoranic membrane
During bottom, stop dry ecthing, wet etching is carried out to remaining silica bottom layer using buffer oxide etch liquid then, described
On stacking inoranic membrane, the pattern of correspondence photoresist layer forms via；The equal of each region etch effect on same substrate can be improved
Even property, it is to avoid prior art each region when formation via especially deep hole on inoranic membrane is laminated etches uneven and etches into lower floor
The phenomenon of film occurs.
The above, for the person of ordinary skill of the art, can be with technology according to the present invention scheme and technology
Other various corresponding changes and deformation are made in design, and all these changes and deformation should all belong to the claims in the present invention
Protection domain.
Claims (8)
1. it is a kind of stacking inoranic membrane engraving method, it is characterised in that comprise the steps：
Step 1, substrate (10) is provided, the substrate (10) includes basement membrane (11), and layer on the basement membrane (11)
Folded inoranic membrane (12), stacking inoranic membrane (12) is including least one layer of silicon oxide layer (121), and least one layer of silicon nitride
Layer (122)；In stacking inoranic membrane (12), the oxidation of the silicon oxide layer (121) and silicon nitride layer (122) by basecoat
Silicon layer (121) plays upwards intersecting successively and arranges, and the silicon oxide layer (121) of the basecoat is silica bottom layer
(121’)；
Step 2, the photoresist layer (15) that patterning is formed on stacking inoranic membrane (12), with the photoresist layer (15) be
Shielding layer, carries out dry ecthing to stacking inoranic membrane (12), to the silica bottom layer for etching into stacking inoranic membrane (12)
When (121 '), stop dry ecthing；
Step 3, offer buffer oxide etch liquid, are entered to remaining silica bottom layer (121 ') using buffer oxide etch liquid
Row wet etching, on stacking inoranic membrane (12), the pattern of correspondence photoresist layer (15) forms via (125).
2. the engraving method of inoranic membrane is laminated as claimed in claim 1, it is characterised in that in the step 2, carry out dry ecthing
When adopted etching gas relative to photoresist layer (15) material to it is described stacking inoranic membrane (12) material have select erosion
Quarter property, the composition of the etching gas include fluorinated hydrocarbon compound, oxygen and noble gases, the noble gases be helium, argon,
One or more in neon, krypton, xenon.
3. the engraving method of inoranic membrane is laminated as claimed in claim 1, it is characterised in that the buffering provided in the step 3
Oxide etching liquid phase has selective wet etching to the material of silicon oxide layer (121) for the material of photoresist layer (15), described
The composition of buffer oxide etch liquid includes Fluohydric acid., ammonium fluoride, He Shui.
4. the engraving method of inoranic membrane is laminated as claimed in claim 1, it is characterised in that for curved surface OLED display panel
Etching to the stacking inoranic membrane in requisition for sweep.
5. the engraving method of inoranic membrane is laminated as claimed in claim 1, it is characterised in that for the blunt of tft array substrate
Change layer to be etched.
6. the engraving method of inoranic membrane is laminated as claimed in claim 1, it is characterised in that in the step 3, using spray
Mode carries out wet etching to the silica bottom layer (121 ').
7. the engraving method of inoranic membrane is laminated as claimed in claim 1, it is characterised in that in the step 2, using gold-tinted system
Journey forms the photoresist layer (15) of patterning, photoresist painting process that the gold-tinted processing procedure includes carrying out successively, exposure process,
And developing procedure.
8. the engraving method of inoranic membrane is laminated as claimed in claim 1, it is characterised in that the via formed in the step 3
(125) depth is more than 1 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611236937.4A CN106548979A (en) | 2016-12-28 | 2016-12-28 | The engraving method of stacking inoranic membrane |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611236937.4A CN106548979A (en) | 2016-12-28 | 2016-12-28 | The engraving method of stacking inoranic membrane |
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| Publication Number | Publication Date |
|---|---|
| CN106548979A true CN106548979A (en) | 2017-03-29 |
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ID=58396301
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| Application Number | Title | Priority Date | Filing Date |
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| CN201611236937.4A Pending CN106548979A (en) | 2016-12-28 | 2016-12-28 | The engraving method of stacking inoranic membrane |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR3091410A1 (en) * | 2018-12-26 | 2020-07-03 | Stmicroelectronics (Crolles 2) Sas | Etching process |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007311747A (en) * | 2006-04-18 | 2007-11-29 | Sharp Corp | Method of manufacturing semiconductor device, semiconductor device, and display |
| CN105492973A (en) * | 2013-08-28 | 2016-04-13 | 日产化学工业株式会社 | Pattern forming method using resist underlayer film |
| CN106206613A (en) * | 2016-08-24 | 2016-12-07 | 昆山工研院新型平板显示技术中心有限公司 | A kind of flexible display substrates and preparation method thereof |
-
2016
- 2016-12-28 CN CN201611236937.4A patent/CN106548979A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007311747A (en) * | 2006-04-18 | 2007-11-29 | Sharp Corp | Method of manufacturing semiconductor device, semiconductor device, and display |
| CN105492973A (en) * | 2013-08-28 | 2016-04-13 | 日产化学工业株式会社 | Pattern forming method using resist underlayer film |
| CN106206613A (en) * | 2016-08-24 | 2016-12-07 | 昆山工研院新型平板显示技术中心有限公司 | A kind of flexible display substrates and preparation method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR3091410A1 (en) * | 2018-12-26 | 2020-07-03 | Stmicroelectronics (Crolles 2) Sas | Etching process |
| US11469095B2 (en) | 2018-12-26 | 2022-10-11 | Stmicroelectronics (Crolles 2) Sas | Etching method |
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