CN106547513B - Utilize the defence differential power consumption analysis adder of sensitive scale-up version logic - Google Patents

Utilize the defence differential power consumption analysis adder of sensitive scale-up version logic Download PDF

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CN106547513B
CN106547513B CN201610892236.XA CN201610892236A CN106547513B CN 106547513 B CN106547513 B CN 106547513B CN 201610892236 A CN201610892236 A CN 201610892236A CN 106547513 B CN106547513 B CN 106547513B
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input
door
oxide
metal
semiconductor
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CN106547513A (en
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汪鹏君
钱浩宇
张跃军
丁代鲁
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Ningbo University
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Ningbo University
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Pure & Applied Mathematics (AREA)
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  • Computational Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Optimization (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Thin Film Transistor (AREA)

Abstract

The invention discloses a kind of defence differential power consumption analysis adder using sensitive scale-up version logic, by four two inputs with it is non-/ with door, eight two input exclusive or/with or door, 22 phase inverters and carry look ahead generation circuits constitute adder；Advantage is using TSMC 65nm CMOS technology, simulation analysis is carried out to circuit by Spectre tool, the experimental results showed that adder of the invention has correct logic function, compared to conventional adders circuit in power consumption independence performance boost 97%, differential power consumption analysis can be effectively resisted.

Description

Utilize the defence differential power consumption analysis adder of sensitive scale-up version logic
Technical field
The present invention relates to a kind of adders, more particularly, to a kind of defence differential power consumption using sensitive scale-up version logic point Analyse adder.
Background technique
With the development of integrated circuit and computer technology, cipherware is widely used in the neck such as smart card, e-commerce Domain greatly ensure that the safety of system.However, cipherware is when handling different data, energy consumption, runing time and The physical messages such as electromagnetic radiation have certain correlation with handled data.Then, attacker usually utilizes these physics Information attack cipherware obtains key information, and the method is referred to as side-channel attacks (Side Channel Attack, SCA).? In a series of side-channel attacks technologies, differential power consumption analysis (Differential Power Analysis, DPA) technology is a kind of Common and effectively side-channel attacks method, seriously threatens the safety of cipherware.There has been proposed many differences in recent years Transfer state double track preliminary filling logic realizes anti-DPA attack, such as tri-state double track preliminary filling logic (Three-Phase Dual-Rail Pre-charge Logic, TDPL), insulation dynamic difference logic (Adiabatic Dynamic Differential Logic, ) and sensitive scale-up version logic (Sense Amplifier Based Logic, SABL) etc. ADDL.Compared to SABL, TDPL is by drawing Enter additional discharge regime balance power consumption, increase the consumption of its energy, if attacker modifies clock and generates individual discharge regime Power consumption then substantially reduces the anti-DPA attack performance of TDPL；ADDL timing control is complicated, and while interact with cmos circuit need to be designed and answer Miscellaneous interface circuit.Due to have many advantages, such as good anti-DPA attack performance, with cmos circuit good compatibility, SABL gradually at For the main method of defence DPA attack.
Add operation is most common arithmetic operation, it is theoretical it is superior, subtract and can be converted into add operation with division operation.Addition Device is the most basic component for forming arithmetic unit, is widely used in handling the number of different word lengths in various digital enciphering systems According to.Since static complementary cmos circuit only just consumes energy, this asymmetric function when 0 → 1 overturning occurs for output signal Consumption feature successfully cracks conventional cipher device for differential power consumption analysis and provides breach.
In view of this, using SABL consumption energy and the mutually independent feature of handled data, designing one kind can defend DPA to attack That hits is of great significance using the defence differential power consumption analysis adder of sensitive scale-up version logic.
Summary of the invention
Technical problem to be solved by the invention is to provide one kind can defend DPA attack utilize sensitive scale-up version logic Defence differential power consumption analysis adder.
The present invention solves technical solution used by above-mentioned technical problem：A kind of defence using sensitive scale-up version logic Differential power consumption analysis adder, including the one or two input with it is non-/ with door, the two or two input with it is non-/ with door, the three or two input with It is non-/ with door, the four or two input with it is non-/ with door, the one or two input exclusive or/with or door, the two or two input exclusive or/with or door, third Two input exclusive or/with or door, the four or two input exclusive or/with or door, the five or two input exclusive or/with or door, the six or two input exclusive or/ Same or door, the seven or two input exclusive or/same or door, the eight or two input exclusive or/same or door, the first phase inverter, the second phase inverter, third Phase inverter, the 4th phase inverter, the 5th phase inverter, hex inverter, the 7th phase inverter, the 8th phase inverter, the 9th phase inverter, the tenth Phase inverter, the 11st phase inverter, the 12nd phase inverter, the 13rd phase inverter, the 14th phase inverter, the 15th phase inverter, the tenth Hex inverter, the 17th phase inverter, eighteen incompatibilities phase device, the 19th phase inverter, the 20th phase inverter, the 21st phase inverter, 22nd phase inverter and carry look ahead generation circuit；The carry look ahead generation circuit include the five or two input with it is non-/ with Door, the six or two input with it is non-/ with door, the seven or two input with it is non-/ with door, the eight or two input with it is non-/ with door, the 9th 2 input with It is non-/ with door, the 12nd input with it is non-/ with door, the 11st input with it is non-/ with door, the 12nd input with it is non-/ with door, the tenth Three or two input with it is non-/ with door, the 14th input with it is non-/ with door, the one or two input or it is non-/ or door, the two or two input or it is non-/ or Door, the three or two input or it is non-/ or door, the four or two input or it is non-/ or door, the five or two input or it is non-/ or door, the six or two input or Non-/or door, the one or three input or non-/ or door, the two or three input or non-/ or door, the 23rd phase inverter, the 24th reverse phase Device, the 25th phase inverter, the 20th hex inverter, the 27th phase inverter, the second eighteen incompatibilities phase device, the 29th reverse phase Device, the 30th phase inverter, the 31st phase inverter, the 32nd phase inverter, the 33rd phase inverter, the 34th phase inverter, 35th phase inverter, the 30th hex inverter, the 37th phase inverter, third eighteen incompatibilities phase device, the 39th phase inverter, 40 phase inverters, the 41st phase inverter, the 42nd phase inverter, the 43rd phase inverter, the 44th phase inverter, the 40th Five phase inverters, the 40th hex inverter, the 47th phase inverter, the 4th eighteen incompatibilities phase device, the 49th phase inverter and the 50th Phase inverter；Described one or two input with it is non-/ with door, the two or two input with it is non-/ with door, the three or two input with It is non-/ with door, described four or two input with it is non-/ with door, the five or two input with it is non-/ with door, the six or two input With it is non-/ with door, described seven or two input with it is non-/ with door, the described the 8th 2 input with it is non-/ with door, the described the 9th 2 defeated Enter with it is non-/ with door, described 12nd input with it is non-/ with door, the 11st input with it is non-/ with door, the described the tenth Two or two inputs with it is non-/ with door, described 13rd input with it is non-/ with door and the 14th input with it is non-/ with door point It Ju You not first input end, the first inverting input terminal, the second input terminal, the second inverting input terminal, clock end, NAND Logic output End and and logic output terminal；Described one or the two input exclusive or/with or door, the two or the two input exclusive or/with or it is door, described The three or two input exclusive or/with or door, described four or the two input exclusive or/with or door, the five or the two input exclusive or/with or Door, the six or the two input exclusive or/same or door, the seven or the two input exclusive or/same or door and the eight or two input Exclusive or/same or door is respectively provided with first input end, the first inverting input terminal, the second input terminal, the second inverting input terminal, clock End, same or logic output terminal and XOR logic output end；Described one or two input or non-/ or door, the two or two input Or non-/ or it is door, described three or two input or non-/ or door, the four or two input or non-/ or door, the described the 5th 2 defeated Enter or non-/ or door and the six or two input or non-/ or door be respectively provided with first input end, the first inverting input terminal, second Input terminal, the second inverting input terminal, clock end, or logic output end and/or logic output terminal；Described one or three input or It is non-/ or door and described two or three input or non-/ or door there is first input end, the first inverting input terminal, the second input terminal, the Two inverting input terminals, third input terminal, third inverting input terminal, clock end, or logic output end and/or logic output terminal；Institute The five or two input stated with it is non-/ with the clock end of door, the six or two input with it is non-/ with the clock end of door, the described the 7th Two inputs with it is non-/ with the clock end of door, the eight or two input with it is non-/ with the clock end of door, the 9th 2 input with It is non-/ with the clock end of door, the 12nd input with it is non-/ with the clock end of door, the 11st input and non-/ and door Clock end, described 12nd input with it is non-/ with the clock end of door, the 13rd input with it is non-/ with door when Zhong Duan, described 14th input and non-/ clock end, institute with the clock end of door, the one or two input or non-/ or door The clock end of the two or two input stated or non-/ or door, the clock end of described three or two input or non-/ or door, the described the 4th The clock end of two inputs or non-/ or door, the clock end of described five or two input or non-/ or door, the six or two input or Non-/or the clock end of door, the clock end of described one or three input or non-/ or door and the two or three input or non-/ or door Clock end connection and its connecting pin be the carry look ahead generation circuit clock end；Described five or two input with it is non-/ With the first input end of door, the 11st input with it is non-/ with the first input end of door, the 13rd input with It is non-/ with the first input end of door and described 14th input with it is non-/ connect with the first input end of door and its connecting pin be 4th carry of the carry look ahead generation circuit transmits signal input part, transmits signal for inputting the 4th carry；It is described The five or two input with it is non-/ with the first inverting input terminal of door, the described the 11st input with it is non-/ defeated with the first reverse phase of door Enter end, described 13rd input with it is non-/ with the first inverting input terminal of door and the 14th input and non-/ and door The first inverting input terminal connection and its connecting pin be the carry look ahead generation circuit the 4th reverse phase carry transmit signal Input terminal transmits signal for inputting the 4th reverse phase carry；Described five or two input and non-/ the second input terminal with door and institute The four or two input stated or non-/ or the second input terminal connection of door and its connecting pin is the of the carry look ahead generation circuit Three carries generate signal input part, generate signal for inputting third carry；Described five or two input with it is non-/ with door second Second inverting input terminal of inverting input terminal and described four or two input or non-/ or door connect and its connecting pin is described surpasses The third reverse phase carry of advanced potential generation circuit generates signal input part, generates signal for inputting third reverse phase carry；It is described The six or two input with it is non-/ with the first input end of door, the described the 9th 2 input with it is non-/ with the first input end of door and described The 12nd input with it is non-/ connect with the first input end of door and its connecting pin is the of the carry look ahead generation circuit Three carries transmit signal input part, for inputting third carry transmission signal；Described six or two input with it is non-/ with door first Inverting input terminal, described 9th 2 input with it is non-/ with the first inverting input terminal of door and the 12nd input with it is non-/ It is connect with the first inverting input terminal of door and its connecting pin is the third reverse phase carry transmission of the carry look ahead generation circuit Signal input part, for inputting third reverse phase carry transmission signal；Described six or two input and non-/ the second input terminal with door Connect with the third input terminal of described one or three input or non-/ or door and its connecting pin is the carry look ahead generation circuit The second carry generate signal input part, for input the second carry generate signal；Described six or two input with it is non-/ with door The third inverting input terminal of second inverting input terminal and described one or three input or non-/ or door connects and its connecting pin is described Carry look ahead generation circuit the second reverse phase carry generate signal input part, for input the second reverse phase carry generate signal； Described seven or two input with it is non-/ with the first input end of door and the 12nd input and non-/ first input end with door Connection and its connecting pin be the carry look ahead generation circuit the second carry transmit signal input part, for input second into Position transmission signal；Described seven or two input with it is non-/ with the first inverting input terminal of door and the 12nd input with it is non-/ with First inverting input terminal of door connects and its connecting pin is the second reverse phase carry transmission letter of the carry look ahead generation circuit Number input terminal transmits signal for inputting the second reverse phase carry；Described seven or two input with it is non-/ with the second input terminal of door and Described five or two input or non-/ or the second input terminal connection of door and its connecting pin is the carry look ahead generation circuit First carry generates signal input part, generates signal for inputting the first carry；Described seven or two input with it is non-/ with door the Second inverting input terminal of two inverting input terminals and described five or two input or non-/ or door connect and its connecting pin is described First reverse phase carry of carry look ahead generation circuit generates signal input part, generates signal for inputting the first reverse phase carry；Institute The eight or two input stated with it is non-/ with the first carry that the first input end of door is the carry look ahead generation circuit transmit signal Input terminal transmits signal for inputting the first carry；Described eight or two input with it is non-/ with the first inverting input terminal of door be institute First reverse phase carry of the carry look ahead generation circuit stated transmits signal input part, for inputting the first reverse phase carry transmission letter Number；Described eight or two input with it is non-/ believe with low order carry that the second input terminal of door is the carry look ahead generation circuit Number input terminal, for inputting low order carry signal；Described eight or two input with it is non-/ with the second inverting input terminal of door be described Carry look ahead generation circuit reverse phase low order carry signal input part, be used for input inversion low order carry signal；Described Five or two inputs with it is non-/ connect with the input terminal of the NAND Logic output end of door and the 23rd phase inverter, described the Five or two inputs with it is non-/ connect with the input terminal of logic output terminal and the 24th phase inverter with door, the described the 6th Two inputs with it is non-/ connect with the input terminal of the NAND Logic output end of door and the 25th phase inverter, the described the 6th Two inputs with it is non-/ connect with the input terminal of logic output terminal and the 20th hex inverter with door, the described the 7th 2 Input with it is non-/ connect with the input terminal of the NAND Logic output end of door and the 27th phase inverter, the described the 7th 2 Input with it is non-/ connect with the input terminal of logic output terminal and the second eighteen incompatibilities phase device with door, the described the 8th 2 is defeated Enter with it is non-/ connect with the input terminal of the NAND Logic output end of door and the 29th phase inverter, the described the 8th 2 is defeated Enter with it is non-/ connect with the input terminal of logic output terminal and the 30th phase inverter with door, the 9th 2 input with It is non-/ to be connect with the input terminal of the NAND Logic output end of door and the 31st phase inverter, described 9th 2 input with It is non-/ to connect with door with the input terminal of logic output terminal and the 32nd phase inverter, the 12nd input with it is non-/ Connect with the input terminal of the NAND Logic output end of door and the 33rd phase inverter, described 12nd input with it is non-/ With being connect with the input terminal of logic output terminal and the 34th phase inverter for door, described 11st input with it is non-/ Connect with the input terminal of the NAND Logic output end of door and the 35th phase inverter, described 11st input with It is non-/ to connect with door with the input terminal of logic output terminal and the 30th hex inverter, the 12nd input with The 12nd non-/ to be connect with the input terminal of the NAND Logic output end of door and the 37th phase inverter, described input With it is non-/ connect with the input terminal of logic output terminal and the third eighteen incompatibilities phase device with door, the 13rd input With it is non-/ connect with the input terminal of the NAND Logic output end of door and the 39th phase inverter, the described the 13rd is defeated Enter with it is non-/ connect with the input terminal of logic output terminal and the 40th phase inverter with door, the 14th input With it is non-/ connect with the input terminal of the NAND Logic output end of door and the 41st phase inverter, the described the 14th is defeated Enter with it is non-/ connect with the input terminal of logic output terminal and the 42nd phase inverter with door, the one or two input Or it is non-/ or the or logic output end of door connected with the input terminal of the 43rd phase inverter, described one or two input Or it is non-/ door or logic output terminal connected with the input terminal of the 44th phase inverter, described two or two input or It is non-/ or the or logic output end of door connected with the input terminal of the 45th phase inverter, described two or two input or It is non-/ door or logic output terminal connected with the input terminal of the 40th hex inverter, described three or two input or non-/ Or the or logic output end of door is connected with the input terminal of the 47th phase inverter, described three or two input or non-/ Door or logic output terminal connected with the input terminal of the 4th eighteen incompatibilities phase device, described four or two input or non-/ or The or logic output end of door connect with the input terminal of the 49th phase inverter, the described 4th 2 input or non-/ or Door or logic output terminal connected with the input terminal of the 50th phase inverter, the output end of the 23rd phase inverter It is connected with described two or two input or non-/ or the first input end of door, the output end of the 24th phase inverter and institute The two or two input stated or non-/ or the first inverting input terminal connection of door, it is the output end of the 25th phase inverter, described The 11st input with it is non-/ connect with the second input terminal of door and the four or two input or non-/ or the first input end of door Connect, the output end of the 20th hex inverter, described 11st input with it is non-/ with the second inverting input terminal of door and Described four or two input or non-/ or the first inverting input terminal connection of door, the output end of the 27th phase inverter, institute The 9th 2 input stated with it is non-/ connect with the second input terminal of door and the one or three input or non-/ or the second input terminal of door It connects, the output end of the second eighteen incompatibilities phase device, described 9th 2 input and non-/ the second inverting input terminal with door and institute The one or three input stated or non-/ or the second inverting input terminal connection of door, it is the output end of the 29th phase inverter, described The 12nd input with it is non-/ inputted with the second input terminal of door and the described 5th 2 or non-/ or the first input end of door connect, The output end of 30th phase inverter, described 12nd input with it is non-/ with the second inverting input terminal of door and described Five or two input or non-/ or the first inverting input terminal connection of door, the output end of the 31st phase inverter, described the 13 inputs with it is non-/ inputted with the second input terminal of door and the described 3rd 2 or non-/ or the second input terminal of door connect, institute The output end for the 32nd phase inverter stated, described 13rd input with it is non-/ with the second inverting input terminal of door and described The three or two input or it is non-/ or door the connection of the second inverting input terminal, it is the output end of the 33rd phase inverter, described 12nd input with it is non-/ inputted with the second input terminal of door and the described 1st or non-/ or the first input end of door connect, The output end of 34th phase inverter, described 12nd input and non-/ the second inverting input terminal with door and institute The one or three input stated or non-/ or the first inverting input terminal connection of door, the output end of the 35th phase inverter and institute The one or two input stated or non-/ or the second input terminal connection of door, the output end of the 30th hex inverter and described One or two input or non-/ or the second inverting input terminal connection of door, the output end of the 37th phase inverter, described the 14 inputs with it is non-/ inputted with the second input terminal of door and the described 3rd 2 or non-/ or the first input end of door connect, institute The output end for the third eighteen incompatibilities phase device stated, described 14th input with it is non-/ with the second inverting input terminal of door and described The three or two input or it is non-/ or door the connection of the first inverting input terminal, the output end of the 39th phase inverter and described The one or two input or it is non-/ or door first input end connection, the output end and described first of the 40th phase inverter Two input or it is non-/ or door the first inverting input terminal connection, the output end and described second of the 41st phase inverter Three inputs or non-/ or the first input end connection of door, the output end of the 42nd phase inverter and the described the 2nd 3 defeated Enter or non-/ or door the connection of the first inverting input terminal, the output end of the 43rd phase inverter and the described the 2nd 3 defeated Enter or non-/ or door the connection of the second input terminal, the output end of the 44th phase inverter and the two or three input or It is non-/ or door the connection of the second inverting input terminal, the output end of the 45th phase inverter and described two or three input or It is non-/ or door the connection of third input terminal, the output end of the 40th hex inverter and described two or three input or non-/ or The third inverting input terminal connection of door, the output end of the 47th phase inverter and described six or two input or non-/ or The first input end connection of door, the output end of the 4th eighteen incompatibilities phase device and described six or two input or non-/ or door The connection of first inverting input terminal, the output end of the 49th phase inverter and described six or two input or non-/ or door The second of the connection of second input terminal, the output end of the 50th phase inverter and described six or two input or non-/ or door is anti- The connection of phase input terminal, described five or two input or non-/ or the or logic output end of door are that the carry look ahead generates electricity The high-order carry signal output end of the first of road, for exporting the first high-order carry signal, the five or two input or non-/ or door Or logic output terminal be the carry look ahead generation circuit the first reverse phase high position carry signal output end, for exporting the One reverse phase high position carry signal, described one or three input or non-/ or the or logic output end of door are the carry look ahead The high-order carry signal output end of the second of generation circuit, for exporting the second high-order carry signal；Described one or three input or It is non-/ door or logic output terminal be the carry look ahead generation circuit the second reverse phase high position carry signal output end, use In the second reverse phase high position carry signal of output；Described six or two input or non-/ or the or logic output end of door are described The third high position carry signal output end of carry look ahead generation circuit, for exporting third high position carry signal, the described the 6th Two input or it is non-/ door or logic output terminal be the carry look ahead generation circuit third reverse phase high position carry signal it is defeated Outlet, for exporting third reverse phase high position carry signal, the two or three input or non-/ or the or logic output end of door are The high-order carry signal output end of the 4th of the carry look ahead generation circuit, for exporting the 4th high-order carry signal；It is described The two or three input or it is non-/ door or logic output terminal be the carry look ahead generation circuit the 4th reverse phase high position carry Signal output end, for exporting the 4th reverse phase high position carry signal；Second input terminal of described two or two input or non-/ or door Signal input part is generated for the 4th carry of the carry look ahead generation circuit, generates signal for inputting the 4th carry；Institute State the two or two input or it is non-/ or door the second inverting input terminal be the carry look ahead generation circuit the 4th reverse phase carry Signal input part is generated, generates signal for inputting the 4th reverse phase carry；Described one or two input and non-/ clock with door End, described two or two input with it is non-/ with the clock end of door, the three or two input with it is non-/ with the clock end of door, described Four or two input with it is non-/ with the clock end of door, the one or the two input exclusive or/with or door clock end, the described the 2nd 2 Input exclusive or/same or door clock end, the three or two input exclusive or/same or door the clock end, the four or two input Exclusive or/same or door clock end, the five or two input exclusive or/same or door the clock end, the six or the two input exclusive or/ With or the clock end of door, described seven or the two input exclusive or/with or the clock end of door, the eight or the two input exclusive or/with or The clock end of door is connected with the clock end of the carry look ahead generation circuit, the low level of the carry look ahead generation circuit into Position signal input part and described five or the two input exclusive or/with or the second inverting input terminal of door connect and its connecting pin is described Adder low order carry signal input part；The reverse phase low order carry signal input part of the carry look ahead generation circuit and Five or two input exclusive or/same or door the second input terminal connection and its connecting pin is the reverse phase low level of the adder Carry signal input terminal；Described one or two input with it is non-/ with the first input end of door and the one or the two input exclusive or/same Or the first input end of door connects and its connecting pin is the first input end of the adder, adds for inputting first four First signal of number signal；Described one or two input with it is non-/ defeated with the first inverting input terminal of door and the described the 1st Enter exclusive or/same or door the first inverting input terminal connection and its connecting pin is the first inverting input terminal of the adder, uses In the first bit Inverting signal for inputting first four addend signal；Described one or two input and non-/ the second input with door End is connected with the one or two input exclusive or/same or door second input terminal and its connecting pin is the second of the adder Input terminal, for inputting first signal of second four addend signal, the one or two input with it is non-/ with door second Inverting input terminal is connected with the one or two input exclusive or/same or door second inverting input terminal and its connecting pin is described Second inverting input terminal of adder, for inputting the first bit Inverting signal of second four addend signal；Described second Two inputs with it is non-/ input exclusive or/together with the first input end of door and the described 2nd 2 or the first input end of door is connect and it Connecting pin is the third input terminal of the adder, for inputting the second signal of first four addend signal；It is described The two or two input with it is non-/ with the first inverting input terminal of door and the two or the two input exclusive or/with or door the first reverse phase Input terminal connection and its connecting pin are the third inverting input terminal of the adder, for inputting first four addend signal Second inversion signal；Described two or two input with it is non-/ with the second input terminal of door and the two or the two input exclusive or/ Same or door the second input terminal connection and its connecting pin are the 4th input terminal of the adder, for inputting second four The second signal of addend signal；Described two or two input and non-/ the second inverting input terminal and the described the 2nd 2 with door It inputs exclusive or/same or door the second inverting input terminal connection and its connecting pin is the 4th inverting input terminal of the adder, For inputting the second inversion signal of second four addend signal；Described three or two input with it is non-/ with it is the first of door defeated Enter end and described three or the two input exclusive or/with or the first input end of door connect and its connecting pin is the of the adder Five input terminals, for inputting the tribute signal of first four addend signal；Described three or two input with it is non-/ with door the One inverting input terminal and described three or the two input exclusive or/with or the first inverting input terminal of door connect and its connecting pin is described Adder the 5th inverting input terminal, for inputting the third bit Inverting signal of first four addend signal；Described Three or two inputs with it is non-/ with the second input terminal of door and the described 3rd 2 input exclusive or/together or the second input terminal of door connect and Its connecting pin is the 6th input terminal of the adder, for inputting the tribute signal of second four addend signal；Institute The three or two input stated with it is non-/ with the second inverting input terminal of door and the three or the two input exclusive or/with or door it is second anti- The connection of phase input terminal and its connecting pin are the 6th inverting input terminal of the adder, for inputting second four addends letter Number third bit Inverting signal；Described four or two input with it is non-/ input with the first input end of door and the described the 4th 2 it is different Or/with or door first input end connection and its connecting pin be the adder the 7th input terminal, for input first 4th signal of four addend signals；Described four or two input with it is non-/ with the first inverting input terminal of door and described the Four or two input exclusive or/same or door the first inverting input terminal connection and its connecting pin are the 7th anti-phase input of the adder End, for inputting the 4th bit Inverting signal of first four addend signal；Described four or two input with it is non-/ with door second Input terminal is connected with the four or two input exclusive or/same or door second input terminal and its connecting pin is the adder 8th input terminal, for inputting the 4th signal of second four addend signal；Described four or two input with it is non-/ with door Second inverting input terminal and described four or the two input exclusive or/with or the second inverting input terminal of door connect and its connecting pin is institute 8th inverting input terminal of the adder stated, for inputting the 4th bit Inverting signal of second four addend signal；Described One or two input with it is non-/ connect with the input terminal of the NAND Logic output end of door and first phase inverter, described first The output end of phase inverter generates signal input part with the first carry of the carry look ahead generation circuit and connects, and described first Two inputs with it is non-/ connect with the input terminal of logic output terminal and second phase inverter with door, second phase inverter The first reverse phase carry of output end and the carry look ahead generation circuit generate signal input part and connect, the described the 1st Input exclusive or/same or door XOR logic output end is connected with the input terminal of the third phase inverter, the third reverse phase The output end of device, the first reverse phase carry transmission signal input part of the carry look ahead generation circuit and the described the 5th 2 are defeated Enter exclusive or/same or door the second inverting input terminal connection, the one or two input exclusive or/same or door the same or logic output terminal It is connected with the input terminal of the 4th phase inverter, the output end of the 4th phase inverter, the carry look ahead generate electricity The first carry transmission signal input part on road is connected with the five or two input exclusive or/same or door second input terminal, described The two or two input with it is non-/ connect with the input terminal of the NAND Logic output end of door and the 5th phase inverter, described the Second carry of the output end of five phase inverters and the carry look ahead generation circuit generates signal input part and connects, and described the Two or two inputs with it is non-/ connect with the input terminal of logic output terminal and the hex inverter with door, the 6th reverse phase The output end of device generates signal input part with the second reverse phase carry of the carry look ahead generation circuit and connects, and described second Two input exclusive or/same or door XOR logic output end is connected with the input terminal of the 7th phase inverter, and the described the 7th is anti- The second reverse phase carry transmission signal input part and the described the 6th 2 of the output end of phase device, the carry look ahead generation circuit Input exclusive or/same or door the second inverting input terminal connection, the two or two input exclusive or/same or door the same or logic output End is connected with the input terminal of the 8th phase inverter, and the output end of the 8th phase inverter, the carry look ahead generate The second carry transmission signal input part of circuit is connected with the six or two input exclusive or/same or door second input terminal, institute The three or two input stated with it is non-/ connect with the input terminal of the NAND Logic output end of door and the 9th phase inverter, it is described The output end of 9th phase inverter generates signal input part with the third carry of the carry look ahead generation circuit and connects, described Three or two input with it is non-/ connect with the input terminal of logic output terminal and the tenth phase inverter with door, the described the tenth instead The third reverse phase carry of the output end of phase device and the carry look ahead generation circuit generates signal input part and connects, and described the Three or two input exclusive or/with or the XOR logic output end of door is connected with the input terminal of the 11st phase inverter, described the The third reverse phase carry transmission signal input part and described of the output end of 11 phase inverters, the carry look ahead generation circuit Seven or two input exclusive or/with or door the connection of the second inverting input terminal, described three or the two input exclusive or/with or door same or patrol Volume output end connect with the input terminal of the 12nd phase inverter, and the output end of the 12nd phase inverter described surpasses The third carry transmission signal input part of advanced potential generation circuit and the seven or the two input exclusive or/same or door the second input End connection, described four or two input with it is non-/ with the NAND Logic output end of door and the input terminal of the 13rd phase inverter Connection, the output end of the 13rd phase inverter and the 4th carry of the carry look ahead generation circuit generate signal input End connection, described four or two input with it is non-/ connect with the input terminal of logic output terminal and the 14th phase inverter with door It connects, the output end of the 14th phase inverter and the 4th reverse phase carry generation signal of the carry look ahead generation circuit are defeated Enter end connection, described four or the two input exclusive or/with or door XOR logic output end and the 15th phase inverter it is defeated Enter end connection, the 4th reverse phase carry transmission of the output end, the carry look ahead generation circuit of the 15th phase inverter Signal input part is connected with the eight or two input exclusive or/same or door second inverting input terminal, the four or two input Exclusive or/same or door same or logic output terminal is connected with the input terminal of the tenth hex inverter, the 16th reverse phase The output end of device, the 4th carry transmission signal input part of the carry look ahead generation circuit and the eight or two input are different Or/with or door the connection of the second input terminal, the high-order carry signal output end of the first of the carry look ahead generation circuit and institute The input terminal for the 17th phase inverter stated connects, and the output end of the 17th phase inverter and the six or two input are different Or/with or door the connection of the first inverting input terminal, the first reverse phase high position carry signal of the carry look ahead generation circuit is defeated Outlet is connected with the input terminal of the eighteen incompatibilities phase device, the output end and the described the 6th 2 of the eighteen incompatibilities phase device Input exclusive or/same or door first input end connection, the high-order carry signal output of the second of the carry look ahead generation circuit End is connected with the input terminal of the 19th phase inverter, the output end of the 19th phase inverter and the described the 7th 2 defeated Enter exclusive or/same or door the first inverting input terminal connection, the second reverse phase high position carry letter of the carry look ahead generation circuit Number output end is connected with the input terminal of the 20th phase inverter, the output end of the 20th phase inverter and described Seven or two input exclusive or/same or door first input end connection, the third high position carry signal of the carry look ahead generation circuit Output end is connected with the input terminal of the 21st phase inverter, the output end of the 21st phase inverter and described Eight or two input exclusive or/same or door the first inverting input terminal connection, the third reverse phase of the carry look ahead generation circuit are high Position carry signal output end is connected with the input terminal of the 22nd phase inverter, the output of the 22nd phase inverter It holds and is connected with the eight or two input exclusive or/same or door the first input end, the 4th of the carry look ahead generation circuit the High-order carry signal output end is the high-order carry signal output end of the adder, the carry look ahead generation circuit 4th reverse phase high position carry signal output end is the reverse phase high position carry signal output end of the adder；Described the five or two Input the first output end that exclusive or/same or door same or output end is the adder, the five or the two input exclusive or/same Or the exclusive or output end of door is the first reversed-phase output of the adder, the six or the two input exclusive or/same or door Same or output end is the second output terminal of the adder, the six or two input exclusive or/same or door the exclusive or output end For the second reversed-phase output of the adder, the seven or two input exclusive or/same or door the same or output end is described Adder third output end, described seven or the two input exclusive or/with or the exclusive or output end of door be the adder Third reversed-phase output, described eight or the two input exclusive or/with or the same or output end of door be the 4th defeated of the adder Outlet, the eight or two input exclusive or/same or door the exclusive or output end are the 4th reversed-phase output of the adder.
Described one or two input with it is non-/ with door include the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, third metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor, the 9th metal-oxide-semiconductor, the tenth metal-oxide-semiconductor, the 11st metal-oxide-semiconductor and the tenth Two metal-oxide-semiconductors；First metal-oxide-semiconductor, second metal-oxide-semiconductor, the third metal-oxide-semiconductor and the 4th metal-oxide-semiconductor is P Type metal-oxide-semiconductor, it is the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor, described The 9th metal-oxide-semiconductor, the tenth metal-oxide-semiconductor, the 11st metal-oxide-semiconductor and the 12nd metal-oxide-semiconductor be N-type metal-oxide-semiconductor； The source electrode of first metal-oxide-semiconductor, the source electrode of second metal-oxide-semiconductor, the source electrode of the third metal-oxide-semiconductor, the described the 4th The grid of the source electrode of metal-oxide-semiconductor and the 7th metal-oxide-semiconductor accesses power supply, the grid of first metal-oxide-semiconductor, the described the 4th The connection of the grid of the grid of metal-oxide-semiconductor and the 12nd metal-oxide-semiconductor and its connecting pin are described one or two input and non-/ and door Clock end, the drain electrode of first metal-oxide-semiconductor, the drain electrode of second metal-oxide-semiconductor, the grid of the third metal-oxide-semiconductor, institute The drain electrode for the 5th metal-oxide-semiconductor stated and the grid connection of the 6th metal-oxide-semiconductor and its connecting pin be described one or two input and It is non-/ with the NAND Logic output end of door, the grid of second metal-oxide-semiconductor, the drain electrode of the third metal-oxide-semiconductor, described the The drain electrode of four metal-oxide-semiconductors, the 5th metal-oxide-semiconductor grid connected with the drain electrode of the 6th metal-oxide-semiconductor and its connecting pin is institute The one or two input stated with it is non-/ with door and logic output terminal, the source electrode of the 5th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor Drain electrode is connected with the drain electrode of the 8th metal-oxide-semiconductor, the source electrode of the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor source electrode, The drain electrode of 9th metal-oxide-semiconductor is connected with the drain electrode of the 11st metal-oxide-semiconductor, the source electrode of the 8th metal-oxide-semiconductor, described The drain electrode of the tenth metal-oxide-semiconductor connected with the source electrode of the 9th metal-oxide-semiconductor, the grid of the 8th metal-oxide-semiconductor is described the One or two inputs with it is non-/ with the first input end of door, the grid of the 9th metal-oxide-semiconductor be the one or two input with it is non-/ with First inverting input terminal of door, the grid of the tenth metal-oxide-semiconductor are the one or two input and non-/ the second input with door End, the grid of the 11st metal-oxide-semiconductor is the one or two input and non-/ the second inverting input terminal with door, described The source electrode of tenth metal-oxide-semiconductor, the 11st metal-oxide-semiconductor source electrode connected with the drain electrode of the 12nd metal-oxide-semiconductor, described The source electrode of 12 metal-oxide-semiconductors is grounded；Described two or two input with it is non-/ with door, the described the 3rd 2 input with it is non-/ with door, described The four or two input with it is non-/ with door, described five or two input with it is non-/ with door, the six or two input with it is non-/ with door, institute The seven or two input stated with it is non-/ with door, described eight or two input with it is non-/ with door, the 9th 2 input with it is non-/ with door, Described 12nd input with it is non-/ with door, the 11st input with it is non-/ with door, the 12nd input with it is non-/ With door, described 13rd input with it is non-/ with door and the 14th input with it is non-/ with the structure of door and described the One or two input and it is non-/ identical as door.The circuit generate power consumption and handled data it is mutually indepedent, will not with input difference and It changes.
Described one or the two input exclusive or/with or door include the 13rd metal-oxide-semiconductor, the 14th metal-oxide-semiconductor, the 15th metal-oxide-semiconductor, the 16 metal-oxide-semiconductors, the 17th metal-oxide-semiconductor, the 18th metal-oxide-semiconductor, the 19th metal-oxide-semiconductor, the 20th metal-oxide-semiconductor, the 21st metal-oxide-semiconductor, second 12 metal-oxide-semiconductors, the 23rd metal-oxide-semiconductor, the 24th metal-oxide-semiconductor, the 25th metal-oxide-semiconductor and the 26th metal-oxide-semiconductor；Described the tenth Three metal-oxide-semiconductors, the 14th metal-oxide-semiconductor, the 15th metal-oxide-semiconductor and the 16th metal-oxide-semiconductor are p-type metal-oxide-semiconductor, institute It is the 17th metal-oxide-semiconductor stated, the 18th metal-oxide-semiconductor, the 19th metal-oxide-semiconductor, the 20th metal-oxide-semiconductor, described 21st metal-oxide-semiconductor, the 22nd metal-oxide-semiconductor, the 23rd metal-oxide-semiconductor, the 24th metal-oxide-semiconductor, institute The 25th metal-oxide-semiconductor and the 26th metal-oxide-semiconductor stated are N-type metal-oxide-semiconductor；The source electrode of 13rd metal-oxide-semiconductor, institute The source electrode for the 14th metal-oxide-semiconductor stated, the source electrode of the 15th metal-oxide-semiconductor, the source electrode of the 16th metal-oxide-semiconductor and described The grid of 19th metal-oxide-semiconductor accesses power supply, the grid of the 13rd metal-oxide-semiconductor, the grid of the 16th metal-oxide-semiconductor and The grid of 26th metal-oxide-semiconductor connects and its connecting pin is the one or two input exclusive or/same or door the clock end, The drain electrode of 13rd metal-oxide-semiconductor, the drain electrode of the 14th metal-oxide-semiconductor, the 15th metal-oxide-semiconductor grid, described The drain electrode of the 17th metal-oxide-semiconductor connected with the grid of the 18th metal-oxide-semiconductor and its connecting pin is described one or two input Exclusive or/same or door same or logic output terminal, the drain electrode of the grid, the 15th metal-oxide-semiconductor of the 14th metal-oxide-semiconductor, The drain electrode of 16th metal-oxide-semiconductor, the grid of the 17th metal-oxide-semiconductor are connected with the drain electrode of the 18th metal-oxide-semiconductor And its connecting pin is the one or two input exclusive or/same or door the XOR logic output end, the source of the 17th metal-oxide-semiconductor Pole, the drain electrode of the 19th metal-oxide-semiconductor, the drain electrode of the 20th metal-oxide-semiconductor and the drain electrode of the 21st metal-oxide-semiconductor Connection, the leakage of the source electrode, the source electrode, the 22nd metal-oxide-semiconductor of the 19th metal-oxide-semiconductor of the 18th metal-oxide-semiconductor Pole is connected with the drain electrode of the 23rd metal-oxide-semiconductor, the grid and the 23rd MOS of the 20th metal-oxide-semiconductor The grid of pipe connect and its connecting pin be the one or the two input exclusive or/with or door first input end, the described the 20th The source electrode of metal-oxide-semiconductor, the 22nd metal-oxide-semiconductor source electrode connected with the drain electrode of the 24th metal-oxide-semiconductor, described The grid of 21 metal-oxide-semiconductors is connected with the grid of the 22nd metal-oxide-semiconductor and its connecting pin is the one or two input Exclusive or/with or door the first inverting input terminal, the source of the source electrode of the 21st metal-oxide-semiconductor, the 23rd metal-oxide-semiconductor Pole is connected with the drain electrode of the 25th metal-oxide-semiconductor, and the grid of the 24th metal-oxide-semiconductor is the one or two input Exclusive or/with or door the second input terminal, the grid of the 25th metal-oxide-semiconductor be the one or the two input exclusive or/with or Second inverting input terminal of door, the source electrode of the 24th metal-oxide-semiconductor, the source electrode of the 25th metal-oxide-semiconductor and described The 26th metal-oxide-semiconductor drain electrode connection, the 26th metal-oxide-semiconductor source electrode ground connection；Two or the two input exclusive or/ With or door, described three or the two input exclusive or/with or door, the four or the two input exclusive or/with or it is door, the described the 5th 2 defeated Enter exclusive or/with or door, described six or the two input exclusive or/with or door, the seven or the two input exclusive or/with or door and described Eight or two input exclusive or/with or door structure and the described 1st input exclusive or/with or door it is identical.The power consumption that the circuit generates It is mutually indepedent with handled data, it will not change with input difference.
Described one or two input or non-/ or door include the 27th metal-oxide-semiconductor, the 28th metal-oxide-semiconductor, the 29th MOS The 30th metal-oxide-semiconductor of pipe, the 31st metal-oxide-semiconductor, the 33rd metal-oxide-semiconductor of the 32nd metal-oxide-semiconductor, the 34th metal-oxide-semiconductor, the 35th Metal-oxide-semiconductor, the 36th metal-oxide-semiconductor, the 37th metal-oxide-semiconductor and the 38th metal-oxide-semiconductor；27th metal-oxide-semiconductor, described 28 metal-oxide-semiconductors, the 29th metal-oxide-semiconductor and the 30th metal-oxide-semiconductor are p-type metal-oxide-semiconductor, and the described the 31st Metal-oxide-semiconductor, the 32nd metal-oxide-semiconductor, the 33rd metal-oxide-semiconductor, the 34th metal-oxide-semiconductor, the third 15 metal-oxide-semiconductors, the 36th metal-oxide-semiconductor, the 37th metal-oxide-semiconductor and the 38th metal-oxide-semiconductor are N-type Metal-oxide-semiconductor；The source electrode of 27th metal-oxide-semiconductor, the source electrode of the 28th metal-oxide-semiconductor, the 29th metal-oxide-semiconductor Source electrode, the source electrode of the 30th metal-oxide-semiconductor and the grid of the 33rd metal-oxide-semiconductor access power supply, described The grid of 27 metal-oxide-semiconductors, the 30th metal-oxide-semiconductor grid connected with the grid of the 38th metal-oxide-semiconductor and its Connecting pin is the clock end of described one or two input or non-/ or door, the drain electrode of the 27th metal-oxide-semiconductor, described the The drain electrode of 28 metal-oxide-semiconductors, the grid of the 29th metal-oxide-semiconductor, the drain electrode of the 31st metal-oxide-semiconductor and described The grid of 32nd metal-oxide-semiconductor connects and its connecting pin is the or logic output end of the one or two input or non-/ or door, The drain electrode of 29th metal-oxide-semiconductor, the drain electrode of the 30th metal-oxide-semiconductor, the 28th metal-oxide-semiconductor grid, The drain electrode connection of the grid of 31st metal-oxide-semiconductor and the 32nd metal-oxide-semiconductor and its connecting pin are described the One or two input or it is non-/ door or logic output terminal, source electrode, the 36th metal-oxide-semiconductor of the 31st metal-oxide-semiconductor Drain electrode, the 33rd metal-oxide-semiconductor drain electrode connected with the drain electrode of the 34th metal-oxide-semiconductor, the described the 30th The source electrode of two metal-oxide-semiconductors, the 33rd metal-oxide-semiconductor source electrode connected with the drain electrode of the 35th metal-oxide-semiconductor, it is described The grid of 34th metal-oxide-semiconductor is the first input end of described one or two input or non-/ or door, the 35th MOS The grid of pipe is the first inverting input terminal of described one or two input or non-/ or door, the grid of the 36th metal-oxide-semiconductor For described one or two input or non-/ or the second input terminal of door, the grid of the 37th metal-oxide-semiconductor is described first Two input or it is non-/ or door the second inverting input terminal, source electrode, the 35th metal-oxide-semiconductor of the 34th metal-oxide-semiconductor Source electrode connected with the drain electrode of the 37th metal-oxide-semiconductor, the source electrode of the 36th metal-oxide-semiconductor, the described the 30th The source electrode of seven metal-oxide-semiconductors is connected with the drain electrode of the 38th metal-oxide-semiconductor, the source electrode ground connection of the 38th metal-oxide-semiconductor；Institute The two or two input stated or non-/ or door, described three or two input or non-/ or door, the four or two input or non-/ or door, The structure and the one or two input of described five or two input or non-/ or door and the six or two input or non-/ or door Or it is non-/ or door it is identical.The power consumption and handled data that the circuit generates are mutually indepedent, will not change with input difference Become.
Described one or three input or non-/ or door include the 39th metal-oxide-semiconductor, the 40th metal-oxide-semiconductor, the 41st metal-oxide-semiconductor, 42nd metal-oxide-semiconductor, the 43rd metal-oxide-semiconductor, the 44th metal-oxide-semiconductor, the 45th metal-oxide-semiconductor, the 46th metal-oxide-semiconductor, the 40th Seven metal-oxide-semiconductors, the 48th metal-oxide-semiconductor, the 49th metal-oxide-semiconductor, the 50th metal-oxide-semiconductor, the 51st metal-oxide-semiconductor and the 52nd metal-oxide-semiconductor； 39th metal-oxide-semiconductor, the 40th metal-oxide-semiconductor, the 41st metal-oxide-semiconductor and the 42nd MOS Pipe is p-type metal-oxide-semiconductor, the 43rd metal-oxide-semiconductor, the 44th metal-oxide-semiconductor, the 45th metal-oxide-semiconductor, institute The 46th metal-oxide-semiconductor, the 47th metal-oxide-semiconductor, the 48th metal-oxide-semiconductor, the 49th MOS stated Pipe, the 50th metal-oxide-semiconductor, the 51st metal-oxide-semiconductor and the 52nd metal-oxide-semiconductor are N-type metal-oxide-semiconductor；Institute The source electrode for the 39th metal-oxide-semiconductor stated, the source electrode of the 40th metal-oxide-semiconductor, the source electrode of the 41st metal-oxide-semiconductor, institute The source electrode for the 42nd metal-oxide-semiconductor stated and the grid of the 45th metal-oxide-semiconductor access power supply, and the described the 39th The grid of metal-oxide-semiconductor, the 42nd metal-oxide-semiconductor grid connected with the grid of the 52nd metal-oxide-semiconductor and its connect End is the clock end of described one or three input or non-/ or door；The drain electrode of 39th metal-oxide-semiconductor, the described the 40th The drain electrode of metal-oxide-semiconductor, the 41st metal-oxide-semiconductor grid, the 43rd metal-oxide-semiconductor drain electrode and the described the 40th The grids of four metal-oxide-semiconductors connects and its connecting pin is the or logic output end of the one or three input or non-/ or door, described It is the grid of 40th metal-oxide-semiconductor, the drain electrode of the 41st metal-oxide-semiconductor, the drain electrode of the 42nd metal-oxide-semiconductor, described The drain electrode of the grid of 43rd metal-oxide-semiconductor and the 44th metal-oxide-semiconductor connects and its connecting pin is defeated for described the one or three Enter or non-/ door or logic output terminal, the leakage of the source electrode, the 45th metal-oxide-semiconductor of the 43rd metal-oxide-semiconductor Pole, the drain electrode of the 46th metal-oxide-semiconductor, the drain electrode of the 48th metal-oxide-semiconductor and the leakage of the 50th metal-oxide-semiconductor Pole connection, the source electrode and the 47th MOS of the source electrode of the 44th metal-oxide-semiconductor, the 45th metal-oxide-semiconductor The drain electrode of pipe connects, the source electrode and the described the 4th of the source electrode of the 46th metal-oxide-semiconductor, the 47th metal-oxide-semiconductor The drain electrodes of 19 metal-oxide-semiconductors connects, and the grid of the 46th metal-oxide-semiconductor is the of the one or three input or non-/ or door One input terminal, the grid of the 47th metal-oxide-semiconductor are the first anti-phase input of the one or three input or non-/ or door End, the grid of the 48th metal-oxide-semiconductor are the second input terminal of the one or three input or non-/ or door, described the The grid of 49 metal-oxide-semiconductors is the second inverting input terminal of described one or three input or non-/ or door, the 50th MOS The grid of pipe is the third input terminal of described one or three input or non-/ or door, and the grid of the 51st metal-oxide-semiconductor is institute State the one or three input or it is non-/ or door third inverting input terminal, the source electrode of the 48th metal-oxide-semiconductor, the described the 4th The source electrode of 19 metal-oxide-semiconductors is connected with the drain electrode of the 51st metal-oxide-semiconductor, the source electrode of the 50th metal-oxide-semiconductor, described The source electrode of 51st metal-oxide-semiconductor is connected with the drain electrode of the 52nd metal-oxide-semiconductor, the source electrode of the 52nd metal-oxide-semiconductor Ground connection；The structure of described two or three input or non-/ or door and the one or three input or non-/ or door are identical.The circuit produces Raw power consumption and handled data are mutually indepedent, will not change with input difference.
Compared with the prior art, the advantages of the present invention are as follows by four two inputs with it is non-/ input with door, eight two it is different Or/with or door, 22 phase inverters and carry look ahead generation circuit constitute adder, using TSMC 65nm CMOS technology, Simulation analysis is carried out to circuit by Spectre tool, the experimental results showed that adder of the invention has correct logic function Can, compared to conventional adders circuit in power consumption independence performance boost 97%, it can effectively resist differential power consumption analysis.
Detailed description of the invention
Fig. 1 is the structure chart of the defence differential power consumption analysis adder of the invention using sensitive scale-up version logic；
Fig. 2 is that the carry look ahead of the defence differential power consumption analysis adder of the invention using sensitive scale-up version logic generates The structure chart of circuit；
Fig. 3 is that the carry look ahead of the defence differential power consumption analysis adder of the invention using sensitive scale-up version logic generates The graphical diagram of circuit；
Fig. 4 (a) is the one or two defeated of the defence differential power consumption analysis adder of the invention using sensitive scale-up version logic Enter with it is non-/ with the circuit diagram of door；
Fig. 4 (b) is the one or two defeated of the defence differential power consumption analysis adder of the invention using sensitive scale-up version logic Enter with it is non-/ with the symbol of door；
Fig. 5 (a) is the one or two defeated of the defence differential power consumption analysis adder of the invention using sensitive scale-up version logic Enter exclusive or/same or door circuit diagram；
Fig. 5 (b) is the one or two defeated of the defence differential power consumption analysis adder of the invention using sensitive scale-up version logic Enter exclusive or/same or door symbol；
Fig. 6 (a) is the one or two defeated of the defence differential power consumption analysis adder of the invention using sensitive scale-up version logic Enter or non-/ or door circuit diagram；
Fig. 6 (b) is the one or two defeated of the defence differential power consumption analysis adder of the invention using sensitive scale-up version logic Enter or non-/ or door symbol；
Fig. 7 (a) is the one or three defeated of the defence differential power consumption analysis adder of the invention using sensitive scale-up version logic Enter or non-/ or door circuit diagram；
Fig. 7 (b) is the one or three defeated of the defence differential power consumption analysis adder of the invention using sensitive scale-up version logic Enter or non-/ or door symbol；
Fig. 8 is the analog waveform figure of the defence differential power consumption analysis adder of the invention using sensitive scale-up version logic；
Fig. 9 is the current curve diagram of existing adder；
Figure 10 is the power consumption profile figure of existing adder；
Figure 11 is the current curve diagram of the defence differential power consumption analysis adder of the invention using sensitive scale-up version logic；
Figure 12 is the power consumption profile figure of the defence differential power consumption analysis adder of the invention using sensitive scale-up version logic.
Specific embodiment
The present invention will be described in further detail below with reference to the embodiments of the drawings.
Embodiment one：As shown in Figure 1, Figure 2 and Figure 3, a kind of defence differential power consumption analysis using sensitive scale-up version logic Adder, including the one or two input with it is non-/ with door T1, the two or two input with it is non-/ with door T2, the three or two input with it is non-/ with door T3, Four or two input with it is non-/ with door T4, the one or two input exclusive or/with or door R1, the two or two input exclusive or/with or door R2, the three or two Input exclusive or/same or door R3, the four or two input exclusive or/same or door R4, the five or two input exclusive or/same or door R5, the six or two input Exclusive or/with or door R6, the seven or two input exclusive or/with or door R7, the eight or two input exclusive or/with or door R8, the first phase inverter N1, the Two phase inverter N2, third phase inverter N3, the 4th phase inverter N4, the 5th phase inverter N5, hex inverter N6, the 7th phase inverter N7, 8th phase inverter N8, the 9th phase inverter N9, the tenth phase inverter N10, the 11st phase inverter N11, the 12nd phase inverter N12, the tenth Three phase inverter N13, the 14th phase inverter N14, the 15th phase inverter N15, the tenth hex inverter N16, the 17th phase inverter N17, Eighteen incompatibilities phase device N18, the 19th phase inverter N19, the 20th phase inverter N20, the 21st phase inverter N21, the 22nd are instead Phase device N22 and carry look ahead generation circuit；Carry look ahead generation circuit include the five or two input with it is non-/ with door T5, the six or two defeated Enter with it is non-/ with door T6, the seven or two input with it is non-/ with door T7, the eight or two input with it is non-/ with door T8, the 9th 2 input and non-/ and door T9, the 12nd input with it is non-/ with door T10, the 11st input with it is non-/ with door T11, the 12nd input with it is non-/ with door T12, 13rd input with it is non-/ with door T13, the 14th input with it is non-/ with door T14, the one or two input or non-/ or door O1, second Two input or it is non-/ or door O2, the three or two input or it is non-/ or door O3, the four or two input or it is non-/ or door O4, the five or two input or it is non-/ Or door O5, the six or two input or non-/ or door O6, the one or three input or non-/ or door Q1, the two or three input or non-/ or door Q2, second 13 phase inverter N23, the 24th phase inverter N24, the 25th phase inverter N25, the 20th hex inverter N26, the 27th Phase inverter N27, the second eighteen incompatibilities phase device N28, the 29th phase inverter N29, the 30th phase inverter N30, the 31st phase inverter N31, the 32nd phase inverter N32, the 33rd phase inverter N33, the 34th phase inverter N34, the 35th phase inverter N35, 30th hex inverter N36, the 37th phase inverter N37, third eighteen incompatibilities phase device N38, the 39th phase inverter N39, the 4th Ten phase inverter N40, the 41st phase inverter N41, the 42nd phase inverter N42, the 43rd phase inverter N43, the 44th are instead Phase device N44, the 45th phase inverter N45, the 40th hex inverter N46, the 47th phase inverter N47, the 4th eighteen incompatibilities phase device N48, the 49th phase inverter N49 and the 50th phase inverter N50；One or two input with it is non-/ with door T1, the two or two input with it is non-/ With door T2, the three or two input with it is non-/ with door T3, the four or two input with it is non-/ with door T4, the five or two input with it is non-/ with door T5, the 6th Two input with it is non-/ with door T6, the seven or two input with it is non-/ with door T7, the eight or two input with it is non-/ with door T8, the 9th 2 input with it is non-/ With door T9, the 12nd input with it is non-/ with door T10, the 11st input with it is non-/ with door T11, the 12nd input and non-/ and door T12, the 13rd input with it is non-/ with door T13 and the 14th input with it is non-/ with door T14 be respectively provided with first input end, first Inverting input terminal, the second input terminal, the second inverting input terminal, clock end, NAND Logic output end and and logic output terminal；First Two input exclusive or/with or door R1, the two or two input exclusive or/with or door R2, the three or two input exclusive or/with or it is door R3, the four or two defeated Enter exclusive or/with or door R4, the five or two input exclusive or/with or door R5, the six or two input exclusive or/with or door R6, the seven or two input it is different Or/with or the input of door R7 and the eight or two exclusive or/with or door R8 be respectively provided with first input end, the first inverting input terminal, second defeated Enter end, the second inverting input terminal, clock end, same or logic output terminal and XOR logic output end；One or two input or non-/ or door It is O1, the two or two input or non-/ or door O2, the three or two input or non-/ or door O3, the four or two input or non-/ or door O4, the five or two defeated Enter or non-/ or the input of door O5 and the six or two or non-/ or door O6 be respectively provided with first input end, the first inverting input terminal, second defeated Enter end, the second inverting input terminal, clock end, or logic output end and/or logic output terminal；One or three input or non-/ or door Q1 With the two or three input or it is non-/ or door Q2 have first input end, the first inverting input terminal, the second input terminal, the second anti-phase input End, third input terminal, third inverting input terminal, clock end, or logic output end and/or logic output terminal；Five or two input with It is non-/ with the clock end of door T5, the six or two input with it is non-/ with the clock end of door T6, the seven or two input and non-/ clock with door T7 End, the eight or two input with it is non-/ with the clock end of door T8, the 9th 2 input with it is non-/ with the clock end of door T9, the 12nd input with It is non-/ with the clock end of door T10, the 11st input with it is non-/ with the clock end of door T11, the 12nd input with it is non-/ with door T12 Clock end, the 13rd input with it is non-/ with the clock end of door T13, the 14th input with it is non-/ with the clock end of door T14, the Clock end, the three or two input or the non-/ or door of the clock end of one or two inputs or non-/ or door O1, the two or two input or non-/ or door O2 The clock end of O3, the four or two input or it is non-/ or door O4 clock end, the five or two input or it is non-/ or door O5 clock end, the six or two The clock end of input or non-/ or door O6, the clock end of the one or three input or non-/ or door Q1 and the two or three input or non-/ or door Q2 Clock end connection and its connecting pin be carry look ahead generation circuit clock end；Five or two input with it is non-/ with the first of door T5 Input terminal, the 11st input with it is non-/ with the first input end of door T11, the 13rd input with it is non-/ with it is the first of door T13 defeated Enter end and the 14th input with it is non-/ connect with the first input end of door T14 and its connecting pin is carry look ahead generation circuit 4th carry transmits signal input part, transmits signal P3 for inputting the 4th carry；Five or two input with it is non-/ with the first of door T5 Inverting input terminal, the 11st input with it is non-/ with the first inverting input terminal of door T11, the 13rd input with it is non-/ with door T13 The first inverting input terminal and the 14th input with it is non-/ connect with the first inverting input terminal of door T14 and its connecting pin is super 4th reverse phase carry of advanced potential generation circuit transmits signal input part, transmits signal for inputting the 4th reverse phase carryThe Five or two input with it is non-/ with the second input terminal of door T5 and the four or two input or it is non-/ or door O4 the second input terminal connect and its company It connects the third carry that end is carry look ahead generation circuit and generates signal input part, generate signal G2 for inputting third carry；The Five or two inputs with it is non-/ connect with the second inverting input terminal of door T5 and the four or two input or non-/ or the second inverting input terminal of door O4 Connect and its connecting pin be carry look ahead generation circuit third reverse phase carry generate signal input part, for input third reverse phase into Position generates signalSix or two input with it is non-/ with the first input end of door T6, the 9th 2 input with it is non-/ with it is the first of door T9 defeated Enter end and the 12nd input with it is non-/ connect with the first input end of door T12 and its connecting pin is carry look ahead generation circuit Third carry transmits signal input part, for inputting third carry transmission signal P2；Six or two input with it is non-/ with the first of door T6 Inverting input terminal, the 9th 2 input with it is non-/ with the first inverting input terminal of door T9 and the 12nd input with it is non-/ with door T12's The connection of first inverting input terminal and its connecting pin are that the third reverse phase carry of carry look ahead generation circuit transmits signal input part, are used Signal is transmitted in input third reverse phase carrySix or two input with it is non-/ with the second input terminal of door T6 and the one or three input or It is non-/ or door Q1 third input terminal connection and its connecting pin be carry look ahead generation circuit the second carry generate signal input End generates signal G1 for inputting the second carry；Six or two input with it is non-/ defeated with the second inverting input terminal of door T6 and the one or three Enter or non-/ or door Q1 the connection of third inverting input terminal and its connecting pin be that the second reverse phase carry of carry look ahead generation circuit produces Raw signal input part generates signal for inputting the second reverse phase carrySeven or two input with it is non-/ with the first input end of door T7 With the 12nd input with it is non-/ connect with the first input end of door T10 and its connecting pin for carry look ahead generation circuit second into Transmission signal input part in position transmits signal P1 for inputting the second carry；Seven or two input with it is non-/ defeated with the first reverse phase of door T7 Enter end and the 12nd input with it is non-/ connect with the first inverting input terminal of door T10 and its connecting pin be carry look ahead generation circuit The second reverse phase carry transmit signal input part, for input the second reverse phase carry transmit signalSeven or two input with it is non-/ with Door T7 the second input terminal and the five or two input or it is non-/ or door O5 the second input terminal connection and its connecting pin be carry look ahead produce First carry of raw circuit generates signal input part, generates signal G0 for inputting the first carry；Seven or two input and non-/ and door The second inverting input terminal of T7 and the five or two input or non-/ or the second inverting input terminal of door O5 connect and its connecting pin is advanced First reverse phase carry of carry generating circuit generates signal input part, generates signal for inputting the first reverse phase carry8th Two inputs with it is non-/ with the first carry that the first input end of door T8 is carry look ahead generation circuit transmit signal input part, be used for Input the first carry transmission signal P0；Eight or two input with it is non-/ with the first inverting input terminal of door T8 be that carry look ahead generates electricity The first reverse phase carry on road transmits signal input part, transmits signal for inputting the first reverse phase carryEight or two input with It is non-/ with the second input terminal of door T8 be carry look ahead generation circuit low order carry signal input part, for inputting low order carry Signal C-1；Eight or two input with it is non-/ with the second inverting input terminal of door T8 be carry look ahead generation circuit reverse phase low order carry Signal input part is used for input inversion low order carry signalFive or two input with it is non-/ with the NAND Logic output end of door T5 Connect with the input terminal of the 23rd phase inverter N23, the five or two input with it is non-/ with door T5 and logic output terminal and the 24th The input terminal of phase inverter N24 connects, the six or two input and non-/ NAND Logic output end and the 25th phase inverter with door T6 The input terminal of N25 connects, the six or two input and non-/ input with logic output terminal and the 20th hex inverter N26 with door T6 End connection, the seven or two input with it is non-/ connect with the input terminal of the NAND Logic output end of door T7 and the 27th phase inverter N27, Seven or two input with it is non-/ connect with the input terminal of logic output terminal and the second eighteen incompatibilities phase device N28 with door T7, the eight or two inputs With it is non-/ connect with the input terminal of the NAND Logic output end of door T8 and the 29th phase inverter N29, the eight or two input with it is non-/ with Door T8 connect with the input terminal of logic output terminal and the 30th phase inverter N30, the 9th 2 input with it is non-/ patrol with non-with door T9 The input terminal of volume output end and the 31st phase inverter N31 connection, the 9th 2 input with it is non-/ with door T9 and logic output terminal and The input terminal of 32nd phase inverter N32 connects, the 12nd input and non-/ NAND Logic output end and the 30th with door T10 The input terminal of three phase inverter N33 connects, the 12nd input with it is non-/ with door T10 and logic output terminal and the 34th phase inverter The input terminal of N34 connects, the 11st input with it is non-/ with the NAND Logic output end of door T11 and the 35th phase inverter N35 Input terminal connection, the 11st input with it is non-/ with the input terminal with logic output terminal and the 30th hex inverter N36 of door T11 Connection, the 12nd input with it is non-/ connect with the input terminal of the NAND Logic output end of door T12 and the 37th phase inverter N37, 12nd input with it is non-/ connect with the input terminal of logic output terminal and third eighteen incompatibilities phase device N38 with door T12, the 13rd Two inputs with it is non-/ connect with the input terminal of the NAND Logic output end of door T13 and the 39th phase inverter N39, the 13rd is defeated Enter with it is non-/ connect with the input terminal of logic output terminal and the 40th phase inverter N40 with door T13, the 14th input with it is non-/ with Door T14 NAND Logic output end and the 41st phase inverter N41 input terminal connection, the 14th input with it is non-/ with door T14 Connect with the input terminal of logic output terminal and the 42nd phase inverter N42, the one or two input or it is non-/ or door O1 or logic The connection of the input terminal of output end and the 43rd phase inverter N43, the one or two input or non-/ or door be O1's or logic output terminal and the The input terminal of 44 phase inverter N44 connects, the or logic output end of the two or two input or non-/ or door O2 and the 45th anti- The input terminal of phase device N45 connects, and the two or two input or non-/ or door be O2's or logic output terminal and the 40th hex inverter N46's Input terminal connection, the three or two input or it is non-/ or door O3 or logic output end and the 47th phase inverter N47 input terminal connect It connects, O3's or logic output terminal and the 4th eighteen incompatibilities phase device N48's the input terminal connection of the three or two input or non-/ or door, the four or two Input or it is non-/ or door O4 or logic output end and the 49th phase inverter N49 input terminal connection, the four or two input or Non-/or door O4's or logic output terminal and the 50th phase inverter N50's input terminal connection, the output of the 23rd phase inverter N23 End and the two or two input or non-/ or the first input end of door O2 connect, the output end of the 24th phase inverter N24 and the two or two defeated Enter or non-/ or door O2 the connection of the first inverting input terminal, the output end of the 25th phase inverter N25, the 11st input with it is non-/ With the second input terminal of door T11 and the four or two input or it is non-/ or the first input end of door O4 connect, the 20th hex inverter N26 Output end, the 11st input with it is non-/ with the second inverting input terminal of door T11 and the four or two input or non-/ or door O4 the The connection of one inverting input terminal, the output end of the 27th phase inverter N27, the 9th 2 input with it is non-/ with the second input terminal of door T9 With the one or three input or it is non-/ or the second input terminal of door Q1 connect, the output end of the second eighteen incompatibilities phase device N28, the 9th 2 input With it is non-/ with the second inverting input terminal of door T9 and the one or three input or it is non-/ or the second inverting input terminal of door Q1 connect, the 20th The output end of nine phase inverter N29, the 12nd input with it is non-/ with the second input terminal of door T10 and the five or two input or non-/ or door O5 First input end connection, the output end of the 30th phase inverter N30, the 12nd input with it is non-/ with the second anti-phase input of door T10 End and the five or two input or it is non-/ or the first inverting input terminal of door O5 connect, the output end of the 31st phase inverter N31, the tenth Three or two input with it is non-/ with the second input terminal of door T13 and the three or two input or it is non-/ or the second input terminal of door O3 connect, third The output end of 12 phase inverter N32, the 13rd input with it is non-/ with the second inverting input terminal of door T13 and the three or two input or It is non-/ or door O3 the connection of the second inverting input terminal, the output end of the 33rd phase inverter N33, the 12nd input and non-/ and door The second input terminal of T12 and the one or three input or it is non-/ or door Q1 first input end connection, the 34th phase inverter N34's is defeated Outlet, the 12nd input with it is non-/ with it is the first of the second inverting input terminal of door T12 and the one or three input or non-/ or door Q1 anti- Phase input terminal connection, the output end of the 35th phase inverter N35 and the one or two input or it is non-/ or door O1 the second input terminal connect Connect, the output end of the 30th hex inverter N36 and the one or two input or it is non-/ or door O1 the second inverting input terminal connection, third The output end of 17 phase inverter N37, the 14th input with it is non-/ with the second input terminal of door T14 and the three or two input or non-/ or The first input end connection of door O3, the output end of third eighteen incompatibilities phase device N38, the 14th input with it is non-/ with the second of door T14 Inverting input terminal with the three or two input or it is non-/ or the first inverting input terminal of door O3 connect, the output of the 39th phase inverter N39 End and the one or two input or it is non-/ or the first input end of door O1 connect, the output end of the 40th phase inverter N40 and the one or two input Or it is non-/ or door O1 the first inverting input terminal connection, the output end of the 41st phase inverter N41 and the two or three input or it is non-/ or The first of the first input end connection of door Q2, the output end of the 42nd phase inverter N42 and the two or three input or non-/ or door Q2 is anti- Phase input terminal connection, the output end of the 43rd phase inverter N43 and the two or three input or it is non-/ or door Q2 the second input terminal connect Connect, the output end of the 44th phase inverter N44 and the two or three input or it is non-/ or door Q2 the second inverting input terminal connection, the 4th The output end of 15 phase inverter N45 and the two or three input or it is non-/ or door Q2 third input terminal connection, the 40th hex inverter The output end of N46 and the two or three input or it is non-/ or door Q2 third inverting input terminal connection, the 47th phase inverter N47's is defeated Outlet with the six or two input or it is non-/ or the first input end of door O6 connect, the output end and the six or two of the 4th eighteen incompatibilities phase device N48 Input or it is non-/ or door O6 the first inverting input terminal connection, the output end of the 49th phase inverter N49 and the six or two input or It is non-/ or door O6 the connection of the second input terminal, the of the output end of the 50th phase inverter N50 and the six or two input or non-/ or door O6 The connection of two inverting input terminals, the five or two input or non-/ or the or logic output end of door O5 are the of carry look ahead generation circuit One high-order carry signal output end, for exporting the first high-order carry signal C0, the five or two input or non-/ or door be O5's or logic Output end is the first reverse phase high position carry signal output end of carry look ahead generation circuit, for exporting the first reverse phase high position carry SignalThe or logic output end of one or three input or non-/ or door Q1 are the second high-order carry of carry look ahead generation circuit Signal output end, for exporting the second high-order carry signal C1；One or three input or it is non-/ door Q1's or logic output terminal be super Second reverse phase high position carry signal output end of advanced potential generation circuit, for exporting the second reverse phase high position carry signalThe Six or two input or it is non-/ or door O6 or logic output end be carry look ahead generation circuit third high position carry signal export End, for exporting third high position carry signal C2, the six or two input or non-/ or door O6's or logic output terminal be that carry look ahead produces The third reverse phase high position carry signal output end of raw circuit, for exporting third reverse phase high position carry signalTwo or three input Or it is non-/ or door Q2 or logic output end be carry look ahead generation circuit the 4th high-order carry signal output end, for defeated 4th high-order carry signal C3 out；Two or three input or non-/ or door Q2's or logic output terminal be carry look ahead generation circuit 4th reverse phase high position carry signal output end, for exporting the 4th reverse phase high position carry signalTwo or two input or it is non-/ or The second input terminal of door O2 is that the 4th carry of carry look ahead generation circuit generates signal input part, is produced for inputting the 4th carry Raw signal G3；Two or two input or it is non-/ or door O2 the second inverting input terminal be carry look ahead generation circuit the 4th reverse phase into Position generates signal input part, generates signal for inputting the 4th reverse phase carryOne or two input with it is non-/ with the clock of door T1 End, the two or two input with it is non-/ with the clock end of door T2, the three or two input with it is non-/ with the clock end of door T3, the four or two input with It is non-/ with the clock end of door T4, the one or two input exclusive or/with or the clock end of door R1, the two or two input exclusive or/with or door R2 when Zhong Duan, the three or two input exclusive or/with or the clock end of door R3, the four or two input exclusive or/with or door R4 clock end, the five or two defeated Enter exclusive or/same or door R5 clock end, the six or two input exclusive or/same or door R6 clock end, the seven or two input exclusive or/same or door The clock end of R7, the eight or two input exclusive or/same or door R8 clock end are connected with the clock end of carry look ahead generation circuit, in advance The low order carry signal input part of carry generating circuit and the five or two input exclusive or/same or door R5 the second inverting input terminal connection And its connecting pin is the low order carry signal input part of adder；The reverse phase low order carry signal of carry look ahead generation circuit inputs End is connected with the five or two input exclusive or/same or door R5 the second input terminal and its connecting pin is the reverse phase low order carry letter of adder Number input terminal；One or two input with it is non-/ with the first input end of door T1 and the one or two input exclusive or/with or door R1 the first input End connection and its connecting pin are the first input end of adder, for inputting first signal of first four addend signal； One or two input with it is non-/ with the first inverting input terminal of door T1 and the one or two input exclusive or/with or door R1 the first anti-phase input End connection and its connecting pin are the first inverting input terminal of adder, and first for inputting first four addend signal is anti- Phase signals；One or two input with it is non-/ with the second input terminal of door T1 and the one or two input exclusive or/with or door R1 the second input terminal Connection and its connecting pin are the second input terminal of adder, for inputting first signal of second four addend signal, the One or two inputs with it is non-/ with the second inverting input terminal of door T1 and the one or two input exclusive or/with or door R1 the second inverting input terminal Connection and its connecting pin are the second inverting input terminal of adder, for inputting first bit Inverting of second four addend signal Signal；Two or two input with it is non-/ with the first input end of door T2 and the two or two input exclusive or/with or the first input end of door R2 connect It connects and its connecting pin is the third input terminal of adder, for inputting the second signal of first four addend signal；Second Two inputs with it is non-/ with the first inverting input terminal of door T2 and the two or two input exclusive or/with or the first inverting input terminal of door R2 connect It connects and its connecting pin is the third inverting input terminal of adder, the second bit Inverting for inputting first four addend signal is believed Number；Two or two input with it is non-/ input exclusive or/together with the second input terminal of door T2 and the two or two or the second input terminal of door R2 is connect And its connecting pin is the 4th input terminal of adder, for inputting the second signal of second four addend signal；Two or two Input with it is non-/ input exclusive or/together with the second inverting input terminal of door T2 and the two or two or the second inverting input terminal of door R2 is connect And its connecting pin is the 4th inverting input terminal of adder, the second bit Inverting for inputting second four addend signal is believed Number；Three or two input with it is non-/ input exclusive or/together with the first input end of door T3 and the three or two or the first input end of door R3 is connect And its connecting pin is the 5th input terminal of adder, for inputting the tribute signal of first four addend signal；Three or two Input with it is non-/ input exclusive or/together with the first inverting input terminal of door T3 and the three or two or the first inverting input terminal of door R3 is connect And its connecting pin is the 5th inverting input terminal of adder, the third bit Inverting for inputting first four addend signal is believed Number；Three or two input with it is non-/ input exclusive or/together with the second input terminal of door T3 and the three or two or the second input terminal of door R3 is connect And its connecting pin is the 6th input terminal of adder, for inputting the tribute signal of second four addend signal；Three or two Input with it is non-/ input exclusive or/together with the second inverting input terminal of door T3 and the three or two or the second inverting input terminal of door R3 is connect And its connecting pin is the 6th inverting input terminal of adder, the third bit Inverting for inputting second four addend signal is believed Number；Four or two input with it is non-/ input exclusive or/together with the first input end of door T4 and the four or two or the first input end of door R4 is connect And its connecting pin is the 7th input terminal of adder, for inputting the 4th signal of first four addend signal；Four or two Input with it is non-/ input exclusive or/together with the first inverting input terminal of door T4 and the four or two or the first inverting input terminal of door R4 is connect And its connecting pin is the 7th inverting input terminal of adder, the 4th bit Inverting for inputting first four addend signal is believed Number；Four or two input with it is non-/ input exclusive or/together with the second input terminal of door T4 and the four or two or the second input terminal of door R4 is connect And its connecting pin is the 8th input terminal of adder, for inputting the 4th signal of second four addend signal；Four or two Input with it is non-/ input exclusive or/together with the second inverting input terminal of door T4 and the four or two or the second inverting input terminal of door R4 is connect And its connecting pin is the 8th inverting input terminal of adder, the 4th bit Inverting for inputting second four addend signal is believed Number；One or two input with it is non-/ connect with the input terminal of the NAND Logic output end of door T1 and the first phase inverter N1, the first phase inverter First carry of the output end of N1 and carry look ahead generation circuit generates signal input part and connect, the one or two input and non-/ and door T1's connect with the input terminal of logic output terminal and the second phase inverter N2, and the output end and carry look ahead of the second phase inverter N2 generates First reverse phase carry of circuit generates signal input part connection, the one or two input exclusive or/same or door R1 XOR logic output end Connected with the input terminal of third phase inverter N3, the output end of third phase inverter N3, carry look ahead generation circuit the first reverse phase into Position transmission signal input part and the five or two input exclusive or/same or door R5 the second inverting input terminal connection, the one or two input exclusive or/ With or door R1 same or logic output terminal and the 4th phase inverter N4 input terminal connection, it is the output end of the 4th phase inverter N4, advanced The first carry transmission signal input part of carry generating circuit and the five or two input exclusive or/same or door R5 the second input terminal connect Connect, the two or two input with it is non-/ connect with the input terminal of the NAND Logic output end of door T2 and the 5th phase inverter N5, the 5th phase inverter Second carry of the output end of N5 and carry look ahead generation circuit generates signal input part and connect, the two or two input and non-/ and door T2's connect with the input terminal of logic output terminal and hex inverter N6, and the output end and carry look ahead of hex inverter N6 generates Second reverse phase carry of circuit generates signal input part connection, the two or two input exclusive or/same or door R2 XOR logic output end Connected with the input terminal of the 7th phase inverter N7, the output end of the 7th phase inverter N7, carry look ahead generation circuit the second reverse phase into Position transmission signal input part and the six or two input exclusive or/same or door R6 the second inverting input terminal connection, the two or two input exclusive or/ With or door R2 same or logic output terminal and the 8th phase inverter N8 input terminal connection, it is the output end of the 8th phase inverter N8, advanced The second carry transmission signal input part of carry generating circuit and the six or two input exclusive or/same or door R6 the second input terminal connect Connect, the three or two input with it is non-/ connect with the input terminal of the NAND Logic output end of door T3 and the 9th phase inverter N9, the 9th phase inverter The third carry of the output end of N9 and carry look ahead generation circuit generates signal input part and connect, the three or two input and non-/ and door T3's connect with the input terminal of logic output terminal and the tenth phase inverter N10, and the output end and carry look ahead of the tenth phase inverter N10 produces The third reverse phase carry of raw circuit generates signal input part connection, the three or two input exclusive or/same or door R3 XOR logic output End is connected with the input terminal of the 11st phase inverter N11, and the of the output end of the 11st phase inverter N11, carry look ahead generation circuit Three reverse phase carries transmit signal input part and the seven or two input exclusive or/same or door R7 the second inverting input terminal connects, and the three or two Input exclusive or/same or door R3 same or logic output terminal and the input terminal connection of the 12nd phase inverter N12, the 12nd phase inverter The output end of N12, the third carry transmission signal input part of carry look ahead generation circuit and the seven or two input exclusive or/same or door R7 The connection of the second input terminal, the four or two input and non-/ input with the NAND Logic output end and the 13rd phase inverter N13 of door T4 End connection, the output end of the 13rd phase inverter N13 generate signal input part with the 4th carry of carry look ahead generation circuit and connect, Four or two input with it is non-/ connect with the input terminal of logic output terminal and the 14th phase inverter N14 with door T4, the 14th phase inverter The output end of N14 generates signal input part with the 4th reverse phase carry of carry look ahead generation circuit and connects, and the four or two input exclusive or/ The input terminal connection of same or door R4 XOR logic output end and the 15th phase inverter N15, the output of the 15th phase inverter N15 End, the 4th reverse phase carry transmission signal input part of carry look ahead generation circuit and the eight or two input exclusive or/with or door R8 the The connection of two inverting input terminals, the four or two input exclusive or/same or door R4 same or logic output terminal and the tenth hex inverter N16's is defeated Enter end connection, the output end of the tenth hex inverter N16, the 4th carry transmission signal input part of carry look ahead generation circuit and the Eight or two input exclusive or/same or door R8 the second input terminal connection, the high-order carry signal output of the first of carry look ahead generation circuit End connect with the input terminal of the 17th phase inverter N17, the output end of the 17th phase inverter N17 and the six or two input exclusive or/together or The first inverting input terminal connection of door R6, the first reverse phase high position carry signal output end of carry look ahead generation circuit and the 18th The input terminal of phase inverter N18 connects, the output end of eighteen incompatibilities phase device N18 and the six or two input exclusive or/same or door R6 first Input terminal connection, the input terminal of the second of carry look ahead generation circuit high-order carry signal output end and the 19th phase inverter N19 Connection, the output end of the 19th phase inverter N19 and the seven or two input exclusive or/same or door R7 the first inverting input terminal connection, surpass Second reverse phase high position carry signal output end of advanced potential generation circuit is connected with the input terminal of the 20th phase inverter N20, and second The output end of ten phase inverter N20 and the seven or two input exclusive or/same or door R7 first input end connection, carry look ahead generation circuit Third high position carry signal output end connected with the input terminal of the 21st phase inverter N21, the 21st phase inverter N21's is defeated Outlet is connected with the eight or two input exclusive or/same or door R8 the first inverting input terminal, the third reverse phase of carry look ahead generation circuit High-order carry signal output end is connected with the input terminal of the 22nd phase inverter N22, the output end of the 22nd phase inverter N22 and Eight or two input exclusive or/same or door R8 first input end connection, the high-order carry signal of the 4th of carry look ahead generation circuit are defeated Outlet is the high-order carry signal output end of adder, the 4th reverse phase high position carry signal output end of carry look ahead generation circuit For the reverse phase high position carry signal output end of adder；Five or two input exclusive or/same or door R5 same or output end is adder The first output end, the five or two input exclusive or/with or door R5 exclusive or output end be adder the first reversed-phase output, the 6th Two input exclusive or/same or door R6 same or output end is the second output terminal of adder, the six or two input exclusive or/same or door R6 Exclusive or output end is the second reversed-phase output of adder, and the seven or two input exclusive or/same or door R7 same or output end is addition The third output end of device, the seven or two input exclusive or/same or door R7 exclusive or output end are the third reversed-phase output of adder, the Eight or two input exclusive or/same or door R8 same or output end is the 4th output end of adder, the eight or two input exclusive or/same or door R8 Exclusive or output end be adder the 4th reversed-phase output.
Embodiment two：The present embodiment is basically the same as the first embodiment, and difference is only that in the present embodiment, such as Fig. 4 (a) and figure Shown in 4 (b), the one or two input with it is non-/ with door T1 include the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, third metal-oxide-semiconductor M3, the 4th MOS Pipe M4, the 5th metal-oxide-semiconductor M5, the 6th metal-oxide-semiconductor M6, the 7th metal-oxide-semiconductor M7, the 8th metal-oxide-semiconductor M8, the 9th metal-oxide-semiconductor M9, the tenth metal-oxide-semiconductor M10, the 11st metal-oxide-semiconductor M11 and the 12nd metal-oxide-semiconductor M12；First metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, third metal-oxide-semiconductor M3 and the 4th Metal-oxide-semiconductor M4 is p-type metal-oxide-semiconductor, the 5th metal-oxide-semiconductor M5, the 6th metal-oxide-semiconductor M6, the 7th metal-oxide-semiconductor M7, the 8th metal-oxide-semiconductor M8, the 9th metal-oxide-semiconductor M9, the tenth metal-oxide-semiconductor M10, the 11st metal-oxide-semiconductor M11 and the 12nd metal-oxide-semiconductor M12 are N-type metal-oxide-semiconductor；The source electrode of first metal-oxide-semiconductor M1, The source electrode of second metal-oxide-semiconductor M2, the source electrode of third metal-oxide-semiconductor M3, the source electrode of the 4th metal-oxide-semiconductor M4 and the grid of the 7th metal-oxide-semiconductor M7 connect Enter power supply, the grid connection and its connection of the grid of the first metal-oxide-semiconductor M1, the grid of the 4th metal-oxide-semiconductor M4 and the 12nd metal-oxide-semiconductor M12 End for the one or two input with it is non-/ with the clock end of door T1, the drain electrode of the first metal-oxide-semiconductor M1, the drain electrode of the second metal-oxide-semiconductor M2, the 3rd MOS The grid of the grid of pipe M3, the drain electrode of the 5th metal-oxide-semiconductor M5 and the 6th metal-oxide-semiconductor M6 connect and its connecting pin be the one or two input with It is non-/ with the NAND Logic output end of door T1, the grid of the second metal-oxide-semiconductor M2, the drain electrode of third metal-oxide-semiconductor M3, the leakage of the 4th metal-oxide-semiconductor M4 The drain electrode of pole, the grid of the 5th metal-oxide-semiconductor M5 and the 6th metal-oxide-semiconductor M6 connect and its connecting pin be the one or two input with it is non-/ with door T1 And logic output terminal, the drain electrode of the source electrode, the 7th metal-oxide-semiconductor M7 of the 5th metal-oxide-semiconductor M5 connected with the drain electrode of the 8th metal-oxide-semiconductor M8, The drain electrode of the source electrode, the source electrode, the 9th metal-oxide-semiconductor M9 of the 7th metal-oxide-semiconductor M7 of six metal-oxide-semiconductor M6 and the drain electrode of the 11st metal-oxide-semiconductor M11 connect It connects, the drain electrode of the source electrode, the tenth metal-oxide-semiconductor M10 of the 8th metal-oxide-semiconductor M8 is connected with the source electrode of the 9th metal-oxide-semiconductor M9, the 8th metal-oxide-semiconductor M8's Grid be the one or two input with it is non-/ with the first input end of door T1, the grid of the 9th metal-oxide-semiconductor M9 be the one or two input with it is non-/ with The first inverting input terminal of door T1, the grid of the tenth metal-oxide-semiconductor M10 are the one or two input and non-/ the second input terminal with door T1, the The grid of 11 metal-oxide-semiconductor M11 be the one or two input with it is non-/ with the second inverting input terminal of door T1, the source electrode of the tenth metal-oxide-semiconductor M10, The drain electrode connection of the source electrode and the 12nd metal-oxide-semiconductor M12 of 11st metal-oxide-semiconductor M11, the source electrode ground connection of the 12nd metal-oxide-semiconductor M12；Second Two input with it is non-/ with door T2, the three or two input with it is non-/ with door T3, the four or two input with it is non-/ with door T4, the five or two input with it is non-/ With door T5, the six or two input with it is non-/ with door T6, the seven or two input with it is non-/ with door T7, the eight or two input with it is non-/ with door T8, the 9th Two inputs with it is non-/ with door T9, the 12nd input with it is non-/ with door T10, the 11st input with it is non-/ with door T11, the 12nd defeated Enter with it is non-/ with door T12, the 13rd input with it is non-/ with the input of door T13 and the 14th with it is non-/ with the structure and first of door T14 Two input and it is non-/ identical as door T1.
As shown in Fig. 5 (a) and Fig. 5 (b), in the present embodiment, the one or two input exclusive or/same or door R1 includes the 13rd MOS Pipe M13, the 14th metal-oxide-semiconductor M14, the 15th metal-oxide-semiconductor M15, the 16th metal-oxide-semiconductor M16, the 17th metal-oxide-semiconductor M17, the 18th metal-oxide-semiconductor M18, the 19th metal-oxide-semiconductor M19, the 20th metal-oxide-semiconductor M20, the 21st metal-oxide-semiconductor M21, the 22nd metal-oxide-semiconductor M22, the 23rd Metal-oxide-semiconductor M23, the 24th metal-oxide-semiconductor M24, the 25th metal-oxide-semiconductor M25 and the 26th metal-oxide-semiconductor M26；13rd metal-oxide-semiconductor M13, 14th metal-oxide-semiconductor M14, the 15th metal-oxide-semiconductor M15 and the 16th metal-oxide-semiconductor M16 are p-type metal-oxide-semiconductor, the 17th metal-oxide-semiconductor M17, the tenth Eight metal-oxide-semiconductor M18, the 19th metal-oxide-semiconductor M19, the 20th metal-oxide-semiconductor M20, the 21st metal-oxide-semiconductor M21, the 22nd metal-oxide-semiconductor M22, 23 metal-oxide-semiconductor M23, the 24th metal-oxide-semiconductor M24, the 25th metal-oxide-semiconductor M25 and the 26th metal-oxide-semiconductor M26 are N-type MOS Pipe；The source electrode of 13rd metal-oxide-semiconductor M13, the source electrode of the 14th metal-oxide-semiconductor M14, the 15th metal-oxide-semiconductor M15 source electrode, the 16th metal-oxide-semiconductor The grid of the source electrode of M16 and the 19th metal-oxide-semiconductor M19 access power supply, grid, the 16th metal-oxide-semiconductor M16 of the 13rd metal-oxide-semiconductor M13 Grid and the 26th metal-oxide-semiconductor M26 grid connection and its connecting pin be the one or two input exclusive or/with or door R1 clock End, the drain electrode of the 13rd metal-oxide-semiconductor M13, the drain electrode of the 14th metal-oxide-semiconductor M14, the 15th metal-oxide-semiconductor M15 grid, the 17th metal-oxide-semiconductor The drain electrode of M17 connected with the grid of the 18th metal-oxide-semiconductor M18 and its connecting pin be the one or two input exclusive or/with or door R1 same or Logic output terminal, the grid of the 14th metal-oxide-semiconductor M14, the drain electrode of the 15th metal-oxide-semiconductor M15, the drain electrode of the 16th metal-oxide-semiconductor M16, The drain electrode of the grid and the 18th metal-oxide-semiconductor M18 of 17 metal-oxide-semiconductor M17 connects and its connecting pin is the one or two input exclusive or/same or door The XOR logic output end of R1, the drain electrode of the source electrode, the 19th metal-oxide-semiconductor M19 of the 17th metal-oxide-semiconductor M17, the 20th metal-oxide-semiconductor M20 Drain electrode is connected with the drain electrode of the 21st metal-oxide-semiconductor M21, the source electrode of the 18th metal-oxide-semiconductor M18, the source electrode of the 19th metal-oxide-semiconductor M19, the The drain electrode of 22 metal-oxide-semiconductor M22 is connected with the drain electrode of the 23rd metal-oxide-semiconductor M23, the grid and the 20th of the 20th metal-oxide-semiconductor M20 The grid of three metal-oxide-semiconductor M23 connects and its connecting pin is the one or two input exclusive or/same or door R1 first input end, the 20th MOS The drain electrode of the source electrode of pipe M20, the source electrode of the 22nd metal-oxide-semiconductor M22 and the 24th metal-oxide-semiconductor M24 connects, the 21st metal-oxide-semiconductor The connection of the grid of the grid of M21 and the 22nd metal-oxide-semiconductor M22 and its connecting pin be the one or two input exclusive or/with or door R1 the One inverting input terminal, the source electrode and the 25th metal-oxide-semiconductor M25 of the source electrode of the 21st metal-oxide-semiconductor M21, the 23rd metal-oxide-semiconductor M23 Drain electrode connection, the grid of the 24th metal-oxide-semiconductor M24 be the one or two input exclusive or/with or door R1 the second input terminal, the 20th The grid of five metal-oxide-semiconductor M25 is the one or two input exclusive or/same or door R1 the second inverting input terminal, the 24th metal-oxide-semiconductor M24's The drain electrode of source electrode, the source electrode of the 25th metal-oxide-semiconductor M25 and the 26th metal-oxide-semiconductor M26 connects, the source of the 26th metal-oxide-semiconductor M26 Pole ground connection；Two or two inputs exclusive or/same or door R2, the three or two input exclusive or/same or door R3, the four or two input exclusive or/same or door R4, the five or two input exclusive or/with or door R5, the six or two input exclusive or/with or door R6, the seven or two input exclusive or/with or door R7 and Eight or two input exclusive or/with or door R8 structure and the one or two input exclusive or/with or door R1 it is identical.
As shown in Fig. 6 (a) and Fig. 6 (b), in the present embodiment, the one or two input or non-/ or door O1 include the 27th MOS Pipe M27, the 28th metal-oxide-semiconductor M28, the 30th metal-oxide-semiconductor M30 of the 29th metal-oxide-semiconductor M29, the 31st metal-oxide-semiconductor M31, the 30th The 33rd metal-oxide-semiconductor M33 of two metal-oxide-semiconductor M32, the 34th metal-oxide-semiconductor M34, the 35th metal-oxide-semiconductor M35, the 36th metal-oxide-semiconductor M36, the 37th metal-oxide-semiconductor M37 and the 38th metal-oxide-semiconductor M38；27th metal-oxide-semiconductor M27, the 28th metal-oxide-semiconductor M28, second 19 metal-oxide-semiconductor M29 and the 30th metal-oxide-semiconductor M30 are p-type metal-oxide-semiconductor, the 31st metal-oxide-semiconductor M31, the 32nd metal-oxide-semiconductor M32, 33 metal-oxide-semiconductor M33, the 34th metal-oxide-semiconductor M34, the 35th metal-oxide-semiconductor M35, the 36th metal-oxide-semiconductor M36, the 37th MOS Pipe M37 and the 38th metal-oxide-semiconductor M38 is N-type metal-oxide-semiconductor；The source electrode of 27th metal-oxide-semiconductor M27, the 28th metal-oxide-semiconductor M28 Source electrode, the source electrode of the 29th metal-oxide-semiconductor M29, the source electrode of the 30th metal-oxide-semiconductor M30 and the grid of the 33rd metal-oxide-semiconductor M33 connect Enter power supply, the grid of the grid of the 27th metal-oxide-semiconductor M27, the grid of the 30th metal-oxide-semiconductor M30 and the 38th metal-oxide-semiconductor M38 connects Connect and its connecting pin be the one or two input or it is non-/ or door O1 clock end, the drain electrode of the 27th metal-oxide-semiconductor M27, the 28th The drain electrode of metal-oxide-semiconductor M28, the grid of the 29th metal-oxide-semiconductor M29, the drain electrode of the 31st metal-oxide-semiconductor M31 and the 32nd metal-oxide-semiconductor The grid of M32 connects and its connecting pin is the one or two input or non-/ or the or logic output end of door O1, the 29th metal-oxide-semiconductor The drain electrode of M29, the drain electrode of the 30th metal-oxide-semiconductor M30, the grid of the 28th metal-oxide-semiconductor M28, the 31st metal-oxide-semiconductor M31 grid With the drain electrode of the 32nd metal-oxide-semiconductor M32 connection and its connecting pin be the one or two input or non-/ or door O1's or logic output terminal, The drain electrode of the source electrode, the 36th metal-oxide-semiconductor M36 of 31st metal-oxide-semiconductor M31, the drain electrode and the 30th of the 33rd metal-oxide-semiconductor M33 The drain electrode of four metal-oxide-semiconductor M34 connects, the source electrode and the 35th of the source electrode of the 32nd metal-oxide-semiconductor M32, the 33rd metal-oxide-semiconductor M33 The drain electrode of metal-oxide-semiconductor M35 connects, and the grid of the 34th metal-oxide-semiconductor M34 is the one or two input or non-/ or the first input end of door O1, The grid of 35th metal-oxide-semiconductor M35 be the one or two input or it is non-/ or door O1 the first inverting input terminal, the 36th metal-oxide-semiconductor The grid of M36 is the one or two input or non-/ or the second input terminal of door O1, and the grid of the 37th metal-oxide-semiconductor M37 is the one two defeated Enter or non-/ or door O1 the second inverting input terminal, the source electrode of the 34th metal-oxide-semiconductor M34, the source electrode of the 35th metal-oxide-semiconductor M35 and The drain electrode of 37th metal-oxide-semiconductor M37 connects, the source electrode of the 36th metal-oxide-semiconductor M36, the source electrode of the 37th metal-oxide-semiconductor M37 and the The drain electrode of 38 metal-oxide-semiconductor M38 connects, the source electrode ground connection of the 38th metal-oxide-semiconductor M38；Two or two input or non-/ or door O2, the Three or two input or it is non-/ or door O3, the four or two input or it is non-/ or door O4, the five or two input or it is non-/ or door O5 and the six or two input or It is non-/ door O6 structure with the one or two input or it is non-/ or door O1 it is identical.
As shown in Fig. 7 (a) and Fig. 7 (b), in the present embodiment, the one or three input or non-/ or door Q1 include the 39th MOS Pipe M39, the 40th metal-oxide-semiconductor M40, the 41st metal-oxide-semiconductor M41, the 42nd metal-oxide-semiconductor M42, the 43rd metal-oxide-semiconductor M43, the 4th 14 metal-oxide-semiconductor M44, the 45th metal-oxide-semiconductor M45, the 46th metal-oxide-semiconductor M46, the 47th metal-oxide-semiconductor M47, the 48th metal-oxide-semiconductor M48, the 49th metal-oxide-semiconductor M49, the 50th metal-oxide-semiconductor M50, the 51st metal-oxide-semiconductor M51 and the 52nd metal-oxide-semiconductor M52；30th Nine metal-oxide-semiconductor M39, the 40th metal-oxide-semiconductor M40, the 41st metal-oxide-semiconductor M41 and the 42nd metal-oxide-semiconductor M42 are p-type metal-oxide-semiconductor, and the 4th 13 metal-oxide-semiconductor M43, the 44th metal-oxide-semiconductor M44, the 45th metal-oxide-semiconductor M45, the 46th metal-oxide-semiconductor M46, the 47th metal-oxide-semiconductor M47, the 48th metal-oxide-semiconductor M48, the 49th metal-oxide-semiconductor M49, the 50th metal-oxide-semiconductor M50, the 51st metal-oxide-semiconductor M51 and the 50th Two metal-oxide-semiconductor M52 are N-type metal-oxide-semiconductor；The source electrode of 39th metal-oxide-semiconductor M39, the source electrode of the 40th metal-oxide-semiconductor M40, the 41st The grid of the source electrode of metal-oxide-semiconductor M41, the source electrode of the 42nd metal-oxide-semiconductor M42 and the 45th metal-oxide-semiconductor M45 accesses power supply, third The grid of the grid of 19 metal-oxide-semiconductor M39, the grid of the 42nd metal-oxide-semiconductor M42 and the 52nd metal-oxide-semiconductor M52 connects and it is connected End for the one or three input or it is non-/ or door Q1 clock end；The drain electrode of 39th metal-oxide-semiconductor M39, the leakage of the 40th metal-oxide-semiconductor M40 The drain electrode of grid, the 43rd metal-oxide-semiconductor M43 of pole, the 41st metal-oxide-semiconductor M41 is connected with the grid of the 44th metal-oxide-semiconductor M44 And its connecting pin be the one or three input or it is non-/ or door Q1 or logic output end, the grid of the 40th metal-oxide-semiconductor M40, the 40th The drain electrode of one metal-oxide-semiconductor M41, the drain electrode of the 42nd metal-oxide-semiconductor M42, the 43rd metal-oxide-semiconductor M43 grid and the 44th metal-oxide-semiconductor The drain electrode of M44 connect and its connecting pin be the one or three input or non-/ or door Q1's or logic output terminal, the 43rd metal-oxide-semiconductor M43 Source electrode, the drain electrode of the 45th metal-oxide-semiconductor M45, the drain electrode of the 46th metal-oxide-semiconductor M46, the drain electrode of the 48th metal-oxide-semiconductor M48 and The drain electrode of 50th metal-oxide-semiconductor M50 connects, the source electrode and the 4th of the source electrode of the 44th metal-oxide-semiconductor M44, the 45th metal-oxide-semiconductor M45 The drain electrode of 17 metal-oxide-semiconductor M47 connects, the source electrode and the 40th of the source electrode of the 46th metal-oxide-semiconductor M46, the 47th metal-oxide-semiconductor M47 The drain electrode of nine metal-oxide-semiconductor M49 connects, and the grid of the 46th metal-oxide-semiconductor M46 is the one or three input or non-/ or the first input of door Q1 End, the grid of the 47th metal-oxide-semiconductor M47 are the one or three input or non-/ or the first inverting input terminal of door Q1, the 48th MOS The grid of pipe M48 is the one or three input or non-/ or the second input terminal of door Q1, and the grid of the 49th metal-oxide-semiconductor M49 is the one or three The second inverting input terminal of input or non-/ or door Q1, the grid of the 50th metal-oxide-semiconductor M50 are the one or three input or non-/ or door Q1 Third input terminal, the grid of the 51st metal-oxide-semiconductor M51 are the one or three input or non-/ or the third inverting input terminal of door Q1, the 4th The drain electrode of the source electrode of 18 metal-oxide-semiconductor M48, the source electrode of the 49th metal-oxide-semiconductor M49 and the 51st metal-oxide-semiconductor M51 connects, and the 50th The drain electrode of the source electrode of metal-oxide-semiconductor M50, the source electrode of the 51st metal-oxide-semiconductor M51 and the 52nd metal-oxide-semiconductor M52 connects, the 52nd MOS The source electrode of pipe M52 is grounded；Two or three input or it is non-/ door Q2 structure with the one or three input or it is non-/ or door Q1 it is identical.
Using TSMC 65nm CMOS technology device parameters, sensitive amplification is utilized to of the invention using Spectre tool The defence differential power consumption analysis adder of type logic carries out simulation analysis.The p-type MOS breadth length ratio of each logic gate is 120nm/ 60nm, the 4th metal-oxide-semiconductor M4 breadth length ratio are 120nm/60nm, other N-types MOS breadth length ratio takes 240nm/60nm；Phase inverter is selected INVD0 in TSMC standard cell lib, Fig. 8 give partial simulation waveform, and wherein working frequency is 100MHz, first addend A3A2A1A0, second addend B3B2B1B0With carry signal CinRespectively " 10100001... ", " 11000010... " and "01101011...".It can be seen from the figure that adder is in pre-charging stage in clock signal clk=0, each output letter Number by preliminary filling to high level；In clock signal clk=1, adder enters the evaluation stage, exports C3S3S2S1S0For " 10110... ", it is consistent with actual result, it was demonstrated that the defence differential power consumption analysis of the invention using sensitive scale-up version logic adds Musical instruments used in a Buddhist or Taoist mass logic function is correct.
Defence differential power consumption analysis adder of the invention using sensitive scale-up version logic is super with existing traditional 4 Advanced potential adder is compared, and reflects that the anti-DPA of circuit is attacked with the difference of source current, power consumption in the different clocks period Hit performance.Wherein, Fig. 9 is the current curve diagram of existing adder, and Figure 10 is the power consumption profile figure of existing adder；Figure 11 For the current curve diagram of the defence differential power consumption analysis adder of the invention using sensitive scale-up version logic；Figure 12 is the present invention Using sensitive scale-up version logic defence differential power consumption analysis adder power consumption profile figure.Analysis chart 9 and Figure 11 are it is found that existing Some adder source current characteristics relies on input signal, can generate corresponding electric current in varying input signal, and this hair The bright defence differential power consumption analysis adder using sensitive scale-up version logic within each clock cycle, no matter input signal How, all there is roughly the same source current characteristic.Analysis chart 10, Figure 12 are it is found that of the invention patrolled using sensitive scale-up version The defence differential power consumption analysis adder collected all has consistent power consumption profile within the different clock cycle, has power consumption independent In the characteristic of input signal, DPA attack can be effectively resisted.

Claims (5)

1. a kind of defence differential power consumption analysis adder using sensitive scale-up version logic, it is characterised in that including the one or two input With it is non-/ with door, the two or two input with it is non-/ with door, the three or two input with it is non-/ with door, the four or two input with it is non-/ with door, the one or two Input exclusive or/with or door, the two or two input exclusive or/with or door, the three or two input exclusive or/with or door, the four or two input exclusive or/same Or door, the five or two input exclusive or/with or door, the six or two input exclusive or/with or door, the seven or two input exclusive or/with or door, the eight or two Input exclusive or/same or door, the first phase inverter, the second phase inverter, third phase inverter, the 4th phase inverter, the 5th phase inverter, the 6th instead Phase device, the 7th phase inverter, the 8th phase inverter, the 9th phase inverter, the tenth phase inverter, the 11st phase inverter, the 12nd phase inverter, 13 phase inverters, the 14th phase inverter, the 15th phase inverter, the tenth hex inverter, the 17th phase inverter, eighteen incompatibilities phase device, 19th phase inverter, the 20th phase inverter, the 21st phase inverter, the 22nd phase inverter and carry look ahead generation circuit；Institute The carry look ahead generation circuit stated include the five or two input with it is non-/ with door, the six or two input with it is non-/ with door, the seven or two input with It is non-/ with door, the eight or two input with it is non-/ with door, the 9th 2 input with it is non-/ with door, the 12nd input with it is non-/ with door, the 11st Input with it is non-/ with door, the 12nd input with it is non-/ with door, the 13rd input with it is non-/ with door, the 14th input with it is non-/ with Door, the one or two input or it is non-/ or door, the two or two input or it is non-/ or door, the three or two input or it is non-/ or door, the four or two input or Non-/or it is door, the five or two input or non-/ or door, the six or two input or non-/ or door, the one or three input or non-/ or door, the two or three defeated Enter or non-/ or door, the 23rd phase inverter, the 24th phase inverter, the 25th phase inverter, the 20th hex inverter, second 17 phase inverters, the second eighteen incompatibilities phase device, the 29th phase inverter, the 30th phase inverter, the 31st phase inverter, the 32nd Phase inverter, the 33rd phase inverter, the 34th phase inverter, the 35th phase inverter, the 30th hex inverter, the 37th are instead Phase device, third eighteen incompatibilities phase device, the 39th phase inverter, the 40th phase inverter, the 41st phase inverter, the 42nd reverse phase Device, the 43rd phase inverter, the 44th phase inverter, the 45th phase inverter, the 40th hex inverter, the 47th reverse phase Device, the 4th eighteen incompatibilities phase device, the 49th phase inverter and the 50th phase inverter；Described one or two input with it is non-/ with door, described The two or two input with it is non-/ with door, described three or two input with it is non-/ with door, the four or two input with it is non-/ with door, institute The five or two input stated with it is non-/ with door, described six or two input with it is non-/ with door, the seven or two input with it is non-/ with door, Described eight or two input with it is non-/ with door, the 9th 2 input with it is non-/ with door, the 12nd input with it is non-/ with Door, described 11st input with it is non-/ with door, the 12nd input with it is non-/ with door, the 13rd input With it is non-/ with door and described 14th input with it is non-/ with door be respectively provided with first input end, the first inverting input terminal, second Input terminal, the second inverting input terminal, clock end, NAND Logic output end and and logic output terminal；One or two input is different Or/same or door, the two or the two input exclusive or/same or door, the three or two input exclusive or/same or the door, the described the 4th Two input exclusive or/same or door, the five or the two input exclusive or/same or door, the six or two input exclusive or/same or the door, institute The seven or the two input exclusive or/same or door and the eight or the two input exclusive or/same or door stated are respectively provided with first input end, first Inverting input terminal, the second input terminal, the second inverting input terminal, clock end, same or logic output terminal and XOR logic output end；Institute The one or two input stated or non-/ or door, described two or two input or non-/ or door, the three or two input or non-/ or door, Described four or two input or non-/ or door, the five or two input or non-/ or door and the six or two input or non-/ or Door is respectively provided with first input end, the first inverting input terminal, the second input terminal, the second inverting input terminal, clock end, or logic Output end and/or logic output terminal；Described one or three input or non-/ or door and the two or three input or non-/ or door have First input end, the first inverting input terminal, the second input terminal, the second inverting input terminal, third input terminal, third anti-phase input End, clock end, or logic output end and/or logic output terminal；
Described five or two input with it is non-/ with the clock end of door, the described the 6th 2 input with it is non-/ with the clock end of door, described The seven or two input with it is non-/ with the clock end of door, the eight or two input with it is non-/ with the clock end of door, the described the 9th 2 Input with it is non-/ with the clock end of door, the 12nd input with it is non-/ with the clock end of door, the 11st input with It is non-/ with the clock end of door, the 12nd input with it is non-/ with the clock end of door, the 13rd input with it is non-/ with The clock end of door, described 14th input with it is non-/ with the clock end of door, the one or two input or non-/ or door when It is Zhong Duan, the clock end of described two or two input or non-/ or door, the clock end of the three or two input or non-/ or door, described The four or two input or non-/ or clock end of door, the clock end of described five or two input or non-/ or door, the described the 6th 2 The clock end of input or non-/ or door, the clock end of described one or three input or non-/ or door and the two or three input or It is non-/ or door clock end connection and its connecting pin be the carry look ahead generation circuit clock end；Described the five or two is defeated Enter with it is non-/ with the first input end of door, the 11st input with it is non-/ with the first input end of door, the described the 13rd Two inputs with it is non-/ with the first input end of door and the described 14th input with it is non-/ connect with the first input end of door and its Connecting pin is that the 4th carry of the carry look ahead generation circuit transmits signal input part, for inputting the 4th carry transmission letter Number；Described five or two input with it is non-/ with the first inverting input terminal of door, the 11st input with it is non-/ with door the One inverting input terminal, described 13rd input and non-/ the first inverting input terminal and the 14th input with door With it is non-/ connect with the first inverting input terminal of door and its connecting pin be the carry look ahead generation circuit the 4th reverse phase carry Signal input part is transmitted, transmits signal for inputting the 4th reverse phase carry；Described five or two input with it is non-/ with it is the second of door defeated The second input terminal for entering end and described four or two input or non-/ or door connect and its connecting pin is the carry look ahead generation The third carry of circuit generates signal input part, generates signal for inputting third carry；Described five or two input with it is non-/ with Second inverting input terminal of the second inverting input terminal of door and described four or two input or non-/ or door connects and its connecting pin is The third reverse phase carry of the carry look ahead generation circuit generates signal input part, generates letter for inputting third reverse phase carry Number；Described six or two input with it is non-/ with the first input end of door, the 9th 2 input with it is non-/ the first input with door End and described 12nd input with it is non-/ connect with the first input end of door and its connecting pin is the carry look ahead generation The third carry of circuit transmits signal input part, for inputting third carry transmission signal；Described six or two input with it is non-/ with First inverting input terminal of door, described 9th 2 input and non-/ the first inverting input terminal and the described the 12nd with door Input with it is non-/ connect with the first inverting input terminal of door and its connecting pin for the carry look ahead generation circuit third reverse phase Carry transmits signal input part, for inputting third reverse phase carry transmission signal；Described six or two input with it is non-/ with door the The third input terminal of two input terminals and described one or three input or non-/ or door connect and its connecting pin is the carry look ahead Second carry of generation circuit generates signal input part, generates signal for inputting the second carry；Described six or two input with It is non-/ connect with the third inverting input terminal of the second inverting input terminal of door and described one or three input or non-/ or door and its company It connects the second reverse phase carry that end is the carry look ahead generation circuit and generates signal input part, for inputting the second reverse phase carry Generate signal；Described seven or two input with it is non-/ with the first input end of door and the 12nd input with it is non-/ with door the The connection of one input terminal and its connecting pin are that the second carry of the carry look ahead generation circuit transmits signal input part, for defeated Enter the second carry transmission signal；Described seven or two input with it is non-/ defeated with the first inverting input terminal of door and the described the 12nd Enter with it is non-/ connect with the first inverting input terminal of door and its connecting pin be the carry look ahead generation circuit the second reverse phase into Transmission signal input part in position transmits signal for inputting the second reverse phase carry；Described seven or two input with it is non-/ with door second Second input terminal of input terminal and described five or two input or non-/ or door connect and its connecting pin is the carry look ahead production First carry of raw circuit generates signal input part, generates signal for inputting the first carry；Described seven or two input with it is non-/ It is connect with the second inverting input terminal of the second inverting input terminal of door and described five or two input or non-/ or door and its connecting pin Signal input part is generated for the first reverse phase carry of the carry look ahead generation circuit, is generated for inputting the first reverse phase carry Signal；Described eight or two input with it is non-/ with the first input end of door be the carry look ahead generation circuit the first carry Signal input part is transmitted, transmits signal P0 for inputting the first carry；Described eight or two input and non-/ the first reverse phase with door Input terminal be the carry look ahead generation circuit the first reverse phase carry transmit signal input part, for input the first reverse phase into Position transmission signalDescribed eight or two input with it is non-/ with the second input terminal of door be the carry look ahead generation circuit Low order carry signal input part, for inputting low order carry signal；Described eight or two input with it is non-/ defeated with the second reverse phase of door Enter the reverse phase low order carry signal input part that end is the carry look ahead generation circuit, believes for input inversion low order carry Number；Described five or two input with it is non-/ connect with the NAND Logic output end of door and the input terminal of the 23rd phase inverter Connect, described five or two input with it is non-/ connect with the input terminal of logic output terminal and the 24th phase inverter with door, Described six or two input with it is non-/ connect with the input terminal of the NAND Logic output end of door and the 25th phase inverter, Described six or two input with it is non-/ connect with the input terminal of logic output terminal and the 20th hex inverter with door, institute The seven or two input stated with it is non-/ connect with the input terminal of the NAND Logic output end of door and the 27th phase inverter, institute The seven or two input stated with it is non-/ connect with the input terminal of logic output terminal and the second eighteen incompatibilities phase device with door, it is described The eight or two input with it is non-/ connect with the input terminal of the NAND Logic output end of door and the 29th phase inverter, it is described The eight or two input with it is non-/ connect with the input terminal of logic output terminal and the 30th phase inverter with door, described the 92 inputs with it is non-/ connect with the input terminal of the NAND Logic output end of door and the 31st phase inverter, described the 92 inputs with it is non-/ connect with the input terminal of logic output terminal and the 32nd phase inverter with door, the described the tenth Two inputs with it is non-/ connect with the input terminal of the NAND Logic output end of door and the 33rd phase inverter, the described the tenth Two inputs with it is non-/ connect with the input terminal of logic output terminal and the 34th phase inverter with door, the described the 11st Two inputs with it is non-/ connect with the input terminal of the NAND Logic output end of door and the 35th phase inverter, the described the tenth One or two inputs with it is non-/ connect with the input terminal of logic output terminal and the 30th hex inverter with door, the described the tenth Two or two inputs with it is non-/ connect with the input terminal of the NAND Logic output end of door and the 37th phase inverter, described the 12 inputs with it is non-/ connect with the input terminal of logic output terminal and the third eighteen incompatibilities phase device with door, described the 13 inputs with it is non-/ connect with the input terminal of the NAND Logic output end of door and the 39th phase inverter, it is described 13rd input with it is non-/ connect with the input terminal of logic output terminal and the 40th phase inverter with door, described the 14 inputs with it is non-/ connect with the input terminal of the NAND Logic output end of door and the 41st phase inverter, it is described 14th input with it is non-/ connect with the input terminal of logic output terminal and the 42nd phase inverter with door, it is described One or two input or it is non-/ or the or logic output end of door connected with the input terminal of the 43rd phase inverter, it is described One or two input or non-/ or door or logic output terminal connected with the input terminal of the 44th phase inverter, described the Two or two inputs or non-/ or the or logic output end of door are connected with the input terminal of the 45th phase inverter, and described the Two or two input or it is non-/ door or logic output terminal connected with the input terminal of the 40th hex inverter, the third Two input or it is non-/ or the or logic output end of door connected with the input terminal of the 47th phase inverter, the third Two input or it is non-/ door or logic output terminal connected with the input terminal of the 4th eighteen incompatibilities phase device, the described the 4th 2 Input or it is non-/ or the or logic output end of door connected with the input terminal of the 49th phase inverter, the described the 4th 2 Input or it is non-/ door or logic output terminal connect with the input terminal of the 50th phase inverter, the described the 23rd instead The output end of phase device and described two or two input or non-/ or the first input end of door connect, the 24th phase inverter Output end and described two or two input or it is non-/ or the first inverting input terminal of door connect, the 25th phase inverter Output end, described 11st input with it is non-/ with the second input terminal of door and the four or two input or non-/ or door First input end connection, the output end of the 20th hex inverter, described 11st input with it is non-/ with door second Inverting input terminal and described four or two input or non-/ or the first inverting input terminal of door connect, the 27th reverse phase The output end of device, described 9th 2 input with it is non-/ with the second input terminal of door and the one or three input or non-/ or door The connection of second input terminal, the output end of the second eighteen incompatibilities phase device, described 9th 2 input with it is non-/ with it is the second of door anti- Phase input terminal and described one or three input or non-/ or the second inverting input terminal of door connect, the 29th phase inverter Output end, described 12nd input with it is non-/ with the second input terminal of door and the five or two input or non-/ or door the The connection of one input terminal, the output end of the 30th phase inverter, described 12nd input with it is non-/ defeated with the second reverse phase of door Enter end and the described 5th 2 to input or non-/ or the first inverting input terminal of door connect, the 31st phase inverter it is defeated Outlet, described 13rd input with it is non-/ with the second input terminal of door and the three or two input or non-/ or door second Input terminal connection, the output end of the 32nd phase inverter, described 13rd input and non-/ the second reverse phase with door Input terminal and described three or two input or non-/ or the second inverting input terminal of door connect, the 33rd phase inverter Output end, described 12nd input with it is non-/ with the second input terminal of door and the one or three input or non-/ or door the The connection of one input terminal, the output end of the 34th phase inverter, described 12nd input with it is non-/ with it is the second of door anti- Phase input terminal and described one or three input or non-/ or the first inverting input terminal of door connect, the 35th phase inverter Output end and described one or two input or it is non-/ or the second input terminal of door connect, the 30th hex inverter it is defeated Outlet and described one or two input or non-/ or the second inverting input terminal of door connect, the 37th phase inverter it is defeated Outlet, described 14th input with it is non-/ with the second input terminal of door and the three or two input or non-/ or door first Input terminal connection, the output end of the third eighteen incompatibilities phase device, described 14th input and non-/ the second reverse phase with door Input terminal and described three or two input or non-/ or the first inverting input terminal of door connect, the 39th phase inverter Output end and described one or two input or non-/ or the first input end of door connect, the output end of the 40th phase inverter It is connected with described one or two input or non-/ or the first inverting input terminal of door, the output end of the 41st phase inverter It is connected with described two or three input or non-/ or the first input end of door, the output end of the 42nd phase inverter and institute The two or three input stated or non-/ or the first inverting input terminal connection of door, the output end of the 43rd phase inverter and institute The two or three input stated or non-/ or the second input terminal connection of door, the output end of the 44th phase inverter and described Two or three input or non-/ or the second inverting input terminal connection of door, the output end of the 45th phase inverter and described Two or three input or it is non-/ or door third input terminal connection, the output end and described second of the 40th hex inverter Three input or it is non-/ or door third inverting input terminal connection, the output end and the described the 6th of the 47th phase inverter Two inputs or non-/ or the first input end connection of door, the output end of the 4th eighteen incompatibilities phase device and the described the 6th 2 defeated Enter or non-/ or door the connection of the first inverting input terminal, the output end of the 49th phase inverter and the described the 6th 2 defeated Enter or non-/ or door the connection of the second input terminal, the output end of the 50th phase inverter and the six or two input or non-/ Or the second inverting input terminal connection of door, the or logic output end of described five or two input or non-/ or door are described super The high-order carry signal output end of the first of advanced potential generation circuit, for exporting the first high-order carry signal, the described the 5th 2 Input or it is non-/ door or logic output terminal be the carry look ahead generation circuit the first reverse phase high position carry signal export End, for exporting the first reverse phase high position carry signal, described one or three input or non-/ or the or logic output end of door are institute The high-order carry signal output end of the second of the carry look ahead generation circuit stated, for exporting the second high-order carry signal；Described One or three input or it is non-/ door or logic output terminal be the carry look ahead generation circuit the second reverse phase high position carry believe Number output end, for exporting the second reverse phase high position carry signal；Described six or two input or non-/ or the or logic output of door End is the third high position carry signal output end of the carry look ahead generation circuit, for exporting third high position carry signal, Described six or two input or non-/ or door or logic output terminal be the carry look ahead generation circuit third reverse phase it is high-order Carry signal output end, it is the two or three input or non-/ or door or non-patrol for exporting third reverse phase high position carry signal The 4th high-order carry signal output end that output end is the carry look ahead generation circuit is collected, for exporting the 4th high position carry Signal；Described two or three input or non-/ or door or logic output terminal be the 4th anti-of the carry look ahead generation circuit Mutually high-order carry signal output end, for exporting the 4th reverse phase high position carry signal；Described two or two input or non-/ or door Second input terminal is that the 4th carry of the carry look ahead generation circuit generates signal input part, is produced for inputting the 4th carry Raw signal；Second inverting input terminal of described two or two input or non-/ or door is the of the carry look ahead generation circuit Four reverse phase carries generate signal input part, generate signal for inputting the 4th reverse phase carry；Described one or two input with it is non-/ with The clock end of door, described two or two input with it is non-/ with the clock end of door, the three or two input and non-/ clock with door End, described four or two input with it is non-/ with the clock end of door, the described the 1st input exclusive or/together or the clock end of door, described The two or two input exclusive or/with or the clock end of door, described three or the two input exclusive or/with or door clock end, described the Four or two input exclusive or/same or door clock end, the five or two input exclusive or/same or door the clock end, the described the 6th 2 Input exclusive or/same or door clock end, the seven or two input exclusive or/same or door the clock end, the eight or two input Exclusive or/same or door clock end is connected with the clock end of the carry look ahead generation circuit, and the carry look ahead generates electricity The low order carry signal input part on road is connected with the five or two input exclusive or/same or door second inverting input terminal and it connects Connect the low order carry signal input part that end is the adder；The reverse phase low order carry of the carry look ahead generation circuit is believed Number input terminal and the five or the two input exclusive or/with or the second input terminal of door connect and its connecting pin is the adder Reverse phase low order carry signal input part；Described one or two input and non-/ first input end and the described the 1st with door It inputs exclusive or/same or door first input end connection and its connecting pin is the first input end of the adder, for inputting First signal of first four addend signal；Described one or two input and non-/ the first inverting input terminal with door and institute The one or the two input exclusive or stated/with or door the connection of the first inverting input terminal and its connecting pin be the first anti-of the adder Phase input terminal, for inputting the first bit Inverting signal of first four addend signal；Described one or two input and non-/ and door The second input terminal and described one or the two input exclusive or/with or the second input terminal of door connect and its connecting pin is described adds Second input terminal of musical instruments used in a Buddhist or Taoist mass, for inputting first signal of second four addend signal, the one or two input with it is non-/ With the second inverting input terminal of door and described one or the two input exclusive or/with or the second inverting input terminal of door connect and its connection End is the second inverting input terminal of the adder, for inputting the first bit Inverting signal of second four addend signal； Described two or two input with it is non-/ with the first input end of door and the two or the two input exclusive or/with or door the first input End connection and its connecting pin are the third input terminal of the adder, for inputting the second of first four addend signal Signal；Described two or two input with it is non-/ with the first inverting input terminal of door and the two or the two input exclusive or/with or door The connection of first inverting input terminal and its connecting pin are the third inverting input terminal of the adder, for inputting first four The second inversion signal of addend signal；Described two or two input and non-/ the second input terminal and the described the 2nd 2 with door It inputs exclusive or/same or door the second input terminal connection and its connecting pin is the 4th input terminal of the adder, for inputting The second signal of second four addend signal；Described two or two input and non-/ the second inverting input terminal with door and institute The two or the two input exclusive or stated/with or door the connection of the second inverting input terminal and its connecting pin be the 4th anti-of the adder Phase input terminal, for inputting the second inversion signal of second four addend signal；Described three or two input and non-/ and door First input end and described three or the two input exclusive or/with or the first input end of door connect and its connecting pin is described adds 5th input terminal of musical instruments used in a Buddhist or Taoist mass, for inputting the tribute signal of first four addend signal；Described three or two input with it is non-/ With the first inverting input terminal of door and described three or the two input exclusive or/with or the first inverting input terminal of door connect and its connection End is the 5th inverting input terminal of the adder, for inputting the third bit Inverting signal of first four addend signal； Described three or two input with it is non-/ with the second input terminal of door and the three or the two input exclusive or/with or door the second input End connection and its connecting pin are the 6th input terminal of the adder, for inputting the third position of second four addend signal Signal；Described three or two input with it is non-/ with the second inverting input terminal of door and the three or the two input exclusive or/with or door The connection of second inverting input terminal and its connecting pin are the 6th inverting input terminal of the adder, for inputting second four The third bit Inverting signal of addend signal；Described four or two input and non-/ first input end and the described the 4th 2 with door It inputs exclusive or/same or door first input end connection and its connecting pin is the 7th input terminal of the adder, for inputting 4th signal of first four addend signal；Described four or two input and non-/ the first inverting input terminal with door and institute The four or the two input exclusive or stated/with or door the connection of the first inverting input terminal and its connecting pin be the 7th anti-of the adder Phase input terminal, for inputting the 4th bit Inverting signal of first four addend signal；Described four or two input and non-/ and door The second input terminal and described four or the two input exclusive or/with or the second input terminal of door connect and its connecting pin is described adds 8th input terminal of musical instruments used in a Buddhist or Taoist mass, for inputting the 4th signal of second four addend signal；Described four or two input with it is non-/ With the second inverting input terminal of door and described four or the two input exclusive or/with or the second inverting input terminal of door connect and its connection End is the 8th inverting input terminal of the adder, for inputting the 4th bit Inverting signal of second four addend signal； Described one or two input with it is non-/ connect with the input terminal of the NAND Logic output end of door and first phase inverter, it is described The first carry of output end and the carry look ahead generation circuit of the first phase inverter generate signal input part and connect, it is described The one or two input with it is non-/ connect with the input terminal of logic output terminal and second phase inverter with door, described second The output end of phase inverter generates signal input part with the first reverse phase carry of the carry look ahead generation circuit and connects, described One or two input exclusive or/with or the XOR logic output end of door is connected with the input terminal of the third phase inverter, described the The output end of three phase inverters, the first reverse phase carry transmission signal input part of the carry look ahead generation circuit and described the Five or two input exclusive or/same or door the second inverting input terminal connection, the one or two input exclusive or/same or door the same or logic Output end is connected with the input terminal of the 4th phase inverter, output end, the carry look ahead of the 4th phase inverter The first carry transmission signal input part of generation circuit and the five or two input exclusive or/same or door second input terminal connect Connect, described two or two input with it is non-/ connect with the input terminal of the NAND Logic output end of door and the 5th phase inverter, institute The output end for the 5th phase inverter stated generates signal input part with the second carry of the carry look ahead generation circuit and connects, institute The two or two input stated with it is non-/ connect with the input terminal of logic output terminal and the hex inverter with door, described the The output end of hex inverter generates signal input part with the second reverse phase carry of the carry look ahead generation circuit and connects, described The two or two input exclusive or/with or the XOR logic output end of door connected with the input terminal of the 7th phase inverter, it is described The second reverse phase carry transmission signal input part and described of the output end of 7th phase inverter, the carry look ahead generation circuit Six or two input exclusive or/with or door the connection of the second inverting input terminal, described two or the two input exclusive or/with or door same or patrol Volume output end is connected with the input terminal of the 8th phase inverter, the output end of the 8th phase inverter, it is described it is advanced into The second carry transmission signal input part of position generation circuit and the six or two input exclusive or/same or door second input terminal connect Connect, described three or two input with it is non-/ connect with the input terminal of the NAND Logic output end of door and the 9th phase inverter, institute The output end for the 9th phase inverter stated generates signal input part with the third carry of the carry look ahead generation circuit and connects, institute The three or two input stated with it is non-/ connect with the input terminal of logic output terminal and the tenth phase inverter with door, described the The output end of ten phase inverters generates signal input part with the third reverse phase carry of the carry look ahead generation circuit and connects, described The three or two input exclusive or/with or the XOR logic output end of door connected with the input terminal of the 11st phase inverter, it is described The output end of the 11st phase inverter, the carry look ahead generation circuit third reverse phase carry transmission signal input part and institute The seven or two input exclusive or/same or door the second inverting input terminal connection stated, the three or the two input exclusive or/same or door same Or logic output terminal is connected with the input terminal of the 12nd phase inverter, it is the output end of the 12nd phase inverter, described Carry look ahead generation circuit third carry transmission signal input part and described seven or the two input exclusive or/with or door second Input terminal connection, described four or two input with it is non-/ defeated with the NAND Logic output end of door and the 13rd phase inverter Enter end connection, the output end of the 13rd phase inverter and the 4th carry of the carry look ahead generation circuit generate signal Input terminal connection, described four or two input and non-/ input with logic output terminal and the 14th phase inverter with door End connection, the output end of the 14th phase inverter and the 4th reverse phase carry of the carry look ahead generation circuit generate letter The connection of number input terminal, the four or the two input exclusive or/with or door XOR logic output end and the 15th phase inverter Input terminal connection, the 4th reverse phase carry of the output end of the 15th phase inverter, the carry look ahead generation circuit Transmission signal input part is connected with the eight or two input exclusive or/same or door second inverting input terminal, and the described the 4th 2 Input exclusive or/same or door same or logic output terminal is connected with the input terminal of the tenth hex inverter, and the described the 16th The output end of phase inverter, the 4th carry transmission signal input part of the carry look ahead generation circuit and the described the 8th 2 are defeated Enter exclusive or/same or door the second input terminal connection, the high-order carry signal output end of the first of the carry look ahead generation circuit It is connected with the input terminal of the 17th phase inverter, the output end of the 17th phase inverter and the six or two input Exclusive or/same or door the first inverting input terminal connection, the first reverse phase high position carry signal of the carry look ahead generation circuit Output end is connected with the input terminal of the eighteen incompatibilities phase device, the output end and the described the 6th of the eighteen incompatibilities phase device Two input exclusive or/same or door first input end connection, the high-order carry signal of the second of the carry look ahead generation circuit are defeated Outlet is connected with the input terminal of the 19th phase inverter, the output end and the described the 7th 2 of the 19th phase inverter Input exclusive or/same or door the first inverting input terminal connection, the second reverse phase high position carry of the carry look ahead generation circuit Signal output end is connected with the input terminal of the 20th phase inverter, the output end of the 20th phase inverter and described Seven or two input exclusive or/same or door first input end connection, the third high position carry letter of the carry look ahead generation circuit Number output end is connected with the input terminal of the 21st phase inverter, the output end of the 21st phase inverter and described The eight or two input exclusive or/with or door the first inverting input terminal connection, the third reverse phase of the carry look ahead generation circuit High-order carry signal output end is connected with the input terminal of the 22nd phase inverter, the 22nd phase inverter it is defeated Outlet and described eight or the two input exclusive or/with or the first input end of door connect, the of the carry look ahead generation circuit Four high-order carry signal output ends are the high-order carry signal output end of the adder, the carry look ahead generation circuit The 4th reverse phase high position carry signal output end be the adder reverse phase high position carry signal output end；Described the 5th Two input exclusive or/same or door same or output end is the first output end of the adder, the five or the two input exclusive or/ Same or door exclusive or output end is the first reversed-phase output of the adder, the six or the two input exclusive or/same or door Same or output end be the adder second output terminal, described six or the two input exclusive or/with or door exclusive or output End is the second reversed-phase output of the adder, and the seven or two input exclusive or/same or door the same or output end is institute The third output end for the adder stated, the seven or two input exclusive or/same or door the exclusive or output end is the adder Third reversed-phase output, described eight or the two input exclusive or/with or the same or output end of door be the 4th of the adder Output end, the eight or two input exclusive or/same or door the exclusive or output end are the 4th reversed-phase output of the adder.
2. a kind of defence differential power consumption analysis adder using sensitive scale-up version logic according to claim 1, special Sign be the one or two input with it is non-/ with door include the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, third metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the Five metal-oxide-semiconductors, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor, the 9th metal-oxide-semiconductor, the tenth metal-oxide-semiconductor, the 11st metal-oxide-semiconductor and the 12nd Metal-oxide-semiconductor；First metal-oxide-semiconductor, second metal-oxide-semiconductor, the third metal-oxide-semiconductor and the 4th metal-oxide-semiconductor is p-type Metal-oxide-semiconductor, it is the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor, described 9th metal-oxide-semiconductor, the tenth metal-oxide-semiconductor, the 11st metal-oxide-semiconductor and the 12nd metal-oxide-semiconductor are N-type metal-oxide-semiconductor；Institute The source electrode for the first metal-oxide-semiconductor stated, the source electrode of second metal-oxide-semiconductor, the source electrode of the third metal-oxide-semiconductor, the 4th MOS The grid of the source electrode of pipe and the 7th metal-oxide-semiconductor accesses power supply, the grid of first metal-oxide-semiconductor, the 4th MOS The connection of the grid of the grid of pipe and the 12nd metal-oxide-semiconductor and its connecting pin be described one or two input with it is non-/ with door Clock end, the drain electrode of first metal-oxide-semiconductor, the drain electrode of second metal-oxide-semiconductor, the third metal-oxide-semiconductor grid, described The drain electrode of the 5th metal-oxide-semiconductor and the grid connection of the 6th metal-oxide-semiconductor and its connecting pin be described one or two input and non-/ With the NAND Logic output end of door, the grid of second metal-oxide-semiconductor, the drain electrode of the third metal-oxide-semiconductor, the described the 4th The drain electrode of metal-oxide-semiconductor, the 5th metal-oxide-semiconductor grid connected with the drain electrode of the 6th metal-oxide-semiconductor and its connecting pin is described The one or two input with it is non-/ with door and logic output terminal, the leakage of the source electrode, the 7th metal-oxide-semiconductor of the 5th metal-oxide-semiconductor Pole is connected with the drain electrode of the 8th metal-oxide-semiconductor, the source electrode of the 6th metal-oxide-semiconductor, the source electrode of the 7th metal-oxide-semiconductor, institute The drain electrode for the 9th metal-oxide-semiconductor stated is connected with the drain electrode of the 11st metal-oxide-semiconductor, the source electrode of the 8th metal-oxide-semiconductor, described The drain electrode of tenth metal-oxide-semiconductor is connected with the source electrode of the 9th metal-oxide-semiconductor, and the grid of the 8th metal-oxide-semiconductor is described first Two inputs with it is non-/ with the first input end of door, the grid of the 9th metal-oxide-semiconductor is the one or two input and non-/ and door The first inverting input terminal, the grid of the tenth metal-oxide-semiconductor is the one or two input and non-/ the second input with door End, the grid of the 11st metal-oxide-semiconductor is the one or two input and non-/ the second inverting input terminal with door, described The source electrode of tenth metal-oxide-semiconductor, the 11st metal-oxide-semiconductor source electrode connected with the drain electrode of the 12nd metal-oxide-semiconductor, described The source electrode of 12 metal-oxide-semiconductors is grounded；Described two or two input with it is non-/ with door, the described the 3rd 2 input with it is non-/ with door, described The four or two input with it is non-/ with door, described five or two input with it is non-/ with door, the six or two input with it is non-/ with door, institute The seven or two input stated with it is non-/ with door, described eight or two input with it is non-/ with door, the 9th 2 input with it is non-/ with door, Described 12nd input with it is non-/ with door, the 11st input with it is non-/ with door, the 12nd input with it is non-/ With door, described 13rd input with it is non-/ with door and the 14th input with it is non-/ with the structure of door and described the One or two input and it is non-/ identical as door.
3. a kind of defence differential power consumption analysis adder using sensitive scale-up version logic according to claim 1, special Sign is that the one or the two input exclusive or/same or door includes the 13rd metal-oxide-semiconductor, the 14th metal-oxide-semiconductor, the 15th metal-oxide-semiconductor, the tenth Six metal-oxide-semiconductors, the 17th metal-oxide-semiconductor, the 18th metal-oxide-semiconductor, the 19th metal-oxide-semiconductor, the 20th metal-oxide-semiconductor, the 21st metal-oxide-semiconductor, the 20th Two metal-oxide-semiconductors, the 23rd metal-oxide-semiconductor, the 24th metal-oxide-semiconductor, the 25th metal-oxide-semiconductor and the 26th metal-oxide-semiconductor；Described the 13rd Metal-oxide-semiconductor, the 14th metal-oxide-semiconductor, the 15th metal-oxide-semiconductor and the 16th metal-oxide-semiconductor are p-type metal-oxide-semiconductor, described The 17th metal-oxide-semiconductor, the 18th metal-oxide-semiconductor, the 19th metal-oxide-semiconductor, the 20th metal-oxide-semiconductor, described It is 21 metal-oxide-semiconductors, the 22nd metal-oxide-semiconductor, the 23rd metal-oxide-semiconductor, the 24th metal-oxide-semiconductor, described The 25th metal-oxide-semiconductor and the 26th metal-oxide-semiconductor be N-type metal-oxide-semiconductor；It is the source electrode of 13rd metal-oxide-semiconductor, described The source electrode of the 14th metal-oxide-semiconductor, the source electrode of the 15th metal-oxide-semiconductor, the source electrode of the 16th metal-oxide-semiconductor and described The grid of 19 metal-oxide-semiconductors accesses power supply, the grid of the 13rd metal-oxide-semiconductor, the grid of the 16th metal-oxide-semiconductor and institute The grid for the 26th metal-oxide-semiconductor stated connects and its connecting pin is the one or two input exclusive or/same or door the clock end, institute The drain electrode for the 13rd metal-oxide-semiconductor stated, the drain electrode of the 14th metal-oxide-semiconductor, the 15th metal-oxide-semiconductor grid, described The drain electrode of 17th metal-oxide-semiconductor is connected with the grid of the 18th metal-oxide-semiconductor and its connecting pin is that the one or two input is different Or/with or door same or logic output terminal, the grid of the 14th metal-oxide-semiconductor, the drain electrode of the 15th metal-oxide-semiconductor, institute The drain electrode for the 16th metal-oxide-semiconductor stated, the 17th metal-oxide-semiconductor grid connected with the drain electrode of the 18th metal-oxide-semiconductor and Its connecting pin is the one or two input exclusive or/same or door the XOR logic output end, the source of the 17th metal-oxide-semiconductor Pole, the drain electrode of the 19th metal-oxide-semiconductor, the drain electrode of the 20th metal-oxide-semiconductor and the drain electrode of the 21st metal-oxide-semiconductor Connection, the leakage of the source electrode, the source electrode, the 22nd metal-oxide-semiconductor of the 19th metal-oxide-semiconductor of the 18th metal-oxide-semiconductor Pole is connected with the drain electrode of the 23rd metal-oxide-semiconductor, the grid and the 23rd MOS of the 20th metal-oxide-semiconductor The grid of pipe connect and its connecting pin be the one or the two input exclusive or/with or door first input end, the described the 20th The source electrode of metal-oxide-semiconductor, the 22nd metal-oxide-semiconductor source electrode connected with the drain electrode of the 24th metal-oxide-semiconductor, described The grid of 21 metal-oxide-semiconductors is connected with the grid of the 22nd metal-oxide-semiconductor and its connecting pin is the one or two input Exclusive or/with or door the first inverting input terminal, the source of the source electrode of the 21st metal-oxide-semiconductor, the 23rd metal-oxide-semiconductor Pole is connected with the drain electrode of the 25th metal-oxide-semiconductor, and the grid of the 24th metal-oxide-semiconductor is the one or two input Exclusive or/with or door the second input terminal, the grid of the 25th metal-oxide-semiconductor be the one or the two input exclusive or/with or Second inverting input terminal of door, the source electrode of the 24th metal-oxide-semiconductor, the source electrode of the 25th metal-oxide-semiconductor and described The 26th metal-oxide-semiconductor drain electrode connection, the 26th metal-oxide-semiconductor source electrode ground connection；Two or the two input exclusive or/ With or door, described three or the two input exclusive or/with or door, the four or the two input exclusive or/with or it is door, the described the 5th 2 defeated Enter exclusive or/with or door, described six or the two input exclusive or/with or door, the seven or the two input exclusive or/with or door and described Eight or two input exclusive or/with or door structure and the described 1st input exclusive or/with or door it is identical.
4. a kind of defence differential power consumption analysis adder using sensitive scale-up version logic according to claim 1, special Sign is the one or two input or non-/ or door includes the 27th metal-oxide-semiconductor, the 28th metal-oxide-semiconductor, the 29th metal-oxide-semiconductor 30th metal-oxide-semiconductor, the 31st metal-oxide-semiconductor, the 33rd metal-oxide-semiconductor of the 32nd metal-oxide-semiconductor, the 34th metal-oxide-semiconductor, the 35th Metal-oxide-semiconductor, the 36th metal-oxide-semiconductor, the 37th metal-oxide-semiconductor and the 38th metal-oxide-semiconductor；
27th metal-oxide-semiconductor, the 28th metal-oxide-semiconductor, the 29th metal-oxide-semiconductor and the described the 30th Metal-oxide-semiconductor is p-type metal-oxide-semiconductor, the 31st metal-oxide-semiconductor, the 32nd metal-oxide-semiconductor, the 33rd MOS Pipe, the 34th metal-oxide-semiconductor, the 35th metal-oxide-semiconductor, the 36th metal-oxide-semiconductor, the described the 37th Metal-oxide-semiconductor and the 38th metal-oxide-semiconductor are N-type metal-oxide-semiconductor；The source electrode of 27th metal-oxide-semiconductor, the described the 20th The source electrode of eight metal-oxide-semiconductors, the source electrode of the 29th metal-oxide-semiconductor, the 30th metal-oxide-semiconductor source electrode and the described the 30th The grid of three metal-oxide-semiconductors accesses power supply, the grid of the 27th metal-oxide-semiconductor, the grid of the 30th metal-oxide-semiconductor and institute The grid of the 38th metal-oxide-semiconductor stated connects and its connecting pin is the clock end of the one or two input or non-/ or door, described The 27th metal-oxide-semiconductor drain electrode, the drain electrode of the 28th metal-oxide-semiconductor, the grid of the 29th metal-oxide-semiconductor, institute The drain electrode for the 31st metal-oxide-semiconductor stated is connected with the grid of the 32nd metal-oxide-semiconductor and its connecting pin is described first The or logic output end of two inputs or non-/ or door, the drain electrode of the 29th metal-oxide-semiconductor, the 30th metal-oxide-semiconductor Drain electrode, the grid of the 28th metal-oxide-semiconductor, the 31st metal-oxide-semiconductor grid and the 32nd metal-oxide-semiconductor Drain electrode connection and its connecting pin be described one or two input or non-/ or door or logic output terminal, the described the 31st The source electrode of metal-oxide-semiconductor, the drain electrode of the 36th metal-oxide-semiconductor, the drain electrode and the described the 30th of the 33rd metal-oxide-semiconductor The drain electrodes of four metal-oxide-semiconductors connects, the source electrode of the 32nd metal-oxide-semiconductor, the source electrode of the 33rd metal-oxide-semiconductor and described The drain electrode of 35th metal-oxide-semiconductor connects, and the grid of the 34th metal-oxide-semiconductor is the one or two input or non-/ or door First input end, the grid of the 35th metal-oxide-semiconductor is that the one or two input or non-/ or the first reverse phase of door are defeated Enter end, the grid of the 36th metal-oxide-semiconductor is the second input terminal of the one or two input or non-/ or door, described The grid of 37th metal-oxide-semiconductor is the second inverting input terminal of described one or two input or non-/ or door, the described the 34th The source electrode of metal-oxide-semiconductor, the 35th metal-oxide-semiconductor source electrode connected with the drain electrode of the 37th metal-oxide-semiconductor, described The source electrode of 36 metal-oxide-semiconductors, the 37th metal-oxide-semiconductor source electrode connected with the drain electrode of the 38th metal-oxide-semiconductor, institute The source electrode for the 38th metal-oxide-semiconductor stated is grounded；Described two or two input or non-/ or door, the three or two input or non-/ or Door, described four or two input or non-/ or door, the five or two input or non-/ or door and the six or two input or non-/ The structure of door and described one or two input or non-/ or door it is identical.
5. a kind of defence differential power consumption analysis adder using sensitive scale-up version logic according to claim 1, special Sign is the one or three input or non-/ or door includes the 39th metal-oxide-semiconductor, the 40th metal-oxide-semiconductor, the 41st metal-oxide-semiconductor, the 42 metal-oxide-semiconductors, the 43rd metal-oxide-semiconductor, the 44th metal-oxide-semiconductor, the 45th metal-oxide-semiconductor, the 46th metal-oxide-semiconductor, the 47th Metal-oxide-semiconductor, the 48th metal-oxide-semiconductor, the 49th metal-oxide-semiconductor, the 50th metal-oxide-semiconductor, the 51st metal-oxide-semiconductor and the 52nd metal-oxide-semiconductor；Institute The 39th metal-oxide-semiconductor, the 40th metal-oxide-semiconductor, the 41st metal-oxide-semiconductor and the 42nd metal-oxide-semiconductor stated It is p-type metal-oxide-semiconductor, it is the 43rd metal-oxide-semiconductor, the 44th metal-oxide-semiconductor, the 45th metal-oxide-semiconductor, described The 46th metal-oxide-semiconductor, the 47th metal-oxide-semiconductor, the 48th metal-oxide-semiconductor, the 49th metal-oxide-semiconductor, 50th metal-oxide-semiconductor, the 51st metal-oxide-semiconductor and the 52nd metal-oxide-semiconductor is N-type metal-oxide-semiconductor；Described The source electrode of 39th metal-oxide-semiconductor, the source electrode of the 40th metal-oxide-semiconductor, the 41st metal-oxide-semiconductor source electrode, described The grid of the source electrode of 42nd metal-oxide-semiconductor and the 45th metal-oxide-semiconductor accesses power supply, the 39th metal-oxide-semiconductor Grid, the 42nd metal-oxide-semiconductor grid connected with the grid of the 52nd metal-oxide-semiconductor and its connecting pin is institute State the one or three input or it is non-/ or door clock end；The drain electrode of 39th metal-oxide-semiconductor, the 40th metal-oxide-semiconductor Drain electrode, the grid of the 41st metal-oxide-semiconductor, the drain electrode of the 43rd metal-oxide-semiconductor and the 44th metal-oxide-semiconductor Grid connection and its connecting pin be described one or three input or non-/ or door or logic output end, the described the 40th The grid of metal-oxide-semiconductor, the drain electrode of the 41st metal-oxide-semiconductor, the drain electrode of the 42nd metal-oxide-semiconductor, the described the 40th The drain electrode connection of the grid of three metal-oxide-semiconductors and the 44th metal-oxide-semiconductor and its connecting pin be the one or three input or non-/ Door or logic output terminal, it is the drain electrode of the source electrode, the 45th metal-oxide-semiconductor of the 43rd metal-oxide-semiconductor, described The drain electrode of 46th metal-oxide-semiconductor, the drain electrode of the 48th metal-oxide-semiconductor are connected with the drain electrode of the 50th metal-oxide-semiconductor, institute The drain electrode of the source electrode for the 44th metal-oxide-semiconductor stated, the source electrode of the 45th metal-oxide-semiconductor and the 47th metal-oxide-semiconductor Connection, the source electrode and the 49th metal-oxide-semiconductor of the source electrode of the 46th metal-oxide-semiconductor, the 47th metal-oxide-semiconductor Drain electrode connection, the grid of the 46th metal-oxide-semiconductor is the first input end of the one or three input or non-/ or door, The grid of 47th metal-oxide-semiconductor is the first inverting input terminal of described one or three input or non-/ or door, described the The grid of 48 metal-oxide-semiconductors is the second input terminal of described one or three input or non-/ or door, the 49th metal-oxide-semiconductor Grid be described one or three input or non-/ or door the second inverting input terminal, the grid of the 50th metal-oxide-semiconductor is institute The third input terminal of the one or three input stated or non-/ or door, the grid of the 51st metal-oxide-semiconductor are the described 1st defeated Enter or non-/ or door third inverting input terminal, the source of the source electrode of the 48th metal-oxide-semiconductor, the 49th metal-oxide-semiconductor Pole is connected with the drain electrode of the 51st metal-oxide-semiconductor, source electrode, the 51st metal-oxide-semiconductor of the 50th metal-oxide-semiconductor Source electrode connected with the drain electrode of the 52nd metal-oxide-semiconductor, the source electrode of the 52nd metal-oxide-semiconductor ground connection；Described The structure of two or three inputs or non-/ or door and described one or three input or non-/ or door are identical.
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