CN106547513B - Utilize the defence differential power consumption analysis adder of sensitive scale-up version logic - Google Patents

Abstract

The invention discloses a defensive differential power analysis adder utilizing sensitive amplified logic, which consists of four two-input NAND/AND gates, eight two-input XOR/XOR gates, twenty-two inverters and The look-ahead carry generating circuit constitutes an adder; the advantage is that the TSMC 65nm CMOS process is adopted, and the circuit is simulated and analyzed by the Specter tool, and the experimental results show that the adder of the present invention has correct logic functions, and is independent in power consumption compared to the traditional adder circuit The performance is improved by 97%, which can effectively resist the analysis of differential power consumption.

Description

Defensive Differential Power Analysis Adder Using Sensitive Amplified Logic

technical field

The invention relates to an adder, in particular to a defensive differential power analysis adder utilizing sensitive amplification logic.

Background technique

With the development of integrated circuits and computer technology, cryptographic devices are widely used in smart cards, e-commerce and other fields, which greatly guarantee the security of the system. However, when cryptographic devices process different data, physical information such as energy consumption, running time, and electromagnetic radiation has a certain correlation with the processed data. Therefore, attackers usually use these physical information to attack cryptographic devices to obtain key information, and this method is called Side Channel Attack (SCA). Among a series of side-channel attack techniques, Differential Power Analysis (DPA) technology is a common and effective side-channel attack method, which seriously threatens the security of cryptographic devices. In recent years, many differential dynamic dual-rail pre-charge logics have been proposed to achieve anti-DPA attacks, such as three-phase dual-rail pre-charge logic (Three-Phase Dual-Rail Pre-charge Logic, TDPL), adiabatic dynamic differential logic (Adiabatic Dynamic Differential Logic, ADDL) And sensitive amplification logic (Sense Amplifier Based Logic, SABL), etc. Compared with SABL, TDPL balances power consumption by introducing an additional discharge stage, which increases its energy consumption. If the attacker modifies the clock to generate a separate discharge stage power consumption, the performance of TDPL against DPA attacks will be greatly reduced; ADDL timing control is complicated, and When interacting with CMOS circuits, complex interface circuits need to be designed. Due to its good anti-DPA attack performance and good compatibility with CMOS circuits, SABL has gradually become the main method for defending against DPA attacks.

Addition is the most commonly used arithmetic operation. In theory, multiplication, subtraction, and division can all be transformed into addition operations. An adder is the most basic component of an arithmetic operator, and is widely used in various digital encryption systems to process data of different word lengths. Since the static complementary CMOS circuit consumes energy only when the output signal flips from 0 to 1, this asymmetric power consumption feature provides a breakthrough for the differential power analysis to successfully crack traditional cryptographic devices.

In view of this, it is of great significance to design a defensive differential power analysis adder using sensitive amplification logic that can defend against DPA attacks by using the characteristics that SABL consumes energy and processed data independently.

Contents of the invention

The technical problem to be solved by the present invention is to provide a defensive differential power analysis adder using sensitive amplification logic that can defend against DPA attacks.

The technical solution adopted by the present invention to solve the above-mentioned technical problems is: a defensive differential power analysis adder utilizing sensitive amplified logic, comprising a first two-input NAND/AND gate, a second two-input NAND/AND gate, The third two-input NAND/AND gate, the fourth two-input NAND/AND gate, the first two-input exclusive-or/same-or gate, the second two-input exclusive-or/same-or gate, the third two-input exclusive-or/same-or gate OR gate, the fourth and second input XOR/same OR gate, the fifth and second input XOR/same OR gate, the sixth and second input XOR/same OR gate, the seventh and second input XOR/same OR gate, the eighth second Input XOR/NOR gate, first inverter, second inverter, third inverter, fourth inverter, fifth inverter, sixth inverter, seventh inverter, Eighth inverter, ninth inverter, tenth inverter, eleventh inverter, twelfth inverter, thirteenth inverter, fourteenth inverter, fifteenth inverter phase, the sixteenth inverter, the seventeenth inverter, the eighteenth inverter, the nineteenth inverter, the twenty-first inverter, the twenty-first inverter, the twenty-second Inverter and advanced carry generating circuit; described advanced carrying generating circuit includes the fifth and second input NAND/AND gate, the sixth and second input NAND/AND gate, the seventh and second input NAND/AND gate, the first Eighty-two input NAND/AND gate, ninth and second input NAND/AND gate, twelfth input NAND/AND gate, eleventh and second input NAND/AND gate, twelfth second input NAND/AND gate , the thirteenth and second input NAND/AND gate, the fourteenth and second input NAND/AND gate, the first and second input NOR/OR gate, the second and second input NOR/OR gate, the third and second input NOR/AND gate, OR gate, fourth second input NOR/OR gate, fifth second input NOR/OR gate, sixth second input NOR/OR gate, first three input NOR/OR gate, second three input NOR/OR gate OR gate, twenty-third inverter, twenty-fourth inverter, twenty-fifth inverter, twenty-sixth inverter, twenty-seventh inverter, twenty-eighth inverter , the 29th inverter, the 30th inverter, the 31st inverter, the 32nd inverter, the 33rd inverter, the 34th inverter, the third The fifteenth inverter, the thirty-sixth inverter, the thirty-seventh inverter, the thirty-eighth inverter, the thirty-ninth inverter, the fortieth inverter, the forty-first inverter phase, forty-second inverter, forty-third inverter, forty-fourth inverter, forty-fifth inverter, forty-sixth inverter, forty-seventh inverter , the forty-eighth inverter, the forty-ninth inverter and the fiftieth inverter; the first two-input NAND/AND gate, the second two-input NAND/AND gate, The third second-input NAND/AND gate, the fourth second-input NAND/AND gate, the fifth second-input NAND/AND gate, the sixth second-input NAND/AND gate gate, the seventh and second input NAND/AND gate, the eighth and second input NAND/AND gate, the ninth and second input NAND/AND gate, the twelfth input NAND /AND gate, the eleventh and second input NAND/AND gate, the twelfth and second input NAND/AND gate, the thirteenth and second input NAND/AND gate and the first The fourteen-two-input NAND/AND gate has a first input terminal, a first inverting input terminal, and a second input terminal respectively. , the second inverting input terminal, the clock terminal, the NAND logic output terminal and the AND logic output terminal; the first two-input XOR/NOR gate, the second two-input XOR/NOR gate, The third two-input XOR/XOR gate, the fourth two-input XOR/XOR gate, the fifth second-input XOR/XOR gate, the sixth second-input XOR gate The OR/XOR gate, the seventh and second input XOR/XOR gate and the eighth second input XOR/XOR gate respectively have a first input terminal, a first inverting input terminal, a second input terminal, the second inverting input terminal, the clock terminal, the NOR logic output terminal and the exclusive OR logic output terminal; the first two-input NOR/OR gate, the second two-input NOR/OR gate, The third two-input NOR/OR gate, the fourth two-input NOR/OR gate, the fifth two-input NOR/OR gate and the sixth two-input NOR/OR gate The gate has a first input terminal, a first inverting input terminal, a second input terminal, a second inverting input terminal, a clock terminal, an NOR logic output terminal and an OR logic output terminal; the first three-input NOR logic output terminal The OR gate and the second three-input NOR/OR gate have a first input terminal, a first inverting input terminal, a second input terminal, a second inverting input terminal, a third input terminal, and a third inverting input terminal. input end, clock end, or non-logic output end and or logic output end; the clock end of the fifth and second input NAND/AND gate, the clock end of the sixth second input NAND/AND gate, all The clock terminal of the seventh and second input NAND/AND gate, the clock terminal of the eighth and second input NAND/AND gate, the clock terminal of the ninth and second input NAND/AND gate, the described The clock end of the twelfth input NAND/AND gate, the clock end of the eleventh and second input NAND/AND gate, the clock end of the twelfth and second input NAND/AND gate, the described The clock end of the thirteenth second input NAND/AND gate, the clock end of the fourteenth second input NAND/AND gate, the clock end of the first two input NOR/OR gate, the described The clock terminal of the second two-input NOR/OR gate, the clock terminal of the third two-input NOR/OR gate, the clock terminal of the fourth two-input NOR/OR gate, the fifth The clock terminal of the two-input NOR/OR gate, the clock terminal of the sixth two-input NOR/OR gate, the clock terminal of the first three-input NOR/OR gate and the second three-input The clock end of the NOR/OR gate is connected and its connection end is the clock end of the described advanced carry generation circuit; the first input end of the fifth and second input NAND/AND gate, the eleventh The first input end of the two-input NAND/AND gate, the first input end of the thirteenth second-input NAND/AND gate and the first input end of the fourteenth second-input NAND/AND gate connected and its connection terminal is the fourth carry transmission signal input terminal of the advanced carry generating circuit, which is used to input the fourth carry transmission signal; the first inverting input of the fifth two-input NAND/AND gate terminal, the first inverting input terminal of the eleventh two-input NAND/AND gate, the first inverting input terminal of the thirteenth two-input NAND/AND gate and the fourteenth The first inverting input end of the two-input NAND/AND gate is connected and its connection end is all The fourth inverting carry transmission signal input terminal of the advanced carry generation circuit is used to input the fourth inverting carry transmission signal; the second input terminal of the fifth two-input NAND/AND gate and the described The second input end of the fourth two-input NOR/OR gate is connected and its connection end is the third carry generation signal input end of the described advanced carry generation circuit, which is used to input the third carry generation signal; The second inverting input end of the five-two-input NAND/AND gate is connected with the second inverting input end of the fourth two-input NOR/OR gate, and its connection end is the advanced carry generation circuit The third inverted carry generation signal input terminal is used to input the third inverted carry generation signal; the first input end of the sixth second input NAND/AND gate, the ninth second input NAND/AND gate The first input end of the gate is connected to the first input end of the twelfth input NAND/AND gate, and its connection end is the third carry transmission signal input end of the advanced carry generation circuit, for Input the third carry transmission signal; the first inverting input terminal of the sixth second input NAND/AND gate, the first inverting input terminal of the ninth second input NAND/AND gate and the described The first inverting input end of the twelfth and second input NAND/AND gate is connected and its connection end is the third inverting carry transmission signal input end of the described advanced carry generating circuit, which is used to input the third inverting carry Transmission signal; the second input end of the sixth second-input NAND/AND gate is connected to the third input end of the first three-input NOR/OR gate, and its connection end is the advanced carry The second carry generation signal input end of the generation circuit is used to input the second carry generation signal; the second inverting input end of the sixth two-input NAND/AND gate and the first three-input NOR/NOR gate The third inversion input end of the OR gate is connected and its connection end is the second inversion carry generation signal input end of the described advanced carry generation circuit, which is used to input the second inversion carry generation signal; the seventh The first input end of the two-input NAND/AND gate is connected to the first input end of the twelfth input NAND/AND gate, and its connection end is the second carry transmission signal of the advanced carry generation circuit The input terminal is used to input the second carry transmission signal; the first inverting input terminal of the seventh second input NAND/AND gate and the first inverting input of the twelfth input NAND/AND gate The terminal is connected and its connection end is the second inverting carry transmission signal input terminal of the described advanced carry generating circuit, which is used to input the second inverting carry transmission signal; the seventh and second input NAND/AND gate of the The second input end is connected with the second input end of the fifth two-input NOR/OR gate and its connection end is the first carry generation signal input end of the described advanced carry generation circuit, which is used to input the first carry generation signal; the second inverting input end of the seventh second input NAND/AND gate is connected with the second inverting input end of the fifth second input NOR/OR gate and its connection end is the The first inverted carry generation signal input end of the advanced carry generation circuit is used to input the first inverted carry generation signal; the first input end of the eighth second input NAND/AND gate is the described The first carry of the look-ahead carry generation circuit The transmission signal input terminal is used to input the first carry transmission signal; the first inversion input terminal of the eighth second input NAND/AND gate is the first inversion carry transmission signal of the advanced carry generation circuit The input terminal is used to input the first inverted carry transmission signal; the second input terminal of the eighth second input NAND/AND gate is the low-order carry signal input terminal of the advanced carry generation circuit, which is used to input Low-order carry signal; the second inverting input terminal of the eighth second-input NAND/AND gate is the inverting low-order carry signal input terminal of the described advanced carry generating circuit, which is used to input the inverting low-order carry signal; The NAND logic output terminal of the fifth second-input NAND/AND gate is connected to the input end of the twenty-third inverter, and the AND logic output of the fifth second-input NAND/AND gate terminal is connected to the input terminal of the twenty-fourth inverter, and the NAND logic output terminal of the sixth and second input NAND/AND gate is connected to the input terminal of the twenty-fifth inverter , the NAND logic output terminal of the sixth and second input NAND/AND gate is connected to the input terminal of the twenty-sixth inverter, and the NAND logic of the seventh and second input NAND/AND gate The output terminal is connected to the input terminal of the twenty-seventh inverter, and the AND logic output terminal of the seventh and second input NAND/AND gate is connected to the input terminal of the twenty-eighth inverter , the NAND logic output end of the eighth second input NAND/AND gate is connected to the input end of the twenty-ninth inverter, and the AND logic of the eighth second input NAND/AND gate The output terminal is connected to the input terminal of the 30th inverter, and the NAND logic output terminal of the ninth and second input NAND/AND gate is connected to the input terminal of the 31st inverter , the NAND logic output terminal of the 92nd input NAND/AND gate is connected to the input terminal of the 32nd inverter, and the NAND logic of the twelfth input NAND/AND gate The output terminal is connected to the input terminal of the thirty-third inverter, and the AND logic output terminal of the twelfth input NAND/AND gate is connected to the input terminal of the thirty-fourth inverter , the NAND logic output terminal of the eleventh-second input NAND/AND gate is connected to the input end of the thirty-fifth inverter, and the eleventh-second input NAND/AND gate Connected with the logic output terminal and the input terminal of the thirty-sixth inverter, the NAND logic output terminal of the twelfth-second input NAND/AND gate and the thirty-seventh inverter The input terminal of the twelfth second input NAND/AND gate is connected to the input terminal of the thirty-eighth inverter, and the thirteenth second input NAND/AND gate is connected to the input terminal of the thirty-eighth inverter. The NAND logic output terminal of the AND gate is connected to the input terminal of the thirty-ninth inverter, and the NAND logic output terminal of the thirteenth and second input NAND/AND gate is connected to the fortieth inverter. The input terminal of the phase device is connected, the NAND logic output terminal of the 14th and 2nd input NAND/AND gate is connected with the input terminal of the 41st inverter, and the 14th 2nd input The AND logic output of the NAND/AND gate is connected to the input of the forty-second inverter, and the NOR logic output of the first two-input NOR/OR gate is connected to the fourth ten The input ends of the three inverters are connected, the OR logic output of the first two-input NOR/OR gate is connected to the input end of the forty-fourth inverter, and the second two-input OR The NOR logic output terminal of the NOR gate is connected to the input terminal of the forty-fifth inverter, and the OR logic output terminal of the second two-input NOR/OR gate is connected to the fortieth inverter. The input terminals of the six inverters are connected, the NOR logic output terminals of the third and second input NOR/OR gates are connected with the input terminals of the forty-seventh inverter, and the third and second input The OR logic output of the NOR/OR gate is connected to the input of the forty-eighth inverter, and the NOR logic output of the fourth second input NOR/OR gate is connected to the fourth The input terminal of the nineteenth inverter is connected, the OR logic output terminal of the fourth and second input NOR/OR gate is connected with the input terminal of the fiftieth inverter, and the twenty-third inverter The output end of the phaser is connected to the first input end of the second two-input NOR/OR gate, and the output end of the twenty-fourth inverter is connected to the second two-input NOR/OR gate. The first inverting input terminal of the gate is connected, the output terminal of the twenty-fifth inverter, the second input terminal of the eleventh second input NAND/AND gate and the fourth second input The first input terminal of the NOR/OR gate is connected, the output terminal of the twenty-sixth inverter, the second inverting input terminal of the eleventh and second input NAND/AND gate and the described The first inverting input end of the fourth and second input NOR/OR gate is connected, the output end of the twenty-seventh inverter, the second input end of the ninth second input NAND/AND gate and The second input terminal of the first three-input NOR/OR gate is connected, the output terminal of the twenty-eighth inverter, the second inverter of the ninth and second input NAND/AND gate The input terminal is connected to the second inverting input terminal of the first three-input NOR/OR gate, the output terminal of the twenty-ninth inverter, the twelfth input NAND/AND gate The second input end of the second input is connected to the first input end of the fifth and second input NOR/OR gate, the output end of the thirtieth inverter, the twelfth input NAND/AND gate The second inverting input terminal of the said fifth and second input NOR/OR gate is connected to the first inverting input terminal of the NOR gate, the output terminal of the thirty-first inverter, the thirteenth and second The second input end of the input NAND/AND gate is connected with the second input end of the third two-input NOR/OR gate, the output end of the thirty-second inverter, the tenth The second inverting input end of the three-two-input NAND/AND gate is connected to the second inverting input end of the third two-input NOR/OR gate, and the output end of the thirty-third inverter , the second input end of the twelfth second-input NAND/AND gate is connected to the first input end of the first three-input NOR/OR gate, and the thirty-fourth inverter The output terminal, the second inverting input terminal of the twelfth input NAND/AND gate and the first inverting input terminal of the first three-input NOR/OR gate are connected, and the third The output terminal of the fifteenth inverter is connected to the second input terminal of the first two-input NOR/OR gate, and the output of the thirty-sixth inverter The end is connected with the second inverting input end of the first two-input NOR/OR gate, the output end of the thirty-seventh inverter, the fourteenth second-input NAND/AND gate The second input end of the second input is connected to the first input end of the third and second input NOR/OR gate, the output end of the thirty-eighth inverter, the fourteenth second input NAND/OR gate The second inverting input terminal of the AND gate is connected to the first inverting input terminal of the third two-input NOR/OR gate, and the output terminal of the thirty-ninth inverter is connected to the first The first input end of the two-input NOR/OR gate is connected, the output end of the fortieth inverter is connected with the first inverting input end of the first two-input NOR/OR gate, and the The output end of the forty-first inverter is connected to the first input end of the second three-input NOR/OR gate, and the output end of the forty-second inverter is connected to the second The first inverting input end of the three-input NOR/OR gate is connected, the output end of the forty-third inverter is connected to the second input end of the second three-input NOR/OR gate, and the The output end of the forty-fourth inverter is connected to the second inverting input end of the second three-input NOR/OR gate, and the output end of the forty-fifth inverter is connected to the The third input terminal of the second three-input NOR/OR gate is connected to the output terminal of the forty-sixth inverter and the third inverting input terminal of the second three-input NOR/OR gate connected, the output end of the forty-seventh inverter is connected to the first input end of the sixth second-input NOR/OR gate, the output end of the forty-eighth inverter is connected to the The first inverting input terminal of the sixth second input NOR/OR gate is connected, the output terminal of the forty-ninth inverter is connected with the second input of the sixth second input NOR/OR gate terminal connection, the output terminal of the fiftieth inverter is connected to the second inverting input terminal of the sixth second-input NOR/OR gate, and the fifth second-input NOR/OR gate The NOR logic output terminal is the first high-order carry signal output terminal of the described advanced carry generation circuit, which is used to output the first high-order carry signal, and the OR logic output terminal of the fifth two-input NOR/OR gate is The first inverted high-order carry signal output terminal of the advanced carry generation circuit is used to output the first inverted high-order carry signal, and the NOR logic output terminal of the first three-input NOR/OR gate is the The second high-order carry signal output terminal of the above-mentioned advanced carry generation circuit is used to output the second high-order carry signal; the OR logic output terminal of the first three-input NOR/OR gate is for the described advanced carry generation The second inverted high-order carry signal output terminal of the circuit is used to output the second inverted high-order carry signal; the NOR logic output terminal of the sixth second-input NOR/OR gate is the advanced carry generation circuit The third high-order carry signal output terminal of the third high-order carry signal output terminal is used to output the third high-order carry signal, and the OR logic output terminal of the sixth second-input NOR/OR gate is the third inverting high-order bit of the advanced carry generation circuit The carry signal output terminal is used to output the third inverted high-order carry signal, and the NOR logic output terminal of the second three-input NOR/OR gate is the fourth high of the advanced carry generation circuit The bit carry signal output terminal is used to output the fourth high-order carry signal; the OR logic output terminal of the second three-input NOR/OR gate is the fourth inverted high-order carry signal output of the advanced carry generation circuit The terminal is used to output the fourth inverted high-order carry signal; the second input terminal of the second two-input NOR/OR gate is the fourth carry generation signal input terminal of the advanced carry generation circuit, which is used for Input the fourth carry generation signal; the second inverting input terminal of the second two-input NOR/OR gate is the fourth inverting carry generation signal input end of the advanced carry generation circuit, used to input the first Four inverted carry generation signals; the clock terminal of the first two-input NAND/AND gate, the clock terminal of the second two-input NAND/AND gate, the third two-input NAND/AND gate The clock terminal of the gate, the clock terminal of the fourth two-input NAND/AND gate, the clock terminal of the first two-input XOR/XOR gate, the second two-input XOR/XOR The clock terminal of the gate, the clock terminal of the third two-input exclusive-or/exclusive-or gate, the clock terminal of the fourth two-input exclusive-or/exclusive-or gate, the fifth two-input exclusive-or/exclusive-or gate The clock terminal of the OR gate, the clock terminal of the sixth second input XOR/XOR gate, the clock end of the seventh second input XOR/XOR gate, the eighth second input XOR/ The clock end of the NOR gate is connected to the clock end of the advanced carry generation circuit, and the low-order carry signal input end of the advanced carry generation circuit is connected to the fifth second input XOR/NOR gate. The two inverting input ends are connected and its connection end is the low-order carry signal input end of the adder; the inverting low-order carry signal input end of the described advanced carry generation circuit and the fifth two-input XOR/ The second input end of the NOR gate is connected and its connection end is the inverting low-order carry signal input end of the adder; the first input end of the first two-input NAND/AND gate and the first input end of the first two-input NAND/AND gate The first input end of a two-input XOR/NOR gate is connected and its connection end is the first input end of the described adder, for inputting the first bit signal of the first four-bit addend signal; The first two-input NAND/AND gate of the first two-input NAND/AND gate is connected with the first two-input XOR/NOR gate's first inverting input terminal and its connection end is the adder's The first inverting input terminal is used to input the first inverting signal of the first four-bit addend signal; the second input terminal of the first two-input NAND/AND gate and the first two The second input end of the input XOR/NOR gate is connected and its connection end is the second input end of the adder, which is used to input the first bit signal of the second four-bit addend signal, and the first bit signal of the described first four-bit addend signal The second inverting input end of a two-input NAND/AND gate is connected with the second inverting input end of the first two-input XOR/NOR gate and its connection end is the second of the adder. The inverting input terminal is used to input the first inverting signal of the second four-bit addend signal; the first input terminal of the second two-input NAND/AND gate and the second two-input exclusive The OR/OR gate is connected to the first input end and its connection end is the third input end of the adder, which is used to input the first four-bit addend signal The second bit signal; the first inverting input of the second two-input NAND/AND gate is connected with the first inverting input of the second two-input XOR/NOR gate and it is connected The end is the third inversion input terminal of the adder, which is used to input the second inversion signal of the first four-bit addend signal; the second input of the second two-input NAND/AND gate The end is connected with the second input end of the second two-input XOR/NOR gate and its connection end is the fourth input end of the adder, which is used to input the second four-bit addend signal Two-bit signal; the second inverting input end of the second two-input NAND/AND gate is connected with the second inverting input end of the second two-input XOR/NOR gate and its connection end is The fourth inverting input terminal of the adder is used to input the second inverting signal of the second four-bit addend signal; the first input terminal of the third two-input NAND/AND gate and The first input end of the third two-input XOR/NOR gate is connected and its connection end is the fifth input end of the adder, which is used to input the third bit of the first four-bit addend signal signal; the first inverting input end of the third two-input NAND/AND gate is connected with the first inverting input end of the third two-input XOR/NOR gate and its connection end is the described The fifth inverting input terminal of the adder is used to input the third inverting signal of the first four-bit addend signal; the second input terminal of the third two-input NAND/AND gate and the The second input end of the third two-input XOR/NOR gate is connected and its connection end is the sixth input end of the adder, which is used to input the third bit signal of the second four-bit addend signal; The second inverting input end of the third two-input NAND/AND gate is connected with the second inverting input end of the third two-input XOR/NOR gate, and its connection end is the addition The sixth inverting input terminal of the device is used to input the third inverting signal of the second four-bit addend signal; the first input terminal of the fourth two-input NAND/AND gate and the first input terminal of the fourth two-input NAND/AND gate The first input end of the four-two input XOR/NOR gate is connected and its connection end is the seventh input end of the adder, which is used to input the fourth bit signal of the first four-bit addend signal; The first inverting input end of the fourth two-input NAND/AND gate is connected with the first inverting input end of the fourth two-input XOR/NOR gate and its connection end is the adder The seventh inverting input terminal is used to input the fourth inverting signal of the first four-bit addend signal; the second input terminal of the fourth and second input NAND/AND gate and the fourth two The second input end of the input XOR/NOR gate is connected and its connection end is the eighth input end of the adder, which is used to input the fourth bit signal of the second four-bit addend signal; The second inverting input end of the four two input NAND/AND gate is connected with the second inverting input end of the fourth two input XOR/NOR gate and its connection end is the eighth of the adder The inversion input terminal is used to input the fourth inversion signal of the second four-bit addend signal; the NAND logic output terminal of the first two-input NAND/AND gate and the first inversion connected to the input of the first inverter, the output of the first inverter and the super- The first carry generation signal input terminal of the advance bit generating circuit is connected, the AND logic output terminal of the first two-input NAND/AND gate is connected with the input terminal of the second inverter, and the second The output end of the inverter is connected to the first inverted carry generation signal input end of the advanced carry generating circuit, and the exclusive OR logic output end of the first two-input XOR/XOR gate is connected to the The input terminal of the third inverter is connected, the output terminal of the third inverter, the first inverted carry transmission signal input terminal of the advanced carry generation circuit and the fifth two input XOR The second inverting input terminal of the NOR gate is connected, the NOR logic output terminal of the first two-input exclusive OR/NOR gate is connected with the input terminal of the fourth inverter, and the first two input NOR gates are connected with the input terminal of the fourth inverter. The output terminals of the four inverters, the first carry transmission signal input terminal of the advanced carry generation circuit and the second input terminal of the fifth two-input XOR/NOR gate are connected, and the second The NAND logic output terminal of the two-input NAND/AND gate is connected to the input terminal of the fifth inverter, and the output terminal of the fifth inverter is connected to the second of the advanced carry generation circuit. The carry generation signal input terminal is connected, the AND logic output terminal of the second two-input NAND/AND gate is connected to the input terminal of the sixth inverter, and the output terminal of the sixth inverter is connected to the input terminal of the sixth inverter. The second inverted carry generation signal input terminal of the advanced carry generating circuit is connected, the exclusive OR logic output terminal of the second two-input exclusive OR/exclusive OR gate and the input of the seventh inverter terminal connection, the output terminal of the seventh inverter, the second inverted carry transmission signal input terminal of the advanced carry generation circuit and the second input terminal of the sixth two-input XOR/NOR gate The inverting input terminal is connected, the NOR logic output terminal of the second two-input XOR/NOR gate is connected to the input terminal of the eighth inverter, and the output terminal of the eighth inverter , the second carry transmission signal input end of the described advanced carry generation circuit is connected to the second input end of the sixth second-input XOR/NOR gate, and the third two-input NAND/AND gate The NAND logic output terminal is connected to the input terminal of the ninth inverter, and the output terminal of the ninth inverter is connected to the third carry generation signal input terminal of the advanced carry generation circuit, The AND logic output terminal of the third and second input NAND/AND gate is connected to the input terminal of the tenth inverter, and the output terminal of the tenth inverter is connected to the advanced carry generation The third inverting carry generation signal input terminal of the circuit is connected, the exclusive OR logic output terminal of the third two-input exclusive OR/exclusive OR gate is connected to the input terminal of the eleventh inverter, and the The output end of the eleventh inverter, the third inverting carry transfer signal input end of the advanced carry generation circuit and the second inverting input end of the seventh second-input XOR/NOR gate are connected , the NOR logic output terminal of the third two-input XOR/NOR gate is connected to the input terminal of the twelfth inverter, the output terminal of the twelfth inverter, the The third carry transmission signal input terminal of the advance carry generation circuit and the seventh second input exclusive OR/exclusive OR gate The second input end of the described fourth two-input NAND/AND gate is connected to the input end of the thirteenth inverter, and the NAND logic output end of the fourth second-input NAND/AND gate is connected to the input end of the thirteenth inverter. The output end is connected with the fourth carry generation signal input end of the advanced carry generation circuit, the AND logic output end of the fourth second-input NAND/AND gate and the input of the fourteenth inverter terminal connection, the output terminal of the fourteenth inverter is connected to the input terminal of the fourth inverted carry generation signal of the advanced carry generation circuit, and the fourth two-input XOR/NOR gate The XOR logic output terminal is connected to the input terminal of the fifteenth inverter, and the output terminal of the fifteenth inverter is input to the fourth inverted carry transmission signal of the advanced carry generation circuit. The end is connected with the second inverting input end of the eighth second-input XOR/NOR gate, and the NOR logic output terminal of the fourth two-input XOR/NOR gate is connected with the sixteenth input XOR/NOR gate. The input end of the inverter is connected, the output end of the sixteenth inverter, the fourth carry transmission signal input end of the advanced carry generation circuit and the eighth second input XOR/XOR The second input terminal of the gate is connected, the first high-order carry signal output terminal of the advanced carry generation circuit is connected with the input terminal of the seventeenth inverter, and the output of the seventeenth inverter The terminal is connected with the first inverting input terminal of the sixth two-input XOR/XOR gate, and the first inverting high-order carry signal output terminal of the advanced carry generating circuit is connected with the eighteenth inverting The input end of the phase device is connected, the output end of the eighteenth inverter is connected with the first input end of the sixth second-input XOR/NOR gate, and the first input end of the advanced carry generation circuit is The output terminal of the two high-order carry signals is connected to the input terminal of the nineteenth inverter, and the output terminal of the nineteenth inverter is connected to the first of the seventh and second input XOR/NOR gates. The inverting input terminal is connected, the second inverting high-order carry signal output terminal of the advanced carry generation circuit is connected to the input terminal of the twentieth inverter, and the output of the twentieth inverter The end is connected with the first input end of the seventh and second input XOR/NOR gate, the third high-order carry signal output end of the advanced carry generation circuit is connected with the twenty-first inverter The input terminal is connected, the output terminal of the twenty-first inverter is connected to the first inverting input terminal of the eighth second input XOR/NOR gate, and the first inverting input terminal of the advanced carry generation circuit is connected. The output terminals of the three inverted high-order carry signals are connected to the input terminals of the twenty-second inverter, and the output terminals of the twenty-second inverter are exclusive OR/simultaneous OR with the eighth second input. The first input end of the gate is connected, the fourth high-order carry signal output end of the described advanced carry generation circuit is the high-order carry signal output end of the adder, and the fourth reverse phase of the described advanced carry generation circuit The high-order carry signal output terminal is the inverted high-order carry signal output terminal of the adder; the same-OR output terminal of the fifth two-input XOR/NOR gate is the first output terminal of the adder, The XOR output of the fifth two-input XOR/XOR gate is the first inversion of the adder Output terminal, the NOR output of the sixth second input XOR/NOR gate is the second output of the adder, the XOR output of the sixth second input XOR/NOR gate end is the second inverting output end of the adder, and the NOR output end of the seventh second input XOR/NOR gate is the third output end of the adder, and the seventh The XOR output of the two-input XOR/NOR gate is the third inverting output of the adder, and the XOR output of the eighth second input XOR/NOR gate is the addition The fourth output terminal of the adder, the exclusive OR output terminal of the eighth second-input XOR/XOR gate is the fourth inverting output terminal of the adder.

The first two-input NAND/AND gate includes a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube MOS tubes, ninth MOS tubes, tenth MOS tubes, eleventh MOS tubes and twelfth MOS tubes; the first MOS tube, the second MOS tube, the third MOS tube and the The fourth MOS transistors are all P-type MOS transistors, the fifth MOS transistors, the sixth MOS transistors, the seventh MOS transistors, the eighth MOS transistors, and the ninth MOS transistors MOS tubes, the tenth MOS tubes, the eleventh MOS tubes and the twelfth MOS tubes are all N-type MOS tubes; the source of the first MOS tube, the first MOS tube The source of the second MOS transistor, the source of the third MOS transistor, the source of the fourth MOS transistor and the gate of the seventh MOS transistor are all connected to the power supply, and the first MOS The grid of the tube, the grid of the fourth MOS tube and the grid of the twelfth MOS tube are connected and its connection terminal is the clock terminal of the first two input NAND/AND gates, so The drain of the first MOS transistor, the drain of the second MOS transistor, the gate of the third MOS transistor, the drain of the fifth MOS transistor, and the sixth MOS transistor The gate is connected and its connection terminal is the NAND logic output terminal of the first two input NAND/AND gates, the gate of the second MOS transistor, the drain of the third MOS transistor, The drain of the fourth MOS transistor, the gate of the fifth MOS transistor and the drain of the sixth MOS transistor are connected, and the connection terminals thereof are the first two input NAND/AND gates The AND logic output terminal, the source of the fifth MOS transistor, the drain of the seventh MOS transistor and the drain of the eighth MOS transistor are connected, and the source of the sixth MOS transistor , the source of the seventh MOS transistor, the drain of the ninth MOS transistor are connected to the drain of the eleventh MOS transistor, the source of the eighth MOS transistor, the The drain of the tenth MOS transistor is connected to the source of the ninth MOS transistor, the gate of the eighth MOS transistor is the first input end of the first two-input NAND/AND gate, the The gate of the ninth MOS transistor is the first inverting input terminal of the first two-input NAND/AND gate, and the gate of the tenth MOS transistor is the first two-input NAND/AND gate the second input end of the eleventh MOS transistor, the gate of the eleventh MOS transistor is the second inverting input end of the first two-input NAND/AND gate, the source electrode of the tenth MOS transistor, the The source of the eleventh MOS transistor is connected to the drain of the twelfth MOS transistor, and the source of the twelfth MOS transistor is grounded; the second input NAND/AND gate, the The third second input NAND/AND gate, the fourth second input NAND/AND gate, the fifth second input NAND/AND gate, the sixth second input NAND/AND gate , the seventh second input NAND/AND gate, the eighth second input NAND/AND gate, the ninth second input NAND/AND gate, said twelfth input NAND/AND gate, said eleventh and second input NAND/AND gate, said twelfth and second input NAND/AND gate, said The structure of the thirteenth two-input NAND/AND gate and the fourteenth two-input NAND/AND gate is the same as that of the first two-input NAND/AND gate. The power consumed by the circuit is independent of the data being processed and does not vary from input to input.

The first and second input XOR/XOR gates include a thirteenth MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor, a sixteenth MOS transistor, a seventeenth MOS transistor, an eighteenth MOS transistor, The 19th MOS tube, the 20th MOS tube, the 21st MOS tube, the 22nd MOS tube, the 23rd MOS tube, the 24th MOS tube, the 25th MOS tube and the 20th MOS tube Six MOS tubes; the thirteenth MOS tube, the fourteenth MOS tube, the fifteenth MOS tube and the sixteenth MOS tube are all P-type MOS tubes, and the first The seventeenth MOS tube, the eighteenth MOS tube, the nineteenth MOS tube, the twenty-first MOS tube, the twenty-first MOS tube, the twenty-second MOS tube tube, the twenty-third MOS tube, the twenty-fourth MOS tube, the twenty-fifth MOS tube and the twenty-sixth MOS tube are all N-type MOS tubes; The source of the thirteenth MOS transistor, the source of the fourteenth MOS transistor, the source of the fifteenth MOS transistor, the source of the sixteenth MOS transistor, and the source of the first MOS transistor The grids of the nineteenth MOS transistors are all connected to the power supply, the grids of the thirteenth MOS transistors, the grids of the sixteenth MOS transistors and the gates of the twenty-sixth MOS transistors are connected and Its connection terminal is the clock terminal of the first and second input XOR/XOR gates, the drain of the thirteenth MOS transistor, the drain of the fourteenth MOS transistor, the tenth MOS transistor The gate of the fifth MOS transistor, the drain of the seventeenth MOS transistor and the gate of the eighteenth MOS transistor are connected, and the connection end is the first two input XOR/NOR gate NOR logic output terminal, the gate of the fourteenth MOS transistor, the drain of the fifteenth MOS transistor, the drain of the sixteenth MOS transistor, the seventeenth MOS transistor The gate of the gate is connected to the drain of the eighteenth MOS transistor, and its connection end is the exclusive OR logic output end of the first two-input XOR/XOR gate, and the seventeenth MOS transistor The source, the drain of the nineteenth MOS transistor, the drain of the twentieth MOS transistor are connected to the drain of the twenty-first MOS transistor, and the eighteenth MOS transistor The source, the source of the nineteenth MOS transistor, the drain of the twenty-second MOS transistor and the drain of the twenty-third MOS transistor are connected, and the twenty-second MOS transistor The gate of the gate is connected to the gate of the twenty-third MOS transistor, and its connection end is the first input end of the first two-input XOR/XOR gate, and the gate of the twenty-third MOS transistor is The source, the source of the twenty-second MOS transistor is connected to the drain of the twenty-fourth MOS transistor, the gate of the twenty-first MOS transistor is connected to the twenty-second MOS transistor The gate of the MOS transistor is connected and its connection terminal is the first inverting input terminal of the first two-input XOR/NOR gate, the source of the twenty-first MOS transistor, the second The source of the thirteenth MOS transistor is connected to the drain of the twenty-fifth MOS transistor, and the gate of the twenty-fourth MOS transistor is the The second input end of the first two-input XOR/XOR gate, the gate of the twenty-fifth MOS transistor is the second inverting input end of the first two-input XOR/XOR gate, The source of the twenty-fourth MOS transistor, the source of the twenty-fifth MOS transistor and the drain of the twenty-sixth MOS transistor are connected, and the twenty-sixth MOS transistor The source is grounded; the second two-input XOR/XOR gate, the third two-input XOR/XOR gate, the fourth two-input XOR/XOR gate, the first Five-two input exclusive OR/same OR gate, said sixth second input exclusive or/same OR gate, said seventh second input exclusive or/same OR gate and said eighth second input exclusive or/same OR gate The structure of the gate is the same as that of the first two-input XOR/XOR gate. The power consumed by the circuit is independent of the data being processed and does not vary from input to input.

The first and second input NOR/OR gates include the twenty-seventh MOS transistor, the twenty-eighth MOS transistor, the twenty-ninth MOS transistor, the thirty-first MOS transistor, the thirty-first MOS transistor, the thirty-second The 33rd MOS tube, the 34th MOS tube, the 35th MOS tube, the 36th MOS tube, the 37th MOS tube and the 38th MOS tube; the twenty The seven MOS tubes, the twenty-eighth MOS tube, the twenty-ninth MOS tube, and the thirty-ninth MOS tube are all P-type MOS tubes, and the thirty-first MOS tube, the The thirty-second MOS transistor, the thirty-third MOS transistor, the thirty-fourth MOS transistor, the thirty-fifth MOS transistor, the thirty-sixth MOS transistor, the thirty-sixth MOS transistor, The thirty-seventh MOS transistor and the thirty-eighth MOS transistor are both N-type MOS transistors; the source of the twenty-seventh MOS transistor and the source of the twenty-eighth MOS transistor , the source of the twenty-ninth MOS transistor, the source of the thirty-third MOS transistor and the gate of the thirty-third MOS transistor are all connected to the power supply, and the twenty-seventh MOS transistor The gate of the MOS transistor, the gate of the thirtieth MOS transistor and the gate of the thirty-eighth MOS transistor are connected and its connection terminal is the clock of the first two input NOR/OR gates terminal, the drain of the twenty-seventh MOS transistor, the drain of the twenty-eighth MOS transistor, the gate of the twenty-ninth MOS transistor, the thirty-first MOS transistor The drain is connected to the gate of the thirty-second MOS transistor and its connection end is the NOR logic output end of the first two-input NOR/OR gate, and the twenty-ninth MOS transistor The drain of the thirtieth MOS transistor, the gate of the twenty-eighth MOS transistor, the gate of the thirty-first MOS transistor, and the thirty-second MOS transistor The drain of the tube is connected and its connection terminal is the OR logic output terminal of the first two input NOR/OR gates, the source of the thirty-first MOS tube, the thirty-sixth MOS tube The drain of the thirty-third MOS transistor and the drain of the thirty-fourth MOS transistor are connected, the source of the thirty-second MOS transistor, the thirty-second MOS transistor The sources of the three MOS transistors are connected to the drain of the thirty-fifth MOS transistor, and the gate of the thirty-fourth MOS transistor is the first input end of the first two-input NOR/OR gate , the gate of the thirty-fifth MOS transistor is the first inverting input terminal of the first two-input NOR/OR gate, and the gate of the thirty-sixth MOS transistor is the first The second input end of the two-input NOR/OR gate, the gate of the thirty-seventh MOS transistor is the second inverting input end of the first two-input NOR/OR gate, and the third The source of the fourteenth MOS transistor, the source of the thirty-fifth MOS transistor and the drain of the thirty-seventh MOS transistor are connected, the source of the thirty-sixth MOS transistor, the The source of the thirty-seventh MOS transistor is connected to the drain of the thirty-eighth MOS transistor, and the source of the thirty-eighth MOS transistor is grounded; the The second two-input NOR/OR gate, the third two-input NOR/OR gate, the fourth two-input NOR/OR gate, the fifth two-input NOR/OR gate and all The structure of the sixth second-input NOR/OR gate is the same as that of the first two-input NOR/OR gate. The power consumed by the circuit is independent of the data being processed and does not vary from input to input.

The first three-input NOR/OR gate includes a thirty-ninth MOS tube, a fortieth MOS tube, a forty-first MOS tube, a forty-second MOS tube, a forty-third MOS tube, a forty Four MOS tubes, forty-fifth MOS tubes, forty-sixth MOS tubes, forty-seventh MOS tubes, forty-eighth MOS tubes, forty-ninth MOS tubes, fiftieth MOS tubes, fifty-first MOS tubes tube and the fifty-second MOS tube; the thirty-ninth MOS tube, the fortieth MOS tube, the forty-first MOS tube and the forty-second MOS tube are P type MOS tube, the forty-third MOS tube, the forty-fourth MOS tube, the forty-fifth MOS tube, the forty-sixth MOS tube, the fortieth The seven MOS tubes, the forty-eighth MOS tube, the forty-ninth MOS tube, the fiftieth MOS tube, the fifty-first MOS tube, and the fifty-second MOS tube The MOS transistors are all N-type MOS transistors; the source of the thirty-ninth MOS transistor, the source of the fortieth MOS transistor, the source of the forty-first MOS transistor, the The source of the forty-second MOS tube and the gate of the forty-fifth MOS tube are connected to the power supply, the grid of the thirty-ninth MOS tube, the gate of the forty-second MOS tube The gate is connected to the gate of the fifty-second MOS transistor and its connection terminal is the clock terminal of the first three-input NOR/OR gate; the drain of the thirty-ninth MOS transistor, The drain of the fortieth MOS transistor, the gate of the forty-first MOS transistor, the drain of the forty-third MOS transistor, and the gate of the forty-fourth MOS transistor connected and its connection end is the NOR logic output end of the first three-input NOR/OR gate, the gate of the fortieth MOS transistor, the drain of the forty-first MOS transistor, The drain of the forty-second MOS transistor, the gate of the forty-third MOS transistor, and the drain of the forty-fourth MOS transistor are connected, and the connecting terminals are the first three Input the OR logic output terminal of the NOR/OR gate, the source of the forty-third MOS transistor, the drain of the forty-fifth MOS transistor, and the drain of the forty-sixth MOS transistor , the drain of the forty-eighth MOS transistor is connected to the drain of the fiftieth MOS transistor, the source of the forty-fourth MOS transistor, the forty-fifth MOS transistor The source is connected to the drain of the forty-seventh MOS transistor, the source of the forty-sixth MOS transistor, the source of the forty-seventh MOS transistor and the forty-ninth The drain of the MOS transistor is connected, the gate of the forty-sixth MOS transistor is the first input terminal of the first three-input NOR/OR gate, and the gate of the forty-seventh MOS transistor is the first input end of the first three-input NOR gate. The first inverting input terminal of the first three-input NOR/OR gate, the gate of the forty-eighth MOS transistor is the second input terminal of the first three-input NOR/OR gate, so The gate of the forty-ninth MOS transistor is the second inverting input terminal of the first three-input NOR/OR gate, and the gate of the fiftieth MOS transistor is The gate is the third input terminal of the first three-input NOR/OR gate, and the gate of the fifty-first MOS transistor is the third inverting input of the first three-input NOR/OR gate terminal, the source of the forty-eighth MOS transistor, the source of the forty-ninth MOS transistor and the drain of the fifty-first MOS transistor are connected, and the fiftieth MOS transistor The source of the fifty-first MOS transistor is connected to the drain of the fifty-second MOS transistor, and the source of the fifty-second MOS transistor is grounded; the second The structure of the three-input NOR/OR gate is the same as that of the first three-input NOR/OR gate. The power consumed by the circuit is independent of the data being processed and does not vary from input to input.

Compared with the prior art, the present invention has the advantages of forming an adder by four two-input NAND/AND gates, eight two-input exclusive-or/nor gates, twenty-two inverters and advanced carry generation circuits , using TSMC 65nm CMOS technology, using the Specter tool to simulate and analyze the circuit, the experimental results show that the adder of the present invention has the correct logic function, compared with the traditional adder circuit, the independent performance of power consumption is improved by 97%, and it can effectively resist the difference Power analysis.

Description of drawings

Fig. 1 is the structural diagram of the defensive differential power consumption analysis adder utilizing sensitive amplification logic of the present invention;

Fig. 2 is the structural diagram of the advanced carry generating circuit of the defensive differential power consumption analysis adder utilizing sensitive amplifying logic of the present invention;

Fig. 3 is the sign diagram of the advanced carry generation circuit of the defensive differential power consumption analysis adder utilizing sensitive amplifying logic of the present invention;

Fig. 4 (a) is the circuit diagram of the first two input NAND/AND gates of the defensive differential power consumption analysis adder utilizing sensitive amplifying logic of the present invention;

Fig. 4 (b) is the symbol of the first two input NAND/AND gates of the defensive differential power consumption analysis adder utilizing sensitive amplifying logic of the present invention;

Fig. 5 (a) is the circuit diagram of the first two input XOR/NOR gates of the defensive differential power analysis adder utilizing sensitive amplifying logic of the present invention;

Fig. 5 (b) is the symbol of the first two input XOR/NOR gates of the defensive differential power analysis adder utilizing sensitive amplifying logic of the present invention;

Fig. 6 (a) is the circuit diagram of the first two input NOR/OR gates of the defensive differential power analysis adder utilizing sensitive amplifying logic of the present invention;

Fig. 6 (b) is the symbol of the first two input NOR/OR gates of the defensive differential power consumption analysis adder utilizing sensitive amplifying logic of the present invention;

Fig. 7 (a) is the circuit diagram of the first three-input NOR/OR gate of the defensive differential power consumption analysis adder utilizing sensitive amplifying logic of the present invention;

Fig. 7 (b) is the symbol of the first three-input NOR/OR gate of the defensive differential power consumption analysis adder utilizing sensitive amplifying logic of the present invention;

Fig. 8 is the analog waveform diagram of the defensive differential power consumption analysis adder utilizing sensitive amplification logic of the present invention;

Fig. 9 is the electric current graph of existing adder;

Fig. 10 is the power consumption curve diagram of existing adder;

Fig. 11 is the current curve diagram of the defensive differential power consumption analysis adder utilizing sensitive amplification logic of the present invention;

FIG. 12 is a power consumption curve diagram of the defensive differential power analysis adder using sensitive amplification logic of the present invention.

Detailed ways

The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

Embodiment 1: As shown in Fig. 1, Fig. 2 and Fig. 3, a defense differential power consumption analysis adder utilizing sensitive amplified logic includes a first two-input NAND/AND gate T1, a second two-input NAND /AND gate T2, the third two-input NAND/AND gate T3, the fourth two-input NAND/AND gate T4, the first two-input exclusive-or/same-or gate R1, the second two-input exclusive-or/same-or gate R2 , the third two-input XOR/NOR gate R3, the fourth two-input XOR/NOR gate R4, the fifth two-input XOR/NOR gate R5, the sixth second-input XOR/NOR gate R6, Seventy-two-input XOR/XOR gate R7, eighth-two-input XOR/XOR gate R8, first inverter N1, second inverter N2, third inverter N3, fourth inverter N4 , fifth inverter N5, sixth inverter N6, seventh inverter N7, eighth inverter N8, ninth inverter N9, tenth inverter N10, eleventh inverter N11 , the twelfth inverter N12, the thirteenth inverter N13, the fourteenth inverter N14, the fifteenth inverter N15, the sixteenth inverter N16, the seventeenth inverter N17, the The eighteenth inverter N18, the nineteenth inverter N19, the twentieth inverter N20, the twenty-first inverter N21, the twenty-second inverter N22 and the advanced carry generating circuit; the advanced carry The generating circuit comprises the fifth and second input NAND/AND gate T5, the sixth and second input NAND/AND gate T6, the seventh and second input NAND/AND gate T7, the eighth and second input NAND/AND gate T8, the ninth and second Input NAND/AND gate T9, twelfth input NAND/AND gate T10, eleventh and second input NAND/AND gate T11, twelfth second input NAND/AND gate T12, thirteenth second input NAND/AND gate T12, thirteenth and second input NAND /AND gate T13, the fourteenth two-input NAND/AND gate T14, the first two-input NOR/OR gate O1, the second two-input NOR/OR gate O2, the third two-input NOR/OR gate O3, The fourth two-input NOR/OR gate O4, the fifth two-input NOR/OR gate O5, the sixth two-input NOR/OR gate O6, the first three-input NOR/OR gate Q1, the second three-input NOR /OR gate Q2, twenty-third inverter N23, twenty-fourth inverter N24, twenty-fifth inverter N25, twenty-sixth inverter N26, twenty-seventh inverter N27, Twenty-eighth inverter N28, twenty-ninth inverter N29, thirtieth inverter N30, thirty-first inverter N31, thirty-second inverter N32, thirty-third inverter N33, thirty-fourth inverter N34, thirty-fifth inverter N35, thirty-sixth inverter N36, thirty-seventh inverter N37, thirty-eighth inverter N38, third Nineteenth inverter N39, fortieth inverter N40, forty-first inverter N41, forty-second inverter N42, forty-third inverter N43, forty-fourth inverter N44 , the forty-fifth inverter N45, the forty-sixth inverter N46, the forty-seventh inverter N47, the forty-eighth inverter N48, the forty-ninth inverter N49 and the fiftieth inverter Phase device N50; the first two-input NAND/AND gate T1, the second two-input NAND/AND gate T2, the third and second input NAND/AND gate T3, the fourth and second input NAND/AND gate T4, the fifth and second input NAND/AND gate T5, the sixth and second input NAND/AND gate T6, the seventh and second input NAND/AND gate T7, eighth and second input NAND/AND gate T8, ninth and second input NAND/AND gate T9, twelfth input NAND/AND gate T10, eleventh and second input NAND/AND gate T11, the twelfth second-input NAND/AND gate T12, the thirteenth second-input NAND/AND gate T13 and the fourteenth second-input NAND/AND gate T14 respectively have a first input terminal and a first inverting input terminal , the second input terminal, the second inverting input terminal, the clock terminal, the NAND logic output terminal and the AND logic output terminal; the first two-input exclusive-or/same-or gate R1, the second two-input exclusive-or/same-or gate R2 , the third two-input XOR/NOR gate R3, the fourth two-input XOR/NOR gate R4, the fifth two-input XOR/NOR gate R5, the sixth second-input XOR/NOR gate R6, The seventy-two-input XOR/NOR gate R7 and the eighth-two-input XOR/NOR gate R8 respectively have a first input terminal, a first inverting input terminal, a second input terminal, a second inverting input terminal, and a clock terminal , NOR logic output and XOR logic output; the first two-input NOR/OR gate O1, the second two-input NOR/OR gate O2, the third two-input NOR/OR gate O3, the fourth two-input The NOR/OR gate O4, the fifth two-input NOR/OR gate O5 and the sixth two-input NOR/OR gate O6 respectively have a first input terminal, a first inversion input terminal, a second input terminal, a second inversion Phase input terminal, clock terminal, NOR logic output terminal and OR logic output terminal; the first three-input NOR/OR gate Q1 and the second three-input NOR/OR gate Q2 have a first input terminal, a first inverting input terminal, the second input terminal, the second inverting input terminal, the third input terminal, the third inverting input terminal, the clock terminal, or the logic output terminal and the logic output terminal; the fifth two input NAND/AND gate T5 The clock terminal of the sixth and second input NAND/AND gate T6, the clock terminal of the seventh and second input NAND/AND gate T7, the clock terminal of the eighth second input NAND/AND gate T8, the ninth and second input The clock terminal of the NAND/AND gate T9, the clock terminal of the twelfth input NAND/AND gate T10, the clock terminal of the eleventh and second input NAND/AND gate T11, the twelfth and second input NAND/AND gate T12 The clock terminal of the 13th and 2nd input NAND/AND gate T13, the clock terminal of the 14th 2nd input NAND/AND gate T14, the clock terminal of the first 2nd input NOR/OR gate O1, the second The clock terminal of the two-input NOR/OR gate O2, the clock terminal of the third two-input NOR/OR gate O3, the clock terminal of the fourth two-input NOR/OR gate O4, the fifth two-input NOR/OR gate O5 The clock end of the clock end, the clock end of the sixth two-input NOR/OR gate O6, the clock end of the first three-input NOR/OR gate Q1 and the clock end of the second three-input NOR/OR gate Q2 are connected and its connection end It is the clock end of the advanced forward generation circuit; the first input end of the fifth and second input NAND/AND gate T5, the first input end of the eleventh and second input NAND/AND gate T11, the thirteenth second input NAND / The first input terminal of the AND gate T13 and the fourteenth second input AND The first input end of the NOT/AND gate T14 is connected and its connection end is the fourth carry transmission signal input end of the advanced carry generation circuit, which is used to input the fourth carry transmission signal P3; the fifth two input NAND/AND gate T5 The first inverting input end of the eleventh second input NAND/AND gate T11, the first inverting input end of the thirteenth second input NAND/AND gate T13 and the fourteenth second input NAND/AND gate T13 The first inverting input end of the input NAND/AND gate T14 is connected and its connection end is the fourth inverting carry transmission signal input end of the advanced carry generation circuit, for inputting the fourth inverting carry transmission signal The second input end of the fifth two-input NAND/AND gate T5 is connected to the second input end of the fourth two-input NOR/OR gate O4, and its connection end is the third carry generation signal input end of the advanced carry generation circuit , for inputting the third carry generation signal G2; the second inverting input terminal of the fifth two-input NAND/AND gate T5 is connected with the second inverting input terminal of the fourth two-input NOR/OR gate O4 and connected The end is the third inverted carry generation signal input end of the advanced carry generation circuit, which is used to input the third inverted carry generation signal The first input end of the sixth second input NAND/AND gate T6, the first input end of the ninth second input NAND/AND gate T9 and the first input end of the twelfth second input NAND/AND gate T12 are connected and Its connection terminal is the third carry transmission signal input terminal of the advanced carry generation circuit, which is used to input the third carry transmission signal P2; The first inverting input end of NAND/AND gate T9 is connected with the first inverting input end of twelfth input NAND/AND gate T12 and its connection end is the third inverting carry transmission of advanced carry generation circuit The signal input terminal is used to input the third inverted carry transmission signal The second input end of the sixth two-input NAND/AND gate T6 is connected to the third input end of the first three-input NOR/OR gate Q1, and its connection end is the second carry generation signal input end of the advanced carry generation circuit , for inputting the second carry generation signal G1; the second inverting input terminal of the sixth two-input NAND/AND gate T6 is connected with the third inverting input terminal of the first three-input NOR/OR gate Q1 and connected The end is the second inverted carry generation signal input end of the advanced carry generation circuit, which is used to input the second inverted carry generation signal The first input end of the seventh and second input NAND/AND gate T7 is connected to the first input end of the twelfth input NAND/AND gate T10, and its connection end is the second carry transmission signal input end of the advanced carry generation circuit , for inputting the second carry transmission signal P1; the first inverting input terminal of the seventh and second input NAND/AND gate T7 is connected with the first inverting input terminal of the twelfth input NAND/AND gate T10 and connected The terminal is the second inverting carry transmission signal input terminal of the look-ahead carry generation circuit for inputting the second inverting carry transmission signal The second input end of the seventh two-input NAND/AND gate T7 is connected to the second input end of the fifth two-input NOR/OR gate O5, and its connection end is the first carry generation signal input end of the advanced carry generation circuit , for inputting the first carry generation signal G0; the second inverting input terminal of the seventh two-input NAND/AND gate T7 is connected with the second inverting input terminal of the fifth two-input NOR/OR gate O5 and connected The end is the first inverted carry generation signal input end of the advanced carry generation circuit, which is used to input the first inverted carry generation signal The first input end of the eighth second input NAND/AND gate T8 is the first carry transmission signal input end of the advanced carry generation circuit, which is used to input the first carry transmission signal P0; the eighth second input NAND/AND gate T8 The first inverting input terminal of the first inverting carry generation circuit is the first inverting carry transmission signal input terminal for inputting the first inverting carry transmission signal The second input end of the eighth second input NAND/AND gate T8 is the low-order carry signal input end of the advanced carry generation circuit, which is used to input the low-order carry signal C _-1 ; the eighth second input NAND/AND gate T8 The first The two inverting input terminals are the inverting low-order carry signal input terminals of the advanced carry generation circuit, which are used to input the inverting low-order carry signal The NAND logic output terminal of the fifth two-input NAND/AND gate T5 is connected to the input terminal of the twenty-third inverter N23, and the NAND logic output terminal of the fifth two-input NAND/AND gate T5 is connected to the twenty-fourth inverter N23. The input end of the inverter N24 is connected, the NAND logic output end of the sixth second input NAND/AND gate T6 is connected with the input end of the twenty-fifth inverter N25, the sixth second input NAND/AND gate T6 It is connected with the logic output terminal and the input terminal of the twenty-sixth inverter N26, and the NAND logic output terminal of the seventh and second input NAND/AND gate T7 is connected with the input terminal of the twenty-seventh inverter N27, and the seventh The AND logic output of the two-input NAND/AND gate T7 is connected to the input of the twenty-eighth inverter N28, and the NAND logic output of the eighth and second input NAND/AND gate T8 is connected to the twenty-ninth inversion The input end of the device N29 is connected, the NAND logic output end of the eighth second input NAND/AND gate T8 is connected with the input end of the thirtieth inverter N30, the NAND logic output of the ninth second input NAND/AND gate T9 end is connected with the input end of the thirty-first inverter N31, the AND logic output end of the ninety-second input NAND/AND gate T9 is connected with the input end of the thirty-second inverter N32, and the twelfth input NAND The NAND logic output of the AND gate T10 is connected to the input of the thirty-third inverter N33, and the twelfth input NAND/AND logic output of the AND gate T10 is connected to the input of the thirty-fourth inverter N34. The NAND logic output terminal of the 112th input NAND/AND gate T11 is connected to the input terminal of the thirty-fifth inverter N35, and the AND logic output terminal of the 112th input NAND/AND gate T11 It is connected with the input end of the thirty-sixth inverter N36, the NAND logic output end of the twelfth second input NAND/AND gate T12 is connected with the input end of the thirty-seventh inverter N37, and the twelfth second input The AND logic output of the NAND/AND gate T12 is connected to the input of the thirty-eighth inverter N38, the NAND logic output of the thirteenth second input NAND/AND gate T13 is connected to the thirty-ninth inverter The input end of N39 is connected, the AND logic output end of the thirteenth second input NAND/AND gate T13 is connected with the input end of the fortieth inverter N40, the NAND logic of the fourteenth second input NAND/AND gate T14 The output terminal is connected to the input terminal of the forty-first inverter N41, the AND logic output terminal of the 14th and second input NAND/AND gate T14 is connected to the input terminal of the forty-second inverter N42, and the first and second input terminals The NOR logic output end of the NOR/OR gate O1 is connected to the input end of the forty-third inverter N43, and the OR logic output end of the first two-input NOR/OR gate O1 is connected to the forty-fourth inverter N44 The input terminal of the second two-input NOR/OR gate O2 is connected with the input terminal of the forty-fifth inverter N45, and the NOR logic output terminal of the second two-input NOR/OR gate O2 It is connected with the input end of the forty-sixth inverter N46, the NOR logic output end of the third two-input NOR/OR gate O3 is connected with the input end of the forty-seventh inverter N47, the third two-input NOR The OR logic output of the OR gate O3 is connected to the input of the forty-eighth inverter N48, and the fourth and second inputs are NOR/OR The NOR logic output terminal of the gate O4 is connected to the input terminal of the forty-ninth inverter N49, and the OR logic output terminal of the fourth and second input NOR/OR gate O4 is connected to the input terminal of the fiftieth inverter N50, The output end of the twenty-third inverter N23 is connected to the first input end of the second two-input NOR/OR gate O2, and the output end of the twenty-fourth inverter N24 is connected to the second two-input NOR/OR gate The first inverting input terminal of O2 is connected, the output terminal of the twenty-fifth inverter N25, the second input terminal of the eleventh two-input NAND/AND gate T11 and the fourth two-input NOR/OR gate O4 The first input terminal is connected, the output terminal of the twenty-sixth inverter N26, the second inverting input terminal of the eleventh two-input NAND/AND gate T11 and the first one of the fourth two-input NOR/OR gate O4 The inverting input terminal is connected, the output terminal of the twenty-seventh inverter N27, the second input terminal of the ninety-second input NAND/AND gate T9 and the second input terminal of the first three-input NOR/OR gate Q1 are connected , the output terminal of the twenty-eighth inverter N28, the second inverting input terminal of the ninth and second input NAND/AND gate T9 and the second inverting input terminal of the first three-input NOR/OR gate Q1 are connected, The output end of the twenty-ninth inverter N29, the second input end of the twelfth input NAND/AND gate T10 and the first input end of the fifth and second input NOR/OR gate O5 are connected, and the thirtieth reverse phase The output terminal of device N30, the second inverting input terminal of the twelfth input NAND/AND gate T10 and the first inverting input terminal of the fifth two-input NOR/OR gate O5 are connected, and the thirty-first inverter The output end of N31, the second input end of the thirteenth second-input NAND/AND gate T13 and the second input end of the third two-input NOR/OR gate O3 are connected, the output end of the thirty-second inverter N32 1. The second inverting input end of the thirteenth second-input NAND/AND gate T13 is connected with the second inverting input end of the third two-input NOR/OR gate O3, and the output end of the thirty-third inverter N33 , the second input end of the twelfth second-input NAND/AND gate T12 is connected to the first input end of the first three-input NOR/OR gate Q1, the output end of the thirty-fourth inverter N34, the twelfth The second inverting input end of the two-input NAND/AND gate T12 is connected with the first inverting input end of the first three-input NOR/OR gate Q1, and the output end of the thirty-fifth inverter N35 is connected with the first two The second input end of the input NOR/OR gate O1 is connected, the output end of the thirty-sixth inverter N36 is connected with the second inverting input end of the first two-input NOR/OR gate O1, and the thirty-seventh inversion The output terminal of the phase device N37, the second input terminal of the fourteenth two-input NAND/AND gate T14 and the first input terminal of the third two-input NOR/OR gate O3 are connected, and the thirty-eighth inverter N38 The output terminal, the second inverting input terminal of the 14th and 2nd input NAND/AND gate T14 are connected with the first inverting input terminal of the 3rd 2nd input NOR/OR gate O3, the 39th inverter N39 The output end is connected with the first input end of the first two-input NOR/OR gate O1, the output end of the fortieth inverter N40 is connected with the first inverting input end of the first two-input NOR/OR gate O1, The output of the forty-first inverter N41 end is connected with the first input end of the second three-input NOR/OR gate Q2, the output end of the forty-second inverter N42 is connected with the first inverting input end of the second three-input NOR/OR gate Q2, The output end of the forty-third inverter N43 is connected to the second input end of the second three-input NOR/OR gate Q2, and the output end of the forty-fourth inverter N44 is connected to the second three-input NOR/OR gate The second inverting input terminal of Q2 is connected, the output terminal of the forty-fifth inverter N45 is connected with the third input terminal of the second three-input NOR/OR gate Q2, and the output terminal of the forty-sixth inverter N46 It is connected with the third inverting input terminal of the second three-input NOR/OR gate Q2, the output terminal of the forty-seventh inverter N47 is connected with the first input terminal of the sixth and second input NOR/OR gate O6, and The output end of the forty-eight inverter N48 is connected with the first inverting input end of the sixth and second input NOR/OR gate O6, the output end of the forty-ninth inverter N49 is connected with the sixth and second input NOR/OR The second input end of the gate O6 is connected, the output end of the fiftieth inverter N50 is connected with the second inverting input end of the sixth two-input NOR/OR gate O6, the fifth two-input NOR/OR gate O5 The NOR logic output terminal is the first high-order carry signal output terminal of the advanced carry generation circuit, which is used to output the first high-order carry signal C0, and the OR logic output terminal of the fifth two-input NOR/OR gate O5 is an advanced carry generation. The first inverted high-order carry signal output terminal of the circuit is used to output the first inverted high-order carry signal The NOR logic output terminal of the first three-input NOR/OR gate Q1 is the second high-order carry signal output terminal of the advanced carry generation circuit, which is used to output the second high-order carry signal C1; the first three-input NOR/OR gate The OR logic output terminal of Q1 is the second inverting high-order carry signal output terminal of the advanced carry generation circuit, which is used to output the second inverting high-order carry signal The NOR logic output end of the sixth second input NOR/OR gate O6 is the third high-order carry signal output end of the advanced carry generation circuit, which is used to output the third high-order carry signal C2, and the sixth second input NOR/OR gate The OR logic output terminal of O6 is the third inverting high-order carry signal output terminal of the advanced carry generation circuit, which is used to output the third inverting high-order carry signal The NOR logic output end of the second three-input NOR/OR gate Q2 is the fourth high-order carry signal output end of the advanced carry generation circuit, which is used to output the fourth high-order carry signal C3; the second three-input NOR/OR gate The OR logic output terminal of Q2 is the fourth inverting high-order carry signal output terminal of the advanced carry generation circuit, which is used to output the fourth inverting high-order carry signal The second input end of the second two-input NOR/OR gate O2 is the fourth carry generation signal input end of the advanced carry generation circuit, which is used to input the fourth carry generation signal G3; the second two-input NOR/OR gate O2 The second inverting input terminal of the advanced carry generating circuit is the fourth inverting carry generating signal input end for inputting the fourth inverting carrying generating signal The clock end of the first two-input NAND/AND gate T1, the clock end of the second two-input NAND/AND gate T2, the clock end of the third two-input NAND/AND gate T3, the fourth two-input NAND/AND gate The clock terminal of the gate T4, the clock terminal of the first two-input XOR/XOR gate R1, the clock end of the second two-input XOR/XOR gate R2, the clock end of the third two-input XOR/XOR gate R3 , the clock end of the fourth and second input XOR/NOR gate R4, the clock end of the fifth and second input XOR/NOR gate R5, the clock end of the sixth and second input XOR/NOR gate R6, the seventh and second input The clock end of the XOR/NOR gate R7, the clock end of the eighth second input XOR/NOR gate R8 are connected to the clock end of the advanced carry generation circuit, the low-order carry signal input end of the advanced carry generation circuit is connected to the fifth The second inverting input end of the two-input XOR/NOR gate R5 is connected and its connection end is the low-order carry signal input end of the adder; The second input end of the OR/OR gate R5 is connected and its connection end is the inverting low-order carry signal input end of the adder; the first input end of the first two-input NAND/AND gate T1 and the first two-input exclusive-or /The first input end of OR gate R1 is connected and its connection end is the first input end of adder, is used for inputting the first bit signal of the first four-bit addend signal; The first two input NAND/AND gate The first inverting input end of T1 is connected with the first inverting input end of the first two-input XOR/NOR gate R1 and its connection end is the first inverting input end of the adder, which is used to input the first four The first bit inverting signal of bit addend signal; The second input end of the first two input NAND/AND gate T1 is connected with the second input end of the first two input XOR/NOR gate R1 and its connection end is The second input terminal of the adder is used to input the first bit signal of the second four-bit addend signal, the second inverting input terminal of the first two-input NAND/AND gate T1 and the first two-input XOR/ Connect with the second inverting input terminal of the OR gate R1 and its connection end is the second inverting input terminal of the adder, for inputting the first inverting signal of the second four-bit addend signal; the second two input The first input end of the NAND/AND gate T2 is connected to the first input end of the second two-input XOR/NOR gate R2 and its connection end is the third input end of the adder for inputting the first four bits The second bit signal of the addend signal; the first inverting input end of the second two-input NAND/AND gate T2 is connected with the first inverting input end of the second two-input XOR/NOR gate R2 and its connection end It is the third inverting input terminal of the adder, which is used to input the second inverting signal of the first four-bit addend signal; the second input terminal of the second two-input NAND/AND gate T2 and the second two-input The second input end of the XOR/NOR gate R2 is connected and its connection end is the fourth input end of the adder, which is used to input the second bit signal of the second four-bit addend signal; the second two input NAND/NO The second inverting input end of AND gate T2 is connected with the second inverting input end of the second two-input XOR/NOR gate R2 and its connection end is the fourth inverting input end of the adder, for inputting the second The second inversion signal of the four-bit addend signal; the third and second input NAND The first input end of the AND gate T3 is connected to the first input end of the third two-input XOR/NOR gate R3 and its connection end is the fifth input end of the adder for inputting the first four-bit addend The third bit signal of the signal; the first inverting input terminal of the third two-input NAND/AND gate T3 is connected with the first inverting input terminal of the third two-input XOR/NOR gate R3 and its connection end is addition The fifth inverting input terminal of the device is used to input the third inverting signal of the first four-bit addend signal; the second input terminal of the third two-input NAND/AND gate T3 and the third two-input XOR / is connected with the second input end of the OR gate R3 and its connection end is the sixth input end of the adder, for inputting the third bit signal of the second four-bit addend signal; the third two input NAND/AND gate The second inverting input terminal of T3 is connected with the second inverting input terminal of the third two-input XOR/NOR gate R3 and its connection end is the sixth inverting input terminal of the adder, which is used to input the second four The third bit inversion signal of bit addend signal; The first input end of the 4th two input NAND/AND gate T4 is connected with the first input end of the fourth two input XOR/NOR gate R4 and its connection end is The seventh input terminal of the adder is used to input the fourth bit signal of the first four-bit addend signal; the first inverting input terminal of the fourth two-input NAND/AND gate T4 and the fourth two-input XOR/ Connect with the first inverting input terminal of the OR gate R4 and its connection end is the seventh inverting input terminal of the adder, which is used to input the fourth inverting signal of the first four-bit addend signal; the fourth and second input The second input end of the NAND/AND gate T4 is connected with the second input end of the fourth two-input XOR/NOR gate R4 and its connection end is the eighth input end of the adder, which is used to input the second four bits The fourth bit signal of the addend signal; the second inverting input end of the fourth two-input NAND/AND gate T4 is connected with the second inverting input end of the fourth two-input XOR/NOR gate R4 and its connection end It is the eighth inversion input terminal of the adder, which is used to input the fourth inversion signal of the second four-bit addend signal; the NAND logic output terminal of the first two input NAND/AND gate T1 and the first inversion The input end of the phase device N1 is connected, the output end of the first inverter N1 is connected with the first carry generation signal input end of the advanced carry generation circuit, and the AND logic output end of the first two input NAND/AND gate T1 is connected with the first carry generation signal input end of the advanced carry generation circuit. The input terminals of the two inverters N2 are connected, the output terminals of the second inverter N2 are connected with the first inverting carry generation signal input end of the advanced carry generation circuit, and the first two input exclusive OR/exclusive OR gate R1 The OR logic output terminal is connected to the input terminal of the third inverter N3, the output terminal of the third inverter N3, the first inverted carry transmission signal input terminal of the advanced carry generation circuit and the fifth and second input XOR/same The second inverting input terminal of the OR gate R5 is connected, the NOR logic output terminal of the first two-input XOR/NOR gate R1 is connected to the input terminal of the fourth inverter N4, and the output terminal of the fourth inverter N4 , the first carry transmission signal input end of the advanced carry generation circuit is connected to the second input end of the fifth two-input XOR/NOR gate R5, and the NAND logic output end of the second two-input NAND/AND gate T2 and The input terminal of the fifth inverter N5 is connected, the fifth inverter The output end of N5 is connected with the second carry generation signal input end of the advanced carry generation circuit, the AND logic output end of the second two-input NAND/AND gate T2 is connected with the input end of the sixth inverter N6, and the sixth inverter The output terminal of the phase device N6 is connected with the second inverted carry generation signal input terminal of the advanced carry generation circuit, and the exclusive OR logic output terminal of the second two-input XOR/NOR gate R2 is connected with the input of the seventh inverter N7 terminal connection, the output terminal of the seventh inverter N7, the second inverting carry transmission signal input terminal of the advanced carry generating circuit and the second inverting input terminal of the sixth two-input XOR/NOR gate R6 are connected, the first The NOR logic output terminal of the two-two input XOR/NOR gate R2 is connected to the input terminal of the eighth inverter N8, the output terminal of the eighth inverter N8, and the second carry transmission signal input of the advanced carry generation circuit Terminal is connected with the second input end of the sixth two-input XOR/NOR gate R6, the NAND logic output end of the third two-input NAND/AND gate T3 is connected with the input end of the ninth inverter N9, the ninth The output end of the inverter N9 is connected to the third carry generation signal input end of the advanced carry generation circuit, and the AND logic output end of the third two-input NAND/AND gate T3 is connected to the input end of the tenth inverter N10, The output end of the tenth inverter N10 is connected to the third inverting carry generating signal input end of the advanced carry generating circuit, and the exclusive OR logic output end of the third two-input XOR/NOR gate R3 is connected to the eleventh inversion The input terminal of the device N11 is connected, the output terminal of the eleventh inverter N11, the third inverting carry transmission signal input terminal of the advanced carry generation circuit and the second inverting phase of the seventh and second input XOR/NOR gate R7 The input terminal is connected, the NOR logic output terminal of the third two-input XOR/NOR gate R3 is connected to the input terminal of the twelfth inverter N12, the output terminal of the twelfth inverter N12, and the advanced carry generation circuit The third carry transmission signal input terminal of the second input is connected with the second input terminal of the seventh two-input XOR/NOR gate R7, and the NAND logic output terminal of the fourth two-input NAND/AND gate T4 is connected with the thirteenth inverter The input end of N13 is connected, the output end of the thirteenth inverter N13 is connected with the fourth carry generation signal input end of the advanced carry generation circuit, the AND logic output end of the fourth two-input NAND/AND gate T4 is connected with the tenth The input terminals of the four inverters N14 are connected, the output terminals of the fourteenth inverter N14 are connected to the input terminals of the fourth inverted carry generation signal of the advanced carry generation circuit, and the fourth two-input XOR/NOR gate R4 The exclusive OR logic output terminal is connected to the input terminal of the fifteenth inverter N15, the output terminal of the fifteenth inverter N15, the fourth inverted carry transmission signal input terminal of the advanced carry generation circuit and the eighth second input exclusive The second inverting input terminal of the OR/OR gate R8 is connected, the OR logic output terminal of the fourth two-input exclusive OR/OR gate R4 is connected to the input terminal of the sixteenth inverter N16, and the sixteenth inverting The output end of the device N16, the fourth carry transmission signal input end of the advanced carry generation circuit and the second input end of the eighth second input XOR/NOR gate R8 are connected, and the first high-order carry signal output of the advanced carry generation circuit terminal and the input of the seventeenth inverter N17 terminal connection, the output terminal of the seventeenth inverter N17 is connected to the first inverting input terminal of the sixty-two input XOR/NOR gate R6, and the first inverting high-order carry signal output terminal of the advanced carry generation circuit and The input end of the eighteenth inverter N18 is connected, the output end of the eighteenth inverter N18 is connected to the first input end of the sixth and second input XOR/NOR gate R6, and the second high bit of the advanced carry generation circuit The carry signal output terminal is connected to the input terminal of the nineteenth inverter N19, and the output terminal of the nineteenth inverter N19 is connected to the first inverting input terminal of the seventh and second input XOR/NOR gate R7, advancing The second inverting high-order carry signal output terminal of the bit generation circuit is connected to the input terminal of the twentieth inverter N20, and the output terminal of the twentieth inverter N20 is connected to the seventh and second input exclusive OR/nor gate R7. One input terminal is connected, the third high-order carry signal output terminal of the advanced carry generation circuit is connected to the input terminal of the twenty-first inverter N21, and the output terminal of the twenty-first inverter N21 is XORed with the eighth and second input / is connected with the first inverting input terminal of the OR gate R8, the third inverting high-order carry signal output terminal of the advanced carry generation circuit is connected with the input terminal of the twenty-second inverter N22, and the twenty-second inverter The output end of N22 is connected with the first input end of the eighth and second input XOR/NOR gate R8, and the fourth high-order carry signal output end of the advanced carry generating circuit is the high-order carry signal output end of the adder, and the advanced carry generation generates The fourth inverting high-order carry signal output end of the circuit is the inverting high-order carry signal output end of the adder; the same-OR output end of the fifth and second input XOR/NOR gate R5 is the first output end of the adder, and the fifth The exclusive OR output end of the two-input XOR/NOR gate R5 is the first inverting output end of the adder, and the NOR output end of the sixth two-input XOR/NOR gate R6 is the second output end of the adder, The XOR output of the sixth and second input XOR/NOR gate R6 is the second inverting output of the adder, and the XOR output of the seventh and second input XOR/NOR gate R7 is the third output of the adder The XOR output end of the seventh and second input XOR/NOR gate R7 is the third inverting output end of the adder, and the XOR output end of the eighth second input XOR/NOR gate R8 is the first NOR output end of the adder Four output terminals, the exclusive OR output terminal of the eighth two-input XOR/XOR gate R8 is the fourth inverting output terminal of the adder.

Embodiment two: this embodiment is basically the same as embodiment one, the difference is that in this embodiment, as shown in Figure 4 (a) and Figure 4 (b), the first two input NAND/AND gate T1 includes the first MOS tube M1, second MOS tube M2, third MOS tube M3, fourth MOS tube M4, fifth MOS tube M5, sixth MOS tube M6, seventh MOS tube M7, eighth MOS tube M8, ninth MOS tube M9, the tenth MOS tube M10, the eleventh MOS tube M11 and the twelfth MOS tube M12; the first MOS tube M1, the second MOS tube M2, the third MOS tube M3 and the fourth MOS tube M4 are all P-type MOS tubes tube, the fifth MOS tube M5, the sixth MOS tube M6, the seventh MOS tube M7, the eighth MOS tube M8, the ninth MOS tube M9, the tenth MOS tube M10, the eleventh MOS tube M11 and the twelfth MOS tube M12 are all N-type MOS transistors; the source of the first MOS transistor M1, the source of the second MOS transistor M2, the source of the third MOS transistor M3, the source of the fourth MOS transistor M4 and the source of the seventh MOS transistor M7 The gates are all connected to the power supply, the gate of the first MOS transistor M1, the gate of the fourth MOS transistor M4 and the gate of the twelfth MOS transistor M12 are connected, and the connection terminal is the first and second input NAND/AND gate T1 The clock terminal of the first MOS transistor M1, the drain of the second MOS transistor M2, the gate of the third MOS transistor M3, the drain of the fifth MOS transistor M5 and the gate of the sixth MOS transistor M6 are connected and Its connection terminal is the NAND logic output terminal of the first two-input NAND/AND gate T1, the gate of the second MOS transistor M2, the drain of the third MOS transistor M3, the drain of the fourth MOS transistor M4, the fifth The gate of the MOS transistor M5 is connected to the drain of the sixth MOS transistor M6 and its connection end is the AND logic output end of the first two-input NAND/AND gate T1, the source of the fifth MOS transistor M5, the seventh MOS transistor The drain of M7 is connected to the drain of the eighth MOS transistor M8, the source of the sixth MOS transistor M6, the source of the seventh MOS transistor M7, the drain of the ninth MOS transistor M9 and the drain of the eleventh MOS transistor M11 The source of the eighth MOS transistor M8, the drain of the tenth MOS transistor M10, and the source of the ninth MOS transistor M9 are connected, and the gate of the eighth MOS transistor M8 is connected to the first two-input NAND/AND gate T1. The first input terminal, the gate of the ninth MOS transistor M9 is the first inverting input terminal of the first two-input NAND/AND gate T1, the gate of the tenth MOS transistor M10 is the first two-input NAND/AND gate T1 The second input terminal, the gate of the eleventh MOS transistor M11 is the second inverting input terminal of the first two-input NAND/AND gate T1, the source of the tenth MOS transistor M10, and the source of the eleventh MOS transistor M11 It is connected to the drain of the twelfth MOS transistor M12, and the source of the twelfth MOS transistor M12 is grounded; the second and second input NAND/AND gate T2, the third and second input NAND/AND gate T3, the fourth and second input AND NOT/AND gate T4, fifth second input NAND/AND gate T5, sixth second input NAND/AND gate T6, seventh second input NAND/AND gate T7, The eighth and second input NAND/AND gate T8, the ninth and second input NAND/AND gate T9, the twelfth input NAND/AND gate T10, the eleventh and second input NAND/AND gate T11, the twelfth and second input The structure of the NAND/AND gate T12, the thirteenth two-input NAND/AND gate T13 and the fourteenth two-input NAND/AND gate T14 is the same as that of the first two-input NAND/AND gate T1.

As shown in Figure 5(a) and Figure 5(b), in this embodiment, the first two-input XOR/XOR gate R1 includes a thirteenth MOS transistor M13, a fourteenth MOS transistor M14, a fifteenth MOS transistor Tube M15, sixteenth MOS tube M16, seventeenth MOS tube M17, eighteenth MOS tube M18, nineteenth MOS tube M19, twenty-first MOS tube M20, twenty-first MOS tube M21, twenty-second MOS tube M22, twenty-third MOS tube M23, twenty-fourth MOS tube M24, twenty-fifth MOS tube M25, and twenty-sixth MOS tube M26; thirteenth MOS tube M13, fourteenth MOS tube M14, The fifteenth MOS tube M15 and the sixteenth MOS tube M16 are P-type MOS tubes, the seventeenth MOS tube M17, the eighteenth MOS tube M18, the nineteenth MOS tube M19, the twentieth MOS tube M20, the second The eleventh MOS tube M21, the twenty-second MOS tube M22, the twenty-third MOS tube M23, the twenty-fourth MOS tube M24, the twenty-fifth MOS tube M25 and the twenty-sixth MOS tube M26 are all N-type MOS tubes tube; the source of the thirteenth MOS transistor M13, the source of the fourteenth MOS transistor M14, the source of the fifteenth MOS transistor M15, the source of the sixteenth MOS transistor M16 and the gate of the nineteenth MOS transistor M19 The poles are connected to the power supply, the gate of the thirteenth MOS transistor M13, the gate of the sixteenth MOS transistor M16 and the gate of the twenty-sixth MOS transistor M26 are connected, and the connection terminals are the first and second input XOR/Same The clock terminal of the OR gate R1, the drain of the thirteenth MOS transistor M13, the drain of the fourteenth MOS transistor M14, the gate of the fifteenth MOS transistor M15, the drain of the seventeenth MOS transistor M17 and the eighteenth MOS transistor M17 The gate of the MOS transistor M18 is connected and its connection terminal is the NOR logic output terminal of the first two-input XOR/NOR gate R1, the gate of the fourteenth MOS transistor M14, the drain of the fifteenth MOS transistor M15, The drain of the sixteenth MOS transistor M16, the gate of the seventeenth MOS transistor M17, and the drain of the eighteenth MOS transistor M18 are connected, and the connection end is the exclusive OR logic of the first two-input exclusive OR/exclusive OR gate R1 The output terminal is connected to the source of the seventeenth MOS transistor M17, the drain of the nineteenth MOS transistor M19, the drain of the twentieth MOS transistor M20, and the drain of the twenty-first MOS transistor M21, and the eighteenth MOS transistor The source of M18, the source of the nineteenth MOS transistor M19, the drain of the twenty-second MOS transistor M22 and the drain of the twenty-third MOS transistor M23 are connected, and the gate of the twentieth MOS transistor M20 is connected to the second The gate of the thirteenth MOS transistor M23 is connected and its connection end is the first input end of the first two-input XOR/NOR gate R1, the source of the twentieth MOS transistor M20, and the source of the twenty-second MOS transistor M22 pole is connected to the drain of the twenty-fourth MOS transistor M24, the gate of the twenty-first MOS transistor M21 is connected to the gate of the twenty-second MOS transistor M22, and its connection terminal is the first two input exclusive OR/same OR The first inverting input of gate R1, the twenty-first MOS The source of the transistor M21, the source of the twenty-third MOS transistor M23 and the drain of the twenty-fifth MOS transistor M25 are connected, and the gate of the twenty-fourth MOS transistor M24 is the first two-input XOR/XOR gate R1 The second input end of the twenty-fifth MOS transistor M25 is the second inverting input end of the first two-input XOR/NOR gate R1, the source electrode of the twenty-fourth MOS transistor M24, the twenty-fifth The source of the MOS transistor M25 is connected to the drain of the twenty-sixth MOS transistor M26, and the source of the twenty-sixth MOS transistor M26 is grounded; Same-OR gate R3, fourth two-input exclusive-or/same-or gate R4, fifth two-input exclusive-or/same-or gate R5, sixth second-input exclusive-or/same-or gate R6, seventh second-input exclusive-or/same-or The structures of the gate R7 and the eighth two-input XOR/XOR gate R8 are the same as those of the first two-input XOR/XOR gate R1.

As shown in FIG. 6(a) and FIG. 6(b), in this embodiment, the first two-input NOR/OR gate O1 includes a twenty-seventh MOS transistor M27, a twenty-eighth MOS transistor M28, a twenty-eighth MOS transistor M28, and a twenty-eighth MOS transistor M28. Nine MOS tubes M29 Thirty MOS tubes M30, Thirty-first MOS tubes M31, Thirty-second MOS tubes M32 Thirty-third MOS tubes M33, Thirty-fourth MOS tubes M34, Thirty-fifth MOS tubes M35, The thirty-sixth MOS tube M36, the thirty-seventh MOS tube M37 and the thirty-eighth MOS tube M38; the twenty-seventh MOS tube M27, the twenty-eighth MOS tube M28, the twenty-ninth MOS tube M29 and the third The ten MOS tubes M30 are all P-type MOS tubes, the thirty-first MOS tube M31, the thirty-second MOS tube M32, the thirty-third MOS tube M33, the thirty-fourth MOS tube M34, and the thirty-fifth MOS tube M35 , the thirty-sixth MOS tube M36, the thirty-seventh MOS tube M37 and the thirty-eighth MOS tube M38 are all N-type MOS tubes; the source of the twenty-seventh MOS tube M27, the source of the twenty-eighth MOS tube M28 The source, the source of the twenty-ninth MOS transistor M29, the source of the thirtieth MOS transistor M30, and the gate of the thirty-third MOS transistor M33 are all connected to the power supply, and the gate of the twenty-seventh MOS transistor M27, The gate of the thirtieth MOS transistor M30 is connected to the gate of the thirty-eighth MOS transistor M38 and its connection terminal is the clock terminal of the first two-input NOR/OR gate O1, and the drain of the twenty-seventh MOS transistor M27 , the drain of the twenty-eighth MOS transistor M28, the gate of the twenty-ninth MOS transistor M29, the drain of the thirty-first MOS transistor M31 are connected to the gate of the thirty-second MOS transistor M32, and the connection terminals are The NOR logic output terminal of the first two-input NOR/OR gate O1, the drain of the twenty-ninth MOS transistor M29, the drain of the thirtieth MOS transistor M30, the gate of the twenty-eighth MOS transistor M28, the drain of the twenty-eighth MOS transistor M28, The gate of the thirty-first MOS transistor M31 is connected to the drain of the thirty-second MOS transistor M32 and its connection end is the OR logic output end of the first two-input NOR/OR gate O1, and the drain of the thirty-first MOS transistor M31 The source, the drain of the thirty-sixth MOS transistor M36, the drain of the thirty-third MOS transistor M33 and the drain of the thirty-fourth MOS transistor M34 are connected, the source of the thirty-second MOS transistor M32, the third The source of the thirteenth MOS transistor M33 is connected to the drain of the thirty-fifth MOS transistor M35, the gate of the thirty-fourth MOS transistor M34 is the first input terminal of the first two-input NOR/OR gate O1, the thirty-fifth The gate of the fifth MOS transistor M35 is the first inverting input terminal of the first two-input NOR/OR gate O1, and the gate of the thirty-sixth MOS transistor M36 is the second input terminal of the first two-input NOR/OR gate O1 , the gate of the thirty-seventh MOS transistor M37 is the second inverting input terminal of the first two-input NOR/OR gate O1, the source of the thirty-fourth MOS transistor M34, and the source of the thirty-fifth MOS transistor M35 connected to the drain of the thirty-seventh MOS transistor M37, the source of the thirty-sixth MOS transistor M36, and the thirty-sixth MOS transistor M36 The source of the seventh MOS transistor M37 is connected to the drain of the thirty-eighth MOS transistor M38, and the source of the thirty-eighth MOS transistor M38 is grounded; the second two-input NOR/OR gate O2, the third two-input NOR/NOR gate The structures of OR gate O3, the fourth two-input NOR/OR gate O4, the fifth two-input NOR/OR gate O5 and the sixth two-input NOR/OR gate O6 are the same as the first two-input NOR/OR gate O1 .

As shown in Figure 7(a) and Figure 7(b), in this embodiment, the first three-input NOR/OR gate Q1 includes a thirty-ninth MOS transistor M39, a fortieth MOS transistor M40, a forty-first MOS tube M41, forty-second MOS tube M42, forty-third MOS tube M43, forty-fourth MOS tube M44, forty-fifth MOS tube M45, forty-sixth MOS tube M46, forty-seventh MOS tube M47, the forty-eighth MOS tube M48, the forty-ninth MOS tube M49, the fiftieth MOS tube M50, the fifty-first MOS tube M51 and the fifty-second MOS tube M52; the thirty-ninth MOS tube M39, the fifty-second MOS tube M52 The forty MOS tube M40, the forty-first MOS tube M41 and the forty-second MOS tube M42 are all P-type MOS tubes, the forty-third MOS tube M43, the forty-fourth MOS tube M44, and the forty-fifth MOS tube M45, the forty-sixth MOS tube M46, the forty-seventh MOS tube M47, the forty-eighth MOS tube M48, the forty-ninth MOS tube M49, the fiftieth MOS tube M50, the fifty-first MOS tube M51 and the The fifty-two MOS transistors M52 are all N-type MOS transistors; the source of the thirty-ninth MOS transistor M39, the source of the fortieth MOS transistor M40, the source of the forty-first MOS transistor M41, the forty-second MOS The source of the tube M42 and the grid of the forty-fifth MOS tube M45 are connected to the power supply, the grid of the thirty-ninth MOS tube M39, the grid of the forty-second MOS tube M42 and the fifty-second MOS tube M52 and its connection end is the clock end of the first three-input NOR/OR gate Q1; the drain of the thirty-ninth MOS transistor M39, the drain of the fortieth MOS transistor M40, the forty-first MOS transistor The gate of M41, the drain of the forty-third MOS transistor M43 and the gate of the forty-fourth MOS transistor M44 are connected, and its connection end is the NOR logic output end of the first three-input NOR/OR gate Q1, and the first three-input NOR/OR gate Q1. The gate of the forty MOS transistor M40, the drain of the forty-first MOS transistor M41, the drain of the forty-second MOS transistor M42, the gate of the forty-third MOS transistor M43 and the forty-fourth MOS transistor M44 The drain is connected and its connection end is the OR logic output end of the first three-input NOR/OR gate Q1, the source of the forty-third MOS transistor M43, the drain of the forty-fifth MOS transistor M45, the forty-sixth The drain of the MOS transistor M46, the drain of the forty-eighth MOS transistor M48 and the drain of the fiftieth MOS transistor M50 are connected, the source of the forty-fourth MOS transistor M44, and the source of the forty-fifth MOS transistor M45 It is connected to the drain of the forty-seventh MOS transistor M47, the source of the forty-sixth MOS transistor M46, the source of the forty-seventh MOS transistor M47 are connected to the drain of the forty-ninth MOS transistor M49, and the forty-ninth MOS transistor M49 is connected to the drain. The gate of the six MOS transistors M46 is the first input end of the first three-input NOR/OR gate Q1, and the gate of the forty-seventh MOS transistor M47 is the first inverting input end of the first three-input NOR/OR gate Q1 , the gate of the forty-eighth MOS transistor M48 is the first three-input NOR/OR gate Q 1, the gate of the forty-ninth MOS transistor M49 is the second inverting input terminal of the first three-input NOR/OR gate Q1, and the gate of the fiftieth MOS transistor M50 is the first three-input NOR gate. The third input end of the OR gate Q1, the gate of the fifty-first MOS transistor M51 is the third inverting input end of the first three-input NOR/OR gate Q1, the source electrode of the forty-eighth MOS transistor M48, The source of the forty-ninth MOS transistor M49 is connected to the drain of the fifty-first MOS transistor M51, the source of the fiftieth MOS transistor M50, the source of the fifty-first MOS transistor M51 and the fifty-second MOS transistor M52 The drain of the fifty-second MOS transistor M52 is connected to the ground; the structure of the second three-input NOR/OR gate Q2 is the same as that of the first three-input NOR/OR gate Q1.

Using TSMC 65nm CMOS process device parameters, using the Specter tool to simulate and analyze the defensive differential power analysis adder using sensitive amplification logic of the present invention. The P-type MOS width-to-length ratio of each logic gate is 120nm/60nm, the width-to-length ratio of the fourth MOS tube M4 is 120nm/60nm, and the width-to-length ratio of other N-type MOS is 240nm/60nm; the inverter is selected from the TSMC standard cell library INVD0, Figure 8 shows part of the analog waveform, where the operating frequency is 100MHz, the first addend A ₃ A ₂ A ₁ A ₀ , the second addend B ₃ B ₂ B ₁ B ₀ and the carry signal C _in "10100001...", "11000010..." and "01101011..." respectively. As can be seen from the figure, when the clock signal clk=0, the adder is in the precharge stage, and each output signal is precharged to a high level; when the clock signal clk=1, the adder enters the evaluation stage, and its The output C ₃ S ₃ S ₂ S ₁ S ₀ is "10110...", which is consistent with the actual result, which proves that the logic function of the defensive differential power analysis adder using sensitive amplification logic of the present invention is correct.

The defensive differential power analysis adder utilizing sensitive amplified logic of the present invention is compared with the existing traditional 4-bit look-ahead carry adder, and reflects the resistance of the circuit with the difference of power supply current and power consumption in different clock cycles. DPA attack performance. Wherein, Fig. 9 is the electric current graph of existing adder, and Fig. 10 is the power consumption graph of existing adder; Fig. 11 is the current of the defense differential power consumption analysis adder utilizing sensitive amplifying logic of the present invention Curve; FIG. 12 is a power consumption curve of the defense differential power analysis adder utilizing sensitive amplification logic of the present invention. Analysis of Fig. 9 and Fig. 11 shows that the current characteristics of the existing adder power supply depend on the input signal, and corresponding currents will be generated when different input signals are used, while the defensive differential power consumption analysis adder utilizing sensitive amplifying logic of the present invention is in the Each clock cycle has approximately the same supply current characteristics regardless of the input signal. Analysis of Fig. 10 and Fig. 12 shows that the defensive differential power consumption analysis adder using sensitive amplifying logic of the present invention has consistent power consumption curves in different clock cycles, has the characteristic that power consumption is independent of input signals, and can effectively Defend against DPA attacks.

Claims (5)

1. A defensive differential power analysis adder utilizing sensitive amplified logic, characterized in that it comprises the first two input NAND/AND gate, the second two input NAND/AND gate, the third two input NAND/AND gate gate, fourth and second input NAND/AND gate, first and second input XOR/Same-OR gate, second and second input XOR/Same-OR gate, third and second input XOR/Same-OR gate, fourth and second input XOR gate Or/same-or gate, fifth and second input exclusive-or/same-or gate, sixth-second input exclusive-or/same-or gate, seventh-second input exclusive-or/same-or gate, eighth-second input exclusive-or/same-or gate, The first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter, the eighth inverter, the ninth inverter Inverter, Tenth Inverter, Eleventh Inverter, Twelfth Inverter, Thirteenth Inverter, Fourteenth Inverter, Fifteenth Inverter, Sixteenth Inverter 17th inverter, 18th inverter, 19th inverter, 20th inverter, 21st inverter, 22nd inverter and look-ahead carry generation Circuit; the advanced carry generation circuit includes the fifth and second input NAND/AND gate, the sixth and second input NAND/AND gate, the seventh and second input NAND/AND gate, the eighth and second input NAND/AND gate , the ninth and second input NAND/AND gate, the twelfth input NAND/AND gate, the eleventh and second input NAND/AND gate, the twelfth and second input NAND/AND gate, the thirteenth and second input NAND/AND gate, the thirteenth and second input NAND/AND gate /AND gate, the 14th and 2nd input NAND/AND gate, the 1st 2nd input NOR/OR gate, the 2nd 2nd input NOR/OR gate, the 3rd 2nd input NOR/OR gate, the 4th 2nd input or NOT/OR gate, fifth and second input NOR/OR gate, sixth and second input NOR/OR gate, first and third input NOR/OR gate, second and third input NOR/OR gate, twenty-third inverse inverter, twenty-fourth inverter, twenty-fifth inverter, twenty-sixth inverter, twenty-seventh inverter, twenty-eighth inverter, twenty-ninth inverter , the thirtieth inverter, the thirty-first inverter, the thirty-second inverter, the thirty-third inverter, the thirty-fourth inverter, the thirty-fifth inverter, the third Sixteenth inverter, thirty-seventh inverter, thirty-eighth inverter, thirty-ninth inverter, fortieth inverter, forty-first inverter, forty-second inverter Inverter, forty-third inverter, forty-fourth inverter, forty-fifth inverter, forty-sixth inverter, forty-seventh inverter, forty-eighth inverter , the forty-ninth inverter and the fiftieth inverter; the first two-input NAND/AND gate, the second two-input NAND/AND gate, the third two-input AND gate NOT/AND gate, the fourth second input NAND/AND gate, the fifth second input NAND/AND gate, the sixth second input NAND/AND gate, the seventh second Input NAND/AND gate, the eighth and second input NAND/AND gate, the ninth and second input NAND/AND gate, the twelfth input NAND/AND gate, the first Eleven-two-input NAND/AND gate, the twelfth-second-input NAND/AND gate, the thirteenth-second-input NAND/AND gate and the fourteenth-second-input NAND/AND gate The gates respectively have a first input terminal, a first inverting input terminal, a second input terminal, a second inverting input terminal, a clock terminal, and Non-logic output terminals and AND logic output terminals; the first two-input exclusive-or/same-or gate, the second two-input exclusive-or/same-or gate, the third two-input exclusive-or/same-or gate gate, the fourth two-input XOR/XOR gate, the fifth second-input XOR/XOR gate, the sixth second-input XOR/XOR gate, the seventh second The input XOR/NOR gate and the eighth second input XOR/NOR gate respectively have a first input terminal, a first inverting input terminal, a second input terminal, a second inverting input terminal, a clock terminal, NOR logic output and XOR logic output; said first two-input NOR/OR gate, said second two-input NOR/OR gate, said third two-input NOR/OR gate , the fourth second-input NOR/OR gate, the fifth second-input NOR/OR gate and the sixth second-input NOR/OR gate respectively have a first input terminal, a first inversion Input terminal, second input terminal, second inverting input terminal, clock terminal, OR logic output terminal and OR logic output terminal; the first three-input NOR/OR gate and the second three-input OR The NOT/OR gate has a first input terminal, a first inverting input terminal, a second input terminal, a second inverting input terminal, a third input terminal, a third inverting input terminal, a clock terminal, or a non-logic output terminal and or logic output; The clock end of the fifth second input NAND/AND gate, the clock end of the sixth second input NAND/AND gate, the clock end of the seventh second input NAND/AND gate, the The clock end of the eighth second input NAND/AND gate, the clock end of the ninth second input NAND/AND gate, the clock end of the twelfth input NAND/AND gate, the first The clock terminal of the twelve-input NAND/AND gate, the clock terminal of the twelfth-second input NAND/AND gate, the clock terminal of the thirteenth-second input NAND/AND gate, the described The clock end of the fourteenth second-input NAND/AND gate, the clock end of the first two-input NOR/OR gate, the clock end of the second two-input NOR/OR gate, the first two-input NOR/OR gate, The clock terminal of the three-two input NOR/OR gate, the clock terminal of the fourth two-input NOR/OR gate, the clock terminal of the fifth two-input NOR/OR gate, the sixth two-input NOR gate The clock end of the input NOR/OR gate, the clock end of the first three-input NOR/OR gate and the clock end of the second three-input NOR/OR gate are connected and its connection end is the described The clock end of the forward shift generation circuit; the first input end of the fifth and second input NAND/AND gate, the first input end of the eleventh and second input NAND/AND gate, the first input end of the described first second input NAND/AND gate The first input end of the thirteenth two-input NAND/AND gate is connected to the first input end of the fourteenth second-input NAND/AND gate, and its connection end is the fourth of the advanced carry generation circuit. The carry transmission signal input terminal is used to input the fourth carry transmission signal; the first inverting input terminal of the fifth and second input NAND/AND gate, the first inverting input terminal of the eleventh and second input NAND/AND gate An inverting input terminal, the first inverting input terminal of the thirteenth second input NAND/AND gate and the first inverting input terminal of the fourteenth second input NAND/AND gate are connected and its The connection terminal is the input terminal of the fourth inverted carry transmission signal of the advanced carry generating circuit, which is used to input the fourth inverted carry transmission signal; the second input terminal of the fifth two-input NAND/AND gate It is connected to the second input end of the fourth two-input NOR/OR gate and its connection end is the third carry generation signal input end of the advanced carry generation circuit, which is used to input the third carry generation signal; The second inverting input end of the fifth two-input NAND/AND gate is connected with the second inverting input end of the fourth two-input NOR/OR gate, and its connection end is the advanced advance The third inverted carry generation signal input end of the bit generation circuit is used to input the third inverted carry generation signal; the first input end of the sixth and second input NAND/AND gate, the ninth second input The first input end of the NAND/AND gate is connected to the first input end of the twelfth input NAND/AND gate, and its connection end is the third carry transmission signal input of the advanced carry generation circuit terminal, used to input the third carry transmission signal; the first inverting input terminal of the sixth second input NAND/AND gate, the first inverting input terminal of the ninth second input NAND/AND gate It is connected with the first inverting input terminal of the twelfth input NAND/AND gate and its connection terminal is the third inverting carry transmission signal input terminal of the described advanced carry generation circuit, for Input the third inverted carry transmission signal; the second input end of the sixth second input NAND/AND gate is connected with the third input end of the first three input NOR/OR gate and its connection end is The second carry generation signal input end of the advanced carry generation circuit is used to input the second carry generation signal; the second inverting input end of the sixth second-input NAND/AND gate and the first The third inversion input end of a three-input NOR/OR gate is connected and its connection end is the second inversion carry generation signal input end of the described advanced carry generation circuit, which is used to input the second inversion carry generation signal ; The first input end of the seventh and second input NAND/AND gate is connected with the first input end of the described twelfth input NAND/AND gate and its connection end is the described advanced carry generation circuit The second carry transmission signal input terminal is used to input the second carry transmission signal; the first inverting input terminal of the seventh and second input NAND/AND gate and the twelfth input NAND/AND gate The first inverting input terminal of is connected and its connecting terminal is the second inverting carry transmission signal input terminal of the described advanced carry generating circuit, which is used to input the second inverting carry transmission signal; the seventh and second input The second input end of the NAND/AND gate is connected to the second input end of the fifth two-input NOR/OR gate, and its connection end is the first carry generation signal input end of the advanced carry generation circuit , used to input the first carry generation signal; the second inverting input terminal of the seventh two-input NAND/AND gate is connected to the second inverting input terminal of the fifth two-input NOR/OR gate And its connection terminal is the first inverted carry generation signal input end of the described advanced carry generation circuit, which is used to input the first inverted carry generation signal; the first of the eighth second input NAND/AND gate The input terminal is the first carry transmission signal input terminal of the advanced carry generation circuit, which is used to input the first carry transmission signal P0; the first inverting input terminal of the eighth second input NAND/AND gate is The first inverted carry transmission signal input terminal of the advanced carry generation circuit is used to input the first inverted carry transmission signal The second input end of the eighth second input NAND/AND gate is the low-order carry signal input end of the described advanced carry generation circuit, which is used to input the low-order carry signal; the eighth second input NAND/AND gate is used to input the low-order carry signal; The second inverting input end of the AND gate is the inverting low-order carry signal input end of the described advanced carry generating circuit, which is used to input the inverting low-order carry signal; the AND of the fifth two-input NAND/AND gate The non-logic output terminal is connected to the input terminal of the twenty-third inverter, and the AND logic output terminal of the fifth and second input NAND/AND gate is connected to the input of the twenty-fourth inverter. terminal connection, the NAND logic output terminal of the sixth second input NAND/AND gate is connected to the input terminal of the twenty-fifth inverter, and the sixth second input NAND/AND gate It is connected with the logic output terminal and the input terminal of the twenty-sixth inverter, and the NAND logic output terminal of the seventh-second input NAND/AND gate is connected with the input terminal of the twenty-seventh inverter. The input end is connected, the AND logic output end of the described seventh and second input NAND/AND gate is connected with the input end of the twenty-eighth inverter, and the eighth second input NAND/AND gate is connected The NAND logic output terminal is connected to the input terminal of the twenty-ninth inverter, and the AND logic output terminal of the eighth and second input NAND/AND gate is connected to the input terminal of the thirty-ninth inverter. terminal connection, the NAND logic output terminal of the 92nd input NAND/AND gate is connected with the input terminal of the 31st inverter, the 92nd input NAND/AND gate It is connected with the logic output terminal and the input terminal of the 32nd inverter, and the NAND logic output terminal of the twelfth input NAND/AND gate is connected with the input terminal of the 33rd inverter. The input terminal is connected, the AND logic output terminal of the twelfth input NAND/AND gate is connected with the input terminal of the thirty-fourth inverter, and the eleventh and second input NAND/AND gate The NAND logic output terminal is connected to the input terminal of the thirty-fifth inverter, and the NAND logic output terminal of the eleventh-second input NAND/AND gate is connected to the thirty-sixth inverter connected to the input of the inverter, the NAND logic output of the twelfth-second input NAND/AND gate is connected to the input of the thirty-seventh inverter, and the twelfth-second input and The NAND logic output terminal of the NAND gate is connected to the input terminal of the thirty-eighth inverter, and the NAND logic output terminal of the thirteenth second-input NAND/AND gate is connected to the third input NAND logic output terminal of the NAND gate. The input terminals of the nineteenth inverters are connected, the AND logic output terminals of the thirteenth and second input NAND/AND gates are connected with the input terminals of the fortieth inverters, and the fourteenth and second The NAND logic output end of the input NAND/AND gate is connected to the input end of the forty-first inverter, and the AND logic output end of the fourteenth second input NAND/AND gate is connected to the input end of the forty-first inverter. The input end of the forty-second inverter is connected, the NOR logic output end of the first two-input NOR/OR gate is connected to the input end of the forty-third inverter, and the first The OR logic output end of a two-input NOR/OR gate is connected to the input end of the forty-fourth inverter, and the NOR logic output end of the second two-input NOR/OR gate is connected to the input end of the forty-fourth inverter. The input of the forty-fifth inverter terminal connection, the OR logic output terminal of the second two-input NOR/OR gate is connected to the input terminal of the forty-sixth inverter, and the OR of the third two-input NOR/OR gate The non-logic output terminal is connected to the input terminal of the forty-seventh inverter, and the OR logic output terminal of the third and second input NOR/OR gate is connected to the input terminal of the forty-eighth inverter. terminal connection, the NOR logic output terminal of the fourth two-input NOR/OR gate is connected to the input terminal of the forty-ninth inverter, and the fourth two-input NOR/OR gate The OR logic output terminal is connected to the input terminal of the fiftieth inverter, and the output terminal of the twenty-third inverter is connected to the first input terminal of the second two-input NOR/OR gate connected, the output of the twenty-fourth inverter is connected to the first inverting input of the second two-input NOR/OR gate, and the output of the twenty-fifth inverter , the second input end of the eleventh second-input NAND/AND gate is connected to the first input end of the fourth second-input NOR/OR gate, and the twenty-sixth inverter The output terminal, the second inverting input terminal of the eleventh two-input NAND/AND gate and the first inverting input terminal of the fourth two-input NOR/OR gate are connected, and the second The output terminal of the seventeenth inverter, the second input terminal of the ninth and second input NAND/AND gate and the second input terminal of the first three-input NOR/OR gate are connected, and the first The output terminal of the twenty-eight inverters, the second inverting input terminal of the ninth and second input NAND/AND gate and the second inverting input terminal of the first three-input NOR/OR gate are connected , the output end of the twenty-ninth inverter, the second input end of the twelfth input NAND/AND gate and the first input end of the fifth second input NOR/OR gate connected, the output of the thirtieth inverter, the second inverting input of the twelfth input NAND/AND gate and the first of the fifth second input NOR/OR gate The inverting input terminal is connected, the output terminal of the thirty-first inverter, the second input terminal of the thirteenth second-input NAND/AND gate and the third second-input NOR/OR The second input end of the gate is connected to the output end of the thirty-second inverter, the second inverting input end of the thirteenth second-input NAND/AND gate and the third second input The second inverting input end of the NOR/OR gate is connected, the output end of the 33rd inverter, the second input end of the twelfth second input NAND/AND gate and the described The first input terminal of the first three-input NOR/OR gate is connected, the output terminal of the thirty-fourth inverter, the second inverting input terminal of the twelfth-second input NAND/AND gate It is connected with the first inverting input end of the first three-input NOR/OR gate, the output end of the thirty-fifth inverter is connected with the first two-input NOR/OR gate of the first The two input ends are connected, the output end of the thirty-sixth inverter is connected to the second inverting input end of the first two-input NOR/OR gate, and the thirty-seventh inverter The output terminal, the second input terminal of the fourteenth second-input NAND/AND gate and the first input terminal of the third second-input NOR/OR gate are connected, The output end of the thirty-eighth inverter, the second inverting input end of the fourteenth second-input NAND/AND gate and the first of the third second-input NOR/OR gate The inverting input terminal is connected, the output terminal of the thirty-ninth inverter is connected to the first input terminal of the first two-input NOR/OR gate, and the output of the fortieth inverter end is connected with the first inverting input end of the first two-input NOR/OR gate, the output end of the forty-first inverter is connected with the second three-input NOR/OR gate The first input terminal is connected, the output terminal of the forty-second inverter is connected with the first inverting input terminal of the second three-input NOR/OR gate, and the forty-third inverting The output end of the inverter is connected to the second input end of the second three-input NOR/OR gate, the output end of the forty-fourth inverter is connected to the second three-input NOR/OR gate The second inverting input terminal of the described forty-fifth inverter is connected with the third input terminal of the second three-input NOR/OR gate, and the forty-sixth inverter The output end of the phaser is connected to the third inverting input end of the second three-input NOR/OR gate, and the output end of the forty-seventh inverter is connected to the sixth second input NOR gate. The first input end of the OR gate is connected, the output end of the forty-eighth inverter is connected with the first inverting input end of the sixth second input NOR/OR gate, and the fourth The output end of the nineteenth inverter is connected to the second input end of the sixth second-input NOR/OR gate, and the output end of the fiftieth inverter is connected to the sixth second-input NOR gate. The second inverting input terminal of the OR gate is connected, and the NOR logic output terminal of the fifth two-input NOR/OR gate is the first high-order carry signal output terminal of the described advanced carry generation circuit, for Outputting the first high-order carry signal, the OR logic output terminal of the fifth two-input NOR/OR gate is the first inverted high-order carry signal output terminal of the described advanced carry generation circuit, which is used to output the first inverted Phase high-order carry signal, the NOR logic output terminal of the first three-input NOR/OR gate is the second high-order carry signal output end of the described advanced carry generation circuit, which is used to output the second high-order carry signal; The OR logic output end of the first three-input NOR/OR gate is the second inverting high-order carry signal output end of the described advanced carry generating circuit, which is used to output the second inverting high-order carry signal; The NOR logic output end of the sixth second input NOR/OR gate is the third high-order carry signal output end of the described advanced carry generating circuit, which is used to output the third high-order carry signal, and the sixth second input The OR logic output end of the NOR/OR gate is the third inverting high-order carry signal output end of the advanced carry generating circuit, which is used to output the third inverting high-order carry signal, and the second three-input NOR The NOR logic output terminal of the OR gate is the fourth high-order carry signal output terminal of the described advanced carry generation circuit, which is used to output the fourth high-order carry signal; the OR of the second three-input NOR/OR gate The logic output terminal is the fourth inverting high-order carry signal output terminal of the advanced carry generating circuit, which is used to output the fourth inverting high-order carry signal; The second input end of the second two-input NOR/OR gate is the fourth carry generation signal input end of the advanced carry generation circuit, which is used to input the fourth carry generation signal; the second two The second inverting input terminal of the input NOR/OR gate is the fourth inverting carry generating signal input end of the described advanced carry generating circuit, which is used to input the fourth inverting carrying generating signal; the first two Input the clock end of the NAND/AND gate, the clock end of the second two-input NAND/AND gate, the clock end of the third two-input NAND/AND gate, the fourth two-input AND gate The clock end of the NOT/AND gate, the clock end of the first two-input XOR/XOR gate, the clock end of the second two-input XOR/XOR gate, the third two-input XOR gate The clock end of the OR/NOR gate, the clock end of the fourth two-input XOR/NOR gate, the clock end of the fifth two-input XOR/NOR gate, the sixth second input The clock end of the XOR/NOR gate, the clock end of the seventh second input XOR/NOR gate, the clock end of the eighth second input XOR/NOR gate and the advanced carry The clock end of the generation circuit is connected, the low-order carry signal input end of the advanced carry generation circuit is connected with the second inverting input end of the fifth two-input XOR/NOR gate, and its connection end is the The low-order carry signal input end of the adder; the inverting low-order carry signal input end of the described advanced carry generation circuit is connected with the second input end of the fifth two-input XOR/NOR gate and its connection end It is the inverting low-order carry signal input end of the adder; the first input end of the first two-input NAND/AND gate and the first input end of the first two-input XOR/NOR gate The terminal is connected and its connection terminal is the first input terminal of the adder, which is used to input the first bit signal of the first four-bit addend signal; the first two-input NAND/AND gate of the first two The inverting input terminal is connected with the first inverting input terminal of the first two-input XOR/NOR gate and its connection terminal is the first inverting input terminal of the adder, which is used to input the first The first inversion signal of the four-bit addend signal; the second input end of the first two-input NAND/AND gate is connected with the second input end of the first two-input XOR/NOR gate And its connection end is the second input end of described adder, is used for inputting the first bit signal of the second four-bit addend signal, and the second inverting phase of the first two input NAND/AND gates The input end is connected with the second inverting input end of the first two-input XOR/NOR gate and its connection end is the second inverting input end of the adder, which is used to input the second four bits The first inversion signal of the addend signal; the first input end of the second two-input NAND/AND gate is connected with the first input end of the second two-input XOR/NOR gate and its The connection terminal is the third input terminal of the adder, which is used to input the second bit signal of the first four-bit addend signal; the first inverting input terminal of the second two-input NAND/AND gate It is connected with the first inverting input end of the second two-input XOR/NOR gate and its connection end is the third inverting input end of the adder for inputting the first four-bit addition The second bit inversion signal of digital signal; The second input end of described second two-input NAND/AND gate is connected with the second input end of described second two-input XOR/NOR gate and it is connected End is the fourth input end of described adder, is used for inputting the second bit signal of the second four-bit addend signal; The second inverting input end of described second two input NAND/AND gate and The second inverting input terminal of the second two-input XOR/NOR gate is connected and its connection end is the fourth inverting input terminal of the adder, which is used to input the second four-bit addend signal The second inverting signal of the second bit; the first input end of the third two-input NAND/AND gate is connected with the first input end of the third two-input XOR/NOR gate and its connection end is The fifth input terminal of the adder is used to input the third bit signal of the first four-bit addend signal; the first inverting input terminal of the third two-input NAND/AND gate and the described The first inverting input end of the third two-input XOR/NOR gate is connected and its connection end is the fifth inverting input end of the adder, which is used to input the first four-bit addend signal Three-bit inversion signal; the second input end of the third two-input NAND/AND gate is connected with the second input end of the third two-input XOR/NOR gate and its connection end is the described The sixth input terminal of the adder is used to input the third signal of the second four-bit addend signal; the second inverting input terminal of the third two-input NAND/AND gate and the first The second inverting input terminal of the three-two input XOR/NOR gate is connected and its connection end is the sixth inverting input terminal of the adder, which is used to input the third bit of the second four-bit addend signal Inversion signal; the first input end of the fourth two-input NAND/AND gate is connected with the first input end of the fourth two-input XOR/NOR gate and its connection end is the addition The seventh input terminal of the device is used to input the fourth bit signal of the first four-bit addend signal; the first inverting input terminal of the fourth two-input NAND/AND gate and the fourth two-bit The first inverting input terminal of the input XOR/NOR gate is connected and its connection terminal is the seventh inverting input terminal of the adder, which is used to input the fourth bit inversion of the first four-bit addend signal Signal; the second input end of the fourth two-input NAND/AND gate is connected with the second input end of the fourth two-input XOR/NOR gate and its connection end is the adder The eighth input terminal is used to input the fourth bit signal of the second four-bit addend signal; the second inverting input terminal of the fourth two-input NAND/AND gate and the fourth two-input exclusive The OR/OR gate is connected to the second inverting input terminal and its connection end is the eighth inverting input terminal of the adder, which is used to input the fourth inverting signal of the second four-bit addend signal; The NAND logic output terminal of the first two-input NAND/AND gate is connected to the input terminal of the first inverter, and the output terminal of the first inverter is connected to the advanced carry The first carry generation signal input terminal of the generating circuit is connected, the AND logic output terminal of the first two-input NAND/AND gate is connected to the input terminal of the second inverter, and the second inverter The output terminal of the device and the first carry generation circuit of the look-ahead An inverting carry generation signal input terminal is connected, the exclusive OR logic output terminal of the first two-input exclusive OR/exclusive OR gate is connected to the input terminal of the third inverter, and the third inverter The output terminal of the device, the first inverting carry transmission signal input terminal of the advanced carry generation circuit and the second inverting input terminal of the fifth two-input XOR/NOR gate are connected, and the first The NOR logic output terminal of a two-input XOR/NOR gate is connected to the input terminal of the fourth inverter, the output terminal of the fourth inverter, the advanced carry generation circuit The first carry transmission signal input end is connected to the second input end of the fifth two-input XOR/NOR gate, and the NAND logic output end of the second two-input NAND/AND gate is connected to the NAND logic output end of the second two-input NAND/AND gate. The input end of the fifth inverter is connected, the output end of the fifth inverter is connected with the second carry generation signal input end of the advanced carry generation circuit, and the second two input NAND/ The AND logic output terminal of the AND gate is connected to the input terminal of the sixth inverter, and the output terminal of the sixth inverter and the second inverted carry generation signal input of the advanced carry generation circuit are input terminal connection, the XOR logic output terminal of the second two-input XOR/NOR gate is connected to the input terminal of the seventh inverter, the output terminal of the seventh inverter, the The second inverting carry transmission signal input terminal of the advanced carry generation circuit is connected to the second inverting input terminal of the sixth two-input XOR/NOR gate, and the second two-input XOR/NOR gate is connected The NOR logic output end of the OR gate is connected to the input end of the eighth inverter, the output end of the eighth inverter, and the second carry transmission signal input end of the advanced carry generation circuit It is connected with the second input terminal of the sixth two-input XOR/NOR gate, the NAND logic output terminal of the third two-input NAND/AND gate and the input of the ninth inverter terminal connection, the output terminal of the ninth inverter is connected to the third carry generation signal input terminal of the advanced carry generation circuit, and the AND logic output terminal of the third two-input NAND/AND gate It is connected with the input end of the tenth inverter, the output end of the tenth inverter is connected with the third inverted carry generation signal input end of the advanced carry generation circuit, and the first The XOR logic output terminal of the three-two input XOR/XOR gate is connected to the input terminal of the eleventh inverter, and the output terminal of the eleventh inverter and the advanced carry generation are generated The third inverting carry transmission signal input end of the circuit is connected to the second inverting input end of the seventh two-input XOR/NOR gate, and the NOR of the third two-input XOR/NOR gate The logic output terminal is connected to the input terminal of the twelfth inverter, the output terminal of the twelfth inverter, the third carry transmission signal input terminal of the advanced carry generation circuit and the The second input end of the seventh second input XOR/NOR gate is connected, and the NAND logic output end of the fourth second input NAND/AND gate is connected to the input end of the thirteenth inverter , the output terminal of the thirteenth inverter and the fourth carry generation signal input terminal of the advanced carry generation circuit connected, the AND logic output terminal of the fourth two-input NAND/AND gate is connected to the input terminal of the fourteenth inverter, and the output terminal of the fourteenth inverter is connected to the The fourth inverted carry generation signal input terminal of the advanced carry generation circuit is connected, and the exclusive OR logic output terminal of the fourth two-input XOR/NOR gate is connected to the input terminal of the fifteenth inverter , the output terminal of the fifteenth inverter, the fourth inverting carry transmission signal input terminal of the advanced carry generating circuit and the second inverting of the eighth second input XOR/XOR gate The phase input terminal is connected, the NOR logic output terminal of the fourth two-input XOR/NOR gate is connected to the input terminal of the sixteenth inverter, and the output of the sixteenth inverter Terminal, the fourth carry transmission signal input end of the described advanced carry generation circuit is connected with the second input end of the eighth second input XOR/NOR gate, the first of the described advanced carry generation circuit The output terminal of the high-order carry signal is connected to the input terminal of the seventeenth inverter, and the output terminal of the seventeenth inverter is connected to the first inverter of the sixth and second input XOR/NOR gate. The phase input terminal is connected, the first inverted high-order carry signal output terminal of the advanced carry generation circuit is connected to the input terminal of the eighteenth inverter, and the output terminal of the eighteenth inverter It is connected with the first input terminal of the sixth and second input XOR/NOR gate, the second high-order carry signal output terminal of the advanced carry generation circuit and the input terminal of the nineteenth inverter connected, the output terminal of the nineteenth inverter is connected to the first inverting input terminal of the seventy-two input XOR/NOR gate, and the second inverting input terminal of the advanced carry generation circuit The high-order carry signal output terminal is connected to the input terminal of the twentieth inverter, and the output terminal of the twentieth inverter is connected to the first input of the seventh and second input XOR/NOR gate The third high-order carry signal output terminal of the advanced carry generation circuit is connected to the input terminal of the twenty-first inverter, and the output terminal of the twenty-first inverter is connected to the input terminal of the twenty-first inverter. The first inverting input end of the eighth second-input XOR/NOR gate is connected, the third inverting high-order carry signal output end of the advanced carry generation circuit is connected to the twenty-second inverter The input terminal of the said twenty-second inverter is connected to the first input terminal of the eighth second-input XOR/NOR gate, and the fourth of the advanced carry generation circuit The high-order carry signal output end is the high-order carry signal output end of the adder, and the fourth inverting high-order carry signal output end of the described advanced carry generation circuit is the inverting high-order carry signal output end of the adder ; The same OR output end of the fifth two input XOR/NOR gate is the first output end of the adder, and the XOR output end of the fifth second input XOR/NOR gate is The first inverting output of the adder, the NOR output of the sixth second input XOR/NOR gate is the second output of the adder, the sixth second input The XOR output of the XOR/XOR gate is the second inverting output of the adder, and the seventh second input XOR The NOR output of the NOR gate is the third output of the adder, and the seventh second input XOR/NOR output of the NOR gate is the third inversion of the adder The output terminal, the NOR output terminal of the eighth second input XOR/NOR gate is the fourth output terminal of the adder, the XOR output of the eighth second input XOR/NOR gate The terminal is the fourth inverting output terminal of the adder. 2. A kind of defensive differential power analysis adder utilizing sensitive amplified logic according to claim 1, characterized in that said first two-input NAND/AND gate comprises a first MOS transistor, a second MOS transistor , the third MOS tube, the fourth MOS tube, the fifth MOS tube, the sixth MOS tube, the seventh MOS tube, the eighth MOS tube, the ninth MOS tube, the tenth MOS tube, the eleventh MOS tube and the twelfth MOS tube MOS tube; the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are all P-type MOS tubes, the fifth MOS tube, the The sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor, the ninth MOS transistor, the tenth MOS transistor, the eleventh MOS transistor and the The twelfth MOS transistor is an N-type MOS transistor; the source of the first MOS transistor, the source of the second MOS transistor, the source of the third MOS transistor, the first MOS transistor The sources of the four MOS transistors and the grid of the seventh MOS transistor are connected to the power supply, the grid of the first MOS transistor, the grid of the fourth MOS transistor and the twelfth MOS transistor The gate of the MOS transistor is connected and its connection terminal is the clock terminal of the first two input NAND/AND gates, the drain of the first MOS transistor, the drain of the second MOS transistor, the The gate of the third MOS transistor, the drain of the fifth MOS transistor and the gate of the sixth MOS transistor are connected, and the connection terminal is the first two-input NAND/AND gate NAND logic output terminal, the gate of the second MOS transistor, the drain of the third MOS transistor, the drain of the fourth MOS transistor, the gate of the fifth MOS transistor and The drain of the sixth MOS transistor is connected and its connection end is the AND logic output end of the first two-input NAND/AND gate, the source of the fifth MOS transistor, the seventh MOS transistor The drain of the MOS transistor is connected to the drain of the eighth MOS transistor, the source of the sixth MOS transistor, the source of the seventh MOS transistor, and the drain of the ninth MOS transistor connected to the drain of the eleventh MOS transistor, the source of the eighth MOS transistor, the drain of the tenth MOS transistor and the source of the ninth MOS transistor, the The gate of the eighth MOS transistor is the first input end of the first two-input NAND/AND gate, and the gate of the ninth MOS transistor is the first input terminal of the first two-input NAND/AND gate. An inverting input terminal, the gate of the tenth MOS transistor is the second input terminal of the first two-input NAND/AND gate, and the gate of the eleventh MOS transistor is the first The second inverting input terminal of the two-input NAND/AND gate, the source of the tenth MOS transistor, the source of the eleventh MOS transistor and the drain of the twelfth MOS transistor are connected , the source of the twelfth MOS transistor is grounded; the second two-input NAND/AND gate, the third two-input NAND/AND gate, the fourth two-input NAND/AND gate, AND gate, the fifth second input NAND/AND gate, the sixth second input AND NOT/AND gate, said seventh second input NAND/AND gate, said eighth second input NAND/AND gate, said ninth second input NAND/AND gate, said twelfth Input NAND/AND gate, said eleventh and second input NAND/AND gate, said twelfth and second input NAND/AND gate, said thirteenth and second input NAND/AND gate and said The structure of the fourteenth or second-input NAND/AND gate is the same as that of the first or second-input NAND/AND gate. 3. A defense differential power analysis adder utilizing sensitive amplified logic according to claim 1, characterized in that said first two-input XOR/XOR gate comprises a thirteenth MOS transistor, a tenth Four MOS tubes, fifteenth MOS tubes, sixteenth MOS tubes, seventeenth MOS tubes, eighteenth MOS tubes, nineteenth MOS tubes, twentieth MOS tubes, twenty-first MOS tubes, twentieth MOS tubes The second MOS tube, the twenty-third MOS tube, the twenty-fourth MOS tube, the twenty-fifth MOS tube, and the twenty-sixth MOS tube; the thirteenth MOS tube, the fourteenth MOS tube, The fifteenth MOS tube and the sixteenth MOS tube are P-type MOS tubes, the seventeenth MOS tube, the eighteenth MOS tube, and the nineteenth MOS tube , the twentieth MOS transistor, the twenty-first MOS transistor, the twenty-second MOS transistor, the twenty-third MOS transistor, the twenty-fourth MOS transistor, The twenty-fifth MOS transistor and the twenty-sixth MOS transistor are both N-type MOS transistors; the source of the thirteenth MOS transistor, the source of the fourteenth MOS transistor, The source of the fifteenth MOS transistor, the source of the sixteenth MOS transistor and the gate of the nineteenth MOS transistor are all connected to the power supply, and the gate of the thirteenth MOS transistor Pole, the gate of the sixteenth MOS transistor is connected to the gate of the twenty-sixth MOS transistor, and its connection end is the clock end of the first two-input XOR/XOR gate, so The drain of the thirteenth MOS transistor, the drain of the fourteenth MOS transistor, the gate of the fifteenth MOS transistor, the drain of the seventeenth MOS transistor and the The gate of the eighteenth MOS transistor is connected and its connection end is the NOR logic output end of the first two input XOR/NOR gates, the gate of the fourteenth MOS transistor, the first The drain of the fifteenth MOS transistor, the drain of the sixteenth MOS transistor, the gate of the seventeenth MOS transistor and the drain of the eighteenth MOS transistor are connected, and the connection terminals thereof are the The XOR logic output terminal of the first two-input XOR/XOR gate, the source of the seventeenth MOS transistor, the drain of the nineteenth MOS transistor, the twentieth MOS transistor The drain of the tube is connected to the drain of the twenty-first MOS tube, the source of the eighteenth MOS tube, the source of the nineteenth MOS tube, the twenty-second MOS tube The drain of the MOS transistor is connected to the drain of the twenty-third MOS transistor, the gate of the twenty-third MOS transistor is connected to the gate of the twenty-third MOS transistor, and its connection terminal is The first input terminal of the first two-input XOR/XOR gate, the source of the twentieth MOS transistor, the source of the twenty-second MOS transistor and the twenty The drains of the four MOS transistors are connected, the gate of the twenty-first MOS transistor is connected to the gate of the twenty-second MOS transistor, and its connection terminal is the exclusive OR/simultaneity of the first two inputs The first inverting input terminal of the OR gate, the source of the twenty-first MOS transistor, the twenty-third M The source of the OS transistor is connected to the drain of the twenty-fifth MOS transistor, and the gate of the twenty-fourth MOS transistor is the second input end of the first two-input XOR/XOR gate , the gate of the twenty-fifth MOS transistor is the second inverting input terminal of the first two-input XOR/XOR gate, the source of the twenty-fourth MOS transistor, the The source of the twenty-fifth MOS transistor is connected to the drain of the twenty-sixth MOS transistor, and the source of the twenty-sixth MOS transistor is grounded; the second two inputs are exclusive OR/same OR gate, the third two-input XOR/XOR gate, the fourth second-input XOR/XOR gate, the fifth second-input XOR/XOR gate, the sixth second The structure of the input XOR/XOR gate, the seventh and second input XOR/XOR gate and the eighth second input XOR/XOR gate and the first and second input XOR/XOR gate The door is the same. 4. A defense differential power analysis adder utilizing sensitive amplified logic according to claim 1, characterized in that said first two-input NOR/OR gate comprises a twenty-seventh MOS transistor, a second 18th MOS tube, 29th MOS tube, 30th MOS tube, 31st MOS tube, 32nd MOS tube, 33rd MOS tube, 34th MOS tube, 35th MOS tube , the thirty-sixth MOS tube, the thirty-seventh MOS tube and the thirty-eighth MOS tube; The twenty-seventh MOS tube, the twenty-eighth MOS tube, the twenty-ninth MOS tube, and the thirty-ninth MOS tube are all P-type MOS tubes, and the third The eleventh MOS tube, the thirty-second MOS tube, the thirty-third MOS tube, the thirty-fourth MOS tube, the thirty-fifth MOS tube, the third The sixteenth MOS tube, the thirty-seventh MOS tube and the thirty-eighth MOS tube are all N-type MOS tubes; the source of the twenty-seventh MOS tube, the twenty-seventh MOS tube The sources of the eight MOS transistors, the source of the twenty-ninth MOS transistor, the source of the thirtieth MOS transistor and the gate of the thirty-third MOS transistor are all connected to the power supply, so The gate of the twenty-seventh MOS transistor, the gate of the thirtieth MOS transistor, and the gate of the thirty-eighth MOS transistor are connected, and the connection terminals are the first and second inputs or The clock terminal of the NOT/OR gate, the drain of the twenty-seventh MOS transistor, the drain of the twenty-eighth MOS transistor, the gate of the twenty-ninth MOS transistor, the The drain of the thirty-first MOS transistor is connected to the gate of the thirty-second MOS transistor, and its connection terminal is the NOR logic output terminal of the first two-input NOR/OR gate, and the The drain of the twenty-ninth MOS transistor, the drain of the thirtieth MOS transistor, the gate of the twenty-eighth MOS transistor, the gate of the thirty-first MOS transistor and the The drain of the thirty-second MOS transistor is connected and its connection end is the OR logic output end of the first two-input NOR/OR gate, the source of the thirty-first MOS transistor, the The drain of the thirty-sixth MOS transistor, the drain of the thirty-third MOS transistor and the drain of the thirty-fourth MOS transistor are connected, the source of the thirty-second MOS transistor, The source of the thirty-third MOS transistor is connected to the drain of the thirty-fifth MOS transistor, and the gate of the thirty-fourth MOS transistor is the first two input OR/OR The first input end of the gate, the gate of the thirty-fifth MOS transistor is the first inverting input end of the first two-input NOR/OR gate, the gate of the thirty-sixth MOS transistor It is the second input end of the first two-input NOR/OR gate, and the gate of the thirty-seventh MOS transistor is the second inverting input end of the first two-input NOR/OR gate , the source of the thirty-fourth MOS transistor, the source of the thirty-fifth MOS transistor and the drain of the thirty-seventh MOS transistor are connected, and the thirty-sixth MOS transistor The source of the thirty-seventh MOS transistor is connected to the drain of the thirty-eighth MOS transistor, and the source of the thirty-eighth MOS transistor is grounded; the second Two-input NOR/OR gate, said third two-input NOR/OR gate, said fourth two-input NOR/OR gate, said fifth two-input NOR/OR gate and said The structure of the sixth second-input NOR/OR gate is the same as that of the first two-input NOR/OR gate. 5. A defense differential power analysis adder utilizing sensitive amplified logic according to claim 1, characterized in that said first three-input NOR/OR gate comprises a thirty-ninth MOS transistor, a fourth Ten MOS tubes, forty-first MOS tubes, forty-second MOS tubes, forty-third MOS tubes, forty-fourth MOS tubes, forty-fifth MOS tubes, forty-sixth MOS tubes, forty-seventh MOS tube, the forty-eighth MOS tube, the forty-ninth MOS tube, the fiftieth MOS tube, the fifty-first MOS tube, and the fifty-second MOS tube; the thirty-ninth MOS tube, the The fortieth MOS tube, the forty-first MOS tube and the forty-second MOS tube are all P-type MOS tubes, the forty-third MOS tube, the forty-fourth MOS tube tube, the forty-fifth MOS tube, the forty-sixth MOS tube, the forty-seventh MOS tube, the forty-eighth MOS tube, the forty-ninth MOS tube tube, the fiftieth MOS tube, the fifty-first MOS tube and the fifty-second MOS tube are all N-type MOS tubes; the source of the thirty-ninth MOS tube, The source of the fortieth MOS transistor, the source of the forty-first MOS transistor, the source of the forty-second MOS transistor, and the gate of the forty-fifth MOS transistor are connected to the power supply, the grid of the thirty-ninth MOS transistor, the grid of the forty-second MOS transistor and the grid of the fifty-second MOS transistor are connected, and the connection terminals are the The clock terminal of the first three-input NOR/OR gate; the drain of the thirty-ninth MOS transistor, the drain of the fortieth MOS transistor, and the forty-first MOS transistor The gate, the drain of the forty-third MOS transistor and the gate of the forty-fourth MOS transistor are connected, and the connection end is the NOR logic of the first three-input NOR/OR gate Output terminal, the gate of the fortieth MOS transistor, the drain of the forty-first MOS transistor, the drain of the forty-second MOS transistor, the forty-third MOS transistor The gate of the gate is connected to the drain of the forty-fourth MOS transistor and its connection end is the OR logic output end of the first three-input NOR/OR gate, and the drain of the forty-third MOS transistor source, the drain of the forty-fifth MOS transistor, the drain of the forty-sixth MOS transistor, the drain of the forty-eighth MOS transistor and the fiftieth MOS transistor The drain of the forty-fourth MOS transistor, the source of the forty-fifth MOS transistor and the drain of the forty-seventh MOS transistor are connected, and the fourth The source of the sixteenth MOS transistor, the source of the forty-seventh MOS transistor and the drain of the forty-ninth MOS transistor are connected, and the gate of the forty-sixth MOS transistor is the The first input end of the first three-input NOR/OR gate, the gate of the forty-seventh MOS transistor is the first inverting input end of the first three-input NOR/OR gate, the said The gate of the forty-eighth MOS transistor is the second input terminal of the first three-input NOR/OR gate, and the forty-ninth The gate of the MOS transistor is the second inverting input terminal of the first three-input NOR/OR gate, and the grid of the fiftieth MOS transistor is the first three-input NOR/OR gate of the first described first three-input NOR/OR gate. Three input terminals, the gate of the fifty-first MOS transistor is the third inverting input terminal of the first three-input NOR/OR gate, the source of the forty-eighth MOS transistor, the The source of the forty-ninth MOS transistor is connected to the drain of the fifty-first MOS transistor, the source of the fiftieth MOS transistor, the source of the fifty-first MOS transistor connected to the drain of the fifty-second MOS transistor, and the source of the fifty-second MOS transistor is grounded; the structure of the second three-input NOR/OR gate and the first three The input NOR/OR gates are the same.