CN106534613A - High-capacity onboard video collection system - Google Patents

Abstract

The invention discloses a high-capacity onboard video collection system. The system is applied to related experiments of a television guided weapon. Video data is collected, and follow-up analysis improvement is carried out. According to the system, TMS320DM368 of DaVinci series of the TI Company is taken as a core processor, and 64-G MTFC64GJDDN-4M IT of the Micron Company is mounted on the core processor to form a video collection and storage system. According to the system, PAL system video analog signals are collected through a video sensor; AD conversion of the analog video signals is realized through a video decoding chip TVP5146; processing such as compression is carried out on the converted digital video signals through DM368; and finally the compressed and coded video data is stored in a storage chip. According to the system, the video data also can be read from the storage chip, and functions such as analyzing and processing the digital video signals and outputting and playing back the analog video signals can be realized. According to the system, the complicated and efficient video coding and decoding processing is realized through the DM368, and the great deal of work required for realizing coding, decoding and compression algorithms is avoided. A high-capacity eMMC (Embedded Multi Media Card) is mounted for storage, so the high-capacity storage capable of being realized in an onboard environment is solved.

Description

A kind of Large Copacity missile-borne video acquisition system

Technical field

The present invention relates to video acquisition field, specifically a kind of using TMS320DM368 as core processor, the MTFC64GJDDN-4M IT for carrying company of Micron Technology 64GB constitute the implementation method of video acquisition storage system.

Background technology

With the fast development of video technique, the application of video is gradually promoted in every field.In military field, video technique is applied to unmanned plane, aviation investigation, television weapon etc..TV guidance is the naturally visible optical information using target reflection, carries out the aiming means for capturing, position, follow the trail of and guiding to target.China's TV guidance technique is just belonging to developmental stage, also there are many deficiencies, needs constantly experiment to be optimized.And in experimentation, needing a Large Copacity missile-borne video acquisition system to deposit video data to gather, the analysis after convenient test is improved.

Innovation and the requirements at the higher level to video along with sensor devices, the data volume of video signal constantly increase, and are to alleviate video storage and the pressure of transmission, need to carry out which necessary compression process.Video processing schemes common at present are mainly DSP and carry FPGA or arm processor, but this scheme needs self-developing Video processing and encoding and decoding algorithm, and the cooperation difficulty between different processor is larger.This results in system stability and hardly results in guarantee, and development difficulty is larger, and the construction cycle is longer.In view of the high overload environment of missile-borne, the memory device of plug-in cannot be used, such as SD card, and the current monolithic capacity of NAND Flash is limited, it is difficult to accomplish massive store, it is therefore desirable to carry out special scheme for the video acquisition system under missile-borne environment and select design.

The content of the invention

It is an object of the invention to provide a kind of system for realizing Large Copacity missile-borne video acquisition.

The technical solution for realizing the object of the invention is：A kind of Large Copacity missile-borne video acquisition system, including video acquisition module（1）, DM368 core processing module（2）, Video Output Modules（3）、DDR（9）With NAND Flash（10）；Video acquisition module（1）By video sensor（4）The analog video data Jing video decoding chip TVP5146 of collection（5）Analog digital conversion is carried out, the digital video signal after conversion passes through image sensor interface ISIF（6）Into DM368 core processing module（2）Video processing subsystem（19）, and by coprocessor（18）Encoding video signal compression is processed；Finally the digital video signal after compression coding can be stored in eMMC (Embedded Multi Media Card)（16）, or by conformable display in the form of analog video signal（17）Output display.

Video acquisition module（1）Including video sensor（4）With video decoding chip TVP5146（5）.Video sensor（4）Collection signal be analog video signal, decoding chip TVP5146（5）The AD conversions of analog video signal are realized, YCbCr422 after conversion, is exported The digital signal of form is linked into ISIF（6）；TVP5146（5）Mode of operation by DM368 core processing module（2）Peripheral Interface（14）In I2C interfaces configured；DM368 core processing module（2）Can support that the digital signal of 8/16bit is input into, and TVP5146（5）Output accuracy be 10/20bit, this place intercepting TVP5146（5）Per group output high 8bit.

3DM368 core processing module（2）Including ISIF（6）、JATG（7）, DDR interfaces（8）、AEMIF（External memory interface）（11）, analog video output（12）、SDIO（Secure digital input-output card）（13）And Peripheral Interface（14）；ISIF（6）Digital video signal input interface, JATG are provided（7）For emulation interface, DDR interfaces（8）For connecting DDR（9）Operation application program, AEMIF（11）Connection NAND Flash（10）For loading system startup program, analog video output（12）For exporting analog video signal, SDIO（13）Connection eMMC（16）Realize that encoded video data is stored, Peripheral Interface（14）Various Peripheral Interfaces are provided.

Video Output Modules（3）Including eMMC（16）Storage and conformable display（17）.eMMC（16）Video data after real-time storage compression coding, and can be from eMMC（16）Middle reading number video data, Jing after digital-to-analogue conversion, by conformable display（17）Shown；Or the digital of digital video data after coding is directly read, for post analysis process, carry out experiment improvement.

DM368 core processing module（2）Collection video data is carried out into encoding and decoding process, and is exported on demand or is stored；DM368 core processing module（2）In video processing subsystem（VPSS）（19）, it passes through Video processing front end receiver decoding chip TVP5146（5）Video data after analog digital conversion, and conformable display is connected by Video processing rear end（17）Carry out video data to show；DM368 core processing module（2）In coprocessor（18）By video processing subsystem（VPSS）（19）The digital of digital video data of reception carries out encoding and decoding process, and the data after compression coding are stored in eMMC（16）.

Missile-borne limited space, video acquisition system size need to be less than 85mm × 70mm.

Compared with prior art, its remarkable advantage is the present invention：1st, from DM368, the present invention is by realizing that complicated efficient coding and decoding video is processed, it is to avoid realize the extensive work needed for codec compression algorithm；2nd, stored by carrying jumbo eMMC, solved attainable massive store under missile-borne environment；3rd, by the selection of this scheme, system dimension is effectively controlled, the good dimensional requirement adapted under missile-borne environment.

Description of the drawings

Fig. 1 is the general structure schematic diagram of the present invention.

Fig. 2 is DM368 system architecture diagrams of the present invention.

Fig. 3 is that video acquisition drives flow chart.

Fig. 4 is Video coding flow process map flow chart.

Fig. 5 is the Linux storage system models based on eMMC.

Fig. 6 is eMMC card initialization flow charts.

Specific embodiment

From TI companies DaVinci serial TMS320DM368 as core processor, the MTFC64GJDDN-4M IT for carrying company of Micron Technology 64GB constitute video acquisition storage system to the present invention.System gathers pal mode video analog signal by video sensor, Jing video decoding chip TVP5146 realize the AD conversions and decoding of analog video signal, digital video signal after conversion enters compression etc. by DM368 and processes, and most the video data at last after compressed encoding is stored in storage chip.Equally, system can read video data, be capable of achieving the function such as digital video signal analyzing and processing and analog video signal output playback.From DM368, the present invention is by realizing that complicated efficient coding and decoding video is processed, it is to avoid realize the extensive work needed for codec compression algorithm；By carrying jumbo eMMC (Embedded Multi Media Card) stored, solve attainable massive store under missile-borne environment.

Above-mentioned TMS320DM368 is a high performance chipses towards multimedia technology application, powerful and price is low.TMS320DM368 is integrated with ARM926EJ-S kernels, two image associations and processes engine (HDVICP and MJCP), image processing subsystem (VPSS).DM368 frequencies are up to 432MH, support multi-format decoding, multi tate and high definition multi-channel function, highest can support that H. 264 encodes the speed of 1080p 30 frames of form/s, and may also provide various free-standing audio frequency, voice and HD video codec (H. 264, MPEG 4, VC1/WMV9 etc.).The processor peripheral interface includes memory expansion interface EMIFs MMC/SD/SDIO interfaces, Watch Dog Timer, SPI interfaces, master/slave I2C bus control units, 2.0 OTG interface controllers of USB etc..System operation is increased income in Linux embedded OSs, Linux systems, stable performance safety.

Above-mentioned TVP5146 chips are the decoding digital video chips of a specialty, can be digitally converted analog video signal.NTSC, PAL, SECAM video signal can be converted into digital component video signal by it, it is adaptable to portable, high-quality and high performance video product.TVP5146 not only supports the digitized of CVBS signals and Y/C signals, also supports the analog digital conversion to analog rgb signal and YPbPr input signals.The analog digital conversion passage of 10 precision is up to inside it containing 4 tunnels, each paths all contain and borrow circuit and programmable gain and off-centre circuit.Various analog video signals can be sampled by 2 times of pixel frequency or ITU-R BT.601 standard frequencies, then are reduced to pixel rate-adaptive pacemaker through subtracting frequency filtering.For the decoding of CVBS signals, 5 line auto-adaptive comb filters of the chip using inside（adaptive comb filter）To carry out YC separation, brightness and the crosstalk of colourity can be so effectively reduced, there is provided optimal YC separation effect.For the input of CVBS and S-video, user can also be by the contrast of 12C Interface Controller video signals, brightness and saturation.

Above-mentioned eMMC is the abbreviation of embedded Multimedia Card, MMC/eMMC is a kind of lower-cost data storage for commonly using and communications media, its use range covers large-area portable type electronic product, such as HPC, digital camera, smart mobile phone etc., the unified feature of these equipment is exactly high fluidity, high-performance, relatively low cost, the low-power consumption of memory card interface and high data throughput.EMMC is the embedded memory standard specificationss ordered by MMC associations, is primarily directed to based on mobile phone productses.It is a kind of NAND chip based on MMC standards, and obtain solid state technology association criterion, it is stipulated that electrical equipment, encapsulation and size etc..Its technical characterstic is similar with LBANAND, that is, employ the framework of " controller+NAND ".The eMMC equipment that the system is selected is Micron Technology's board, and its memory capacity is 64GB.

Below in conjunction with the accompanying drawings the present invention is described in further detail.

With reference to Fig. 1 and Fig. 2, system includes video acquisition module, DM368 core processing module and Video Output Modules.Video acquisition module includes video sensor and video decoding chip TVP5146.Video sensor gathers signal for analog video signal, and decoding chip TVP5146 realizes the AD conversions and decoding of analog video signal, output YCbCr422 The digital signal of form is linked into ISIF.The mode of operation of TVP5146 is configured by the I2C interfaces in Peripheral Interface.DM368 core processing module can support that the digital signal of 8/16bit is input into, and the output accuracy of TVP5146 is 10/20bit, and this place intercepts the high 8bit of per group of output of TVP5146.DM368 core processing module includes：ISIF, JATG, DDR interface, AEMIF, analog video output, SDIO and Peripheral Interface.ISIF is digital video input interface, and JATG is emulation interface, DDR Interface is used for connecting DDR operation programs, AEMIF connection NAND Flash is used for loading startup program, and analog video is exported for exporting analog video signal, and SDIO connection eMMC realize that encoded video data is stored, and Peripheral Interface provides various Peripheral Interfaces.Video Output Modules include that eMMC storages and conformable display show.Video data after eMMC real-time storage coding, and analog video signal can be read and be converted into, shown by conformable display.Or the video data after coding is directly read, for post analysis process, carry out experiment improvement.

The system module related to video is mainly VPSS, and by taking video acquisition as an example, specific driver includes Video processing front end（VPFE）Driver and video capture processor TVP5146 drivers.TVP5146 needs to VPFE to register as sub- equipment, and VPFE provides whole device file handling function interfaces upwards, and defers to V4L2 (Video For Linux 2) standards.Final application program only needs to call VPFE to drive the application interface for meeting V4L2 standards for providing, and then the various functions function provided in recalling TVP5146 drivers can just realize corresponding video processing function.Video acquisition drives block diagram as shown in Figure 3.

V4L2 is developed on V4L, the routine interface being specific to designed by Linux Video Captures.V4L2 is refined as double-deck driving in inner nuclear layer.The double-deck top layer for driving is V4L2dev equipment, and in kernel file V4L2_dev.c, major function is to provide loading and unloading function to kernel and provide interactive interface to Virtual File System to the device definition.Operation of the user to device file is converted into specific equipment operation by interactions of the V4L2 by Virtual File System, and it includes the normalizing operations such as hardware detecting, initialization, equipment read-write and equipment control.

The double-deck bottom layer drivings for driving of V4L2 are VPFE device drives, are defined within kernel file vpfe_capture.c as a videodev equipment, and major function is to realize the detection of hardware and remove.Specific works are completed by hardware detecting function probe (), and when registration loading is driven, detection VPFE equipment whether there is, and register to V4L2 layers if existing.Simultaneously the sub- equipment of V4L2 is inquired about, the configuration interface I2C of the video decoding chip TVP5146 that the system is selected is exactly the sub- equipment of common V4L2.TVP5146 is considered the sub- equipment of I2C, and its driver also belongs to the double-deck bottoms for driving of V4L2, is specifically defined in kernel file tvp514x.c, called by V4L2_subdev_ops and realize that video acquisition works.

TI provides xDAIS and xDM software frames for Leonardo da Vinci's series, it is achieved thereby that the skeletonisation and modularity of software development, increased development efficiency.Software frame is divided into application layer, three part of signal processing layer and I/O layers, can develop oneself various algorithms and application program according to this rule user.By taking the system as an example, signal processing layer operates in DM368 coprocessors side, the encoding and decoding algorithm of main responsible audio frequency and video, Codec Engine and ARM communication modules etc..I/O layers are the respective driver for DM368 peripheral modules.Application layer passes through Codec The Video API of Engine realize the various functions of Video processing calling the algorithm of coprocessor side.

The realization of coding and decoding video particularly may be divided into three steps：The * .cfg files of engine configuration are initially set up, encoding and decoding engine is defined；Secondly API Function in the application, opens engine and simultaneously creates encoding and decoding example；Configuration file makefile is finally compiled, and then compiles generation application program.Engine file mainly includes Engine Name, codec names and other modules.After the completion of configuration, encoding and decoding algorithm handle just can be created in the application and calls algorithms library.Equally by taking coding as an example, specific coding flow chart is as shown in Figure 4.CE (Codec Engine) is initialized first, coding engine is opened, encryption algorithm handle is then created, algorithm controls function is then passed through and is realized specific coding with algorithm process function, delete encryption algorithm handle, and close coding engine after being finished.Decoding process is similar with coding, and respective function is respectively VIDDEC2_creat, VIDDEC2_control, VIDDEC2_process and VIDDEC2_delete.

The system using storage device be eMMC, operating system is the embedded system based on Linux, eMMC is realized in the form of block device in Linux, and the Embedded Memory System based on eMMC memorizeies is mainly made up of client layer, inner nuclear layer, three part of hardware layer.Fig. 5 is an Embedded Memory System model based on eMMC equipment.Client layer is the application program that we use at ordinary times, and it is responsible for directly contacting with user, the actual read-write requests order of receive user or application program.Inner nuclear layer is mainly made up of three parts：Virtual File System, actual file system and Block Device Driver.The groundwork of this layer is exactly the order of transmitting client layer and data through encapsulation, then by send it is corresponding order, the request of user is passed to into device controller.Unified block device interface is realized in block device driver, and the work for mainly completing is to register block device to kernel, and INIT block equipment, definition block equipment operation function process request etc..Hardware layer is made up of eMMC controller and storage chip, and control unit interface is SDHCI (Secure Digital Host Controller Interface), eMMC equipment is Micron Technology's board its memory capacity is 64GB.

After system electrification, in order to store video data in time, eMMC needs to start a series of services, then initialization apparatus, and idiographic flow is as shown in Figure 6.After equipment initialization is completed, the read-write length of the data block of operating system nucleus acquiescence is 512 bytes, generally system carries out the read-write operation to eMMC equipment in units of 512 bytes, if other needs, the reading length of data block can also be set by sending order CMD16, the value can be configured so that the arbitrary value between 1-512 bytes.But block length is necessary for 512 bytes then to be required to the process of writing of eMMC equipment, because 512 bytes are the sizes of one sector of block device.When operation is written and read to block device eMMC use absolute address, i.e. from 32 bit address of 0 open numbering, it is written and read used here as block number, block number is from 0 open numbering, and the size per block is a sector (i.e. 512 bytes), therefore start all sector number must be converted into absolute address.Read-write to equipment is divided into two kinds of monolithic pattern and polylith pattern.Read-write is all the integral multiple of block size every time.These data all can be at end with _ CRC check code, and when verification failure, the data of transmission can be dropped, data read-write operation can also be aborted.

The read operation of data in eMMC equipment, is that, after device controller receives the data block that upper strata hands down, controller first sends order CMD17 to eMMC first, after eMMC receives command signal, returns effective response signal to controller, then start receiving data.

Data to be sent to eMMC, the order CMD24 for writing is sent to eMMC by device controller first, after controller receives the effective response signal ox00 of eMMC equipment return, start to transmit data by bus.

The basic erasure unit of block device is named as wiping unit, and eMMC equipment is no exception, and erasing unit is made up of one or several continuous erasing blocks, wipes the least unit that block is that eMMC equipment performs erasing operation, and erasing unit is made up of four parts：One is erasing unit header：It is typically placed at the beginning location of erasing unit, contain the control information related to erasing unit, two is block allocation table and block distribution information, allocation table has reacted the type of the logical address and data block of read-write data block, and block allocation table refers to that the block of all read-write blocks of each erasing unit distributes information with the Storage Format of one-dimension array.Three is check information, and the design parameter of check information is indicated by flag bit.Four is data block, and data block is for data storage and relevant information.

Erasing operation first has to judge whether input data legal, initial address must alignment module border, and the column address of initial address is 0, because erasing operation must be in units of block.Then row address is obtained, judges whether write-protect, carry out erasing order.Often wipe one piece to judge whether to successfully complete by read states information.Then increase page address, and the page address value of each increase of erasing order unlike read write command is the number of one piece of page for being included, and next piece is then wiped until completing.

After realizing above-mentioned video acquisition module function, DM368 core processing module function and eMMC store functions, the allomeric function of Large Copacity missile-borne video acquisition system is just capable of achieving.The system has abundant video interface, and applicable different video acquisition needs.DM368 possesses various video encoding and decoding algorithm, and stable performance, small volume are adaptable in various working environments.Using eMMC storage chips, capacity is expansible, and operation is intelligent.The Large Copacity missile-borne video acquisition system of function admirable is realized finally.

Claims (6)

1. a kind of Large Copacity missile-borne video acquisition system, it is characterised in that：Including video acquisition module（1）, DM368 core processing module（2）, Video Output Modules（3）、DDR（9）With NAND Flash（10）；Video acquisition module（1）Including video sensor（4）With video decoding chip TVP5146（5）, video acquisition module（1）By video sensor（4）The analog video data Jing video decoding chip TVP5146 of collection（5）Analog digital conversion is carried out, the digital video signal after conversion passes through image sensor interface ISIF（6）Into DM368 core processing module（2）Video processing subsystem（19）, and by coprocessor（18）Encoding video signal compression is processed；Digital video signal most at last after compression coding is stored in eMMC (Embedded Multi Media Card)（16）, or by conformable display in the form of analog video signal（17）Output display, DM368 core processing module（2）In DDR interfaces（8）For connecting DDR（9）Operation application program, AEMIF（11）Connection NAND Flash（10）For loading system startup program.

2. Large Copacity missile-borne video acquisition system according to claim 1, it is characterised in that：The video sensor（4）Collection signal be analog video signal, decoding chip TVP5146（5）Realize the AD of analog video signal Conversion, the digital signal for exporting YCbCr422 forms after conversion are linked into ISIF（6）；TVP5146（5）Mode of operation by DM368 core processing module（2）Peripheral Interface（14）In I2C interfaces configured；DM368 core processing module（2）Can support that the digital signal of 8/16bit is input into, TVP5146（5）Output accuracy be 10/20bit, this place intercepting TVP5146（5）Per group output high 8bit.

3. Large Copacity missile-borne video acquisition system according to claim 1, it is characterised in that：DM368 core processing module（2）Collection video data is carried out into encoding and decoding process, and is exported on demand or is stored；DM368 core processing module（2）In video processing subsystem VPSS（19）, it passes through Video processing front end receiver decoding chip TVP5146（5）Video data after analog digital conversion, and conformable display is connected by Video processing rear end（17）Carry out video data to show；DM368 core processing module（2）In coprocessor（18）By video processing subsystem VPSS（19）The digital of digital video data of reception carries out encoding and decoding process, and the data after compression coding are stored in eMMC（16）.

4. Large Copacity missile-borne video acquisition system according to claim 1, it is characterised in that：The DM368 core processing module（2）Including ISIF（6）、JATG（7）, DDR interfaces（8）, external memory interface AEMIF（11）, analog video output（12）, secure digital input-output card SDIO（13）And Peripheral Interface（14）；ISIF（6）Digital video signal input interface, JATG are provided（7）For emulation interface, analog video output（12）For exporting analog video signal, SDIO（13）Connection eMMC（16）Realize that encoded video data is stored, Peripheral Interface（14）Various Peripheral Interface connection ancillary equipment are provided（15）.

5. Large Copacity missile-borne video acquisition system according to claim 1, it is characterised in that：Video Output Modules（3）Including eMMC（16）Storage and conformable display（17）；eMMC（16）Video data after real-time storage compression coding, and can be from eMMC（16）Middle reading number video data, Jing after digital-to-analogue conversion, by conformable display（17）Shown；Or the digital of digital video data after coding is directly read, for post analysis process, carry out experiment improvement.

6. a kind of Large Copacity missile-borne video acquisition system, it is characterised in that：The video acquisition system size is less than 85mm × 70mm.