CN106533646A - Clock Data Recovery System in Sequencer/Deserializer - Google Patents
Clock Data Recovery System in Sequencer/Deserializer Download PDFInfo
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- CN106533646A CN106533646A CN201510569933.7A CN201510569933A CN106533646A CN 106533646 A CN106533646 A CN 106533646A CN 201510569933 A CN201510569933 A CN 201510569933A CN 106533646 A CN106533646 A CN 106533646A
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Abstract
A clock data recovery system in a sequencer/deserializer. The clock data recovery system includes: a continuous time linear equalizer generating a first equalized signal; a summer for superimposing the first equalized signal and the feedback equalized signal and generating a superimposed signal; a first error slicer for slicing the superimposed signal according to the clock signal and a first slicing voltage and generating a first error signal; a second error slicer for slicing the superimposed signal according to the clock signal and a second slicing voltage and generating a second error signal; a data slicer for slicing the superimposed signal according to the clock signal and a third slicing voltage and generating a data signal; the clock data recovery circuit generates the clock signal; the adaptive filter receives the data signal and the first error signal and generates a reference voltage and decision feedback equalization coefficient set according to the data signal and the first error signal; and a decision feedback equalizer for receiving the data signal and the decision feedback equalization coefficient set and generating the feedback equalization signal.
Description
Technical field
The present invention relates in a kind of serial device/solution sequence device (Serializer/Deserializer, abbreviation Serdes)
Circuit, and the clock data recovery system in more particularly to a kind of serial device/solution sequence device (Serdes).
Background technology
Electronic circuit (such as chip, crystal grain, integrated circuit etc.) is the most important hardware of advanced information society
Basis；Different electronic circuit available channels (channel) connect into interconnection system, to hand over via passage
Signal (such as information, data, message, order and/or packet etc.) is changed, different electronic circuit energy are allowed
Mutually coordinated running, plays the comprehensive function of addition.But, the characteristic of passage itself can also affect signal
The quality of contact transmission.In general, passage is low-pass nature, therefore the radio-frequency head in suppression signal can be subtracted
Point, cause distorted signals (distortion)；For example, when an electronic circuit as transmitting terminal will
During via passage by the electronic circuit of the signal transmission of a square-wave waveform a to receiving terminal, receiving terminal is received
Signal waveform can be a slow waveform for rising slow drop, be unable to maintain that the liter of square-wave waveform along and drop edge.
In the signal waveform that receiving terminal is received, its slow liter part can be considered one before vernier (pre-cursor), its
The slow peak value for rising can be considered a main cursor, and vernier after the part for delaying drop by peak value then can be considered
(post-cursor).Distorted signals can further result in interference (ISI, inter-symbol between symbol
Interference), the quality of signal transmission is affected, for example, says it is to improve bit error rate.
In order to compensate the impact that passage is caused, can be respectively provided with transmitting terminal and receiving terminal filtering mechanism with
Equilibrating mechanism.For example, the filtering mechanism of transmitting terminal (transmitter, abbreviation Tx) may include that one is pre- strong
Change wave filter (pre-emphasis filter) to strengthen the HFS of transmitting end signal；Receiving terminal
The equilibrating mechanism of (receiver, abbreviation Rx) then may include a continuous time linear equalizer (continuous
Time linear equalizer, abbreviation CTLE) and a decision feedback equalizer (decision feedback
Equalizer, abbreviation DFE).When a signal to be passed is sent to receiving terminal by transmitting terminal, transmitting terminal filter
Ripple device can be filtered for signal to be passed according to multiple filter factors, then filtered signal is driven to logical
Road；After the signal that receiving terminal receiving channel is transmitted, the signal for receiving can be entered according to multiple equalizing coefficients
Row equilibrium treatment, then by taking the content and/or other information that also which carries in signal after equalization (such as clock).
Fig. 1 is refer to, it is known array device/solution sequence device (Serdes) schematic diagram which is depicted.In transmitting terminal
In the electronic circuit of Tx, strengthen wave filter (pre-emphasis filter) 102 receiving data signal (data in advance
Signal) S produce data signal Sw of filtration.Wherein, pre- reinforcing wave filter 102 improves data signal
The size (increase the magnitude of higher frequencies) of the HFS in S and became
Data signal Sw of filter.
Afterwards, data signal Sw of filtration be sent to the other end via one end of passage (channel) 104 and
Become the electronic circuit for receiving signal Sx and being input into receiving terminal Rx.In the electronic circuit of receiving terminal Rx
In, including clock data recovery system (clock data recovering system) 110, to rebuild data
Signal S.
Clock data recovery system 110 includes：Data sampler (data sampler) 113, edge sampler
(edge sampler) 115, clock data recovery circuit (clock data recovering circuit) 117, decision-making
Feedback equalizer (decision feedback equalizer) 119 and summer (adder) 111.
Substantially, the reception signal Sx on the other end of passage 104 can input clock data recovery system
110.Feedback equalization signal (the feedback that decision feedback equalizer 119 is produced by summer 111
Equalizing signal) Sf with receive signal Sx added up after produce superposition signal (superposed
signal)Sz。
Data sampler 113 is sampled according to data clock dCLK and superposition signal Sz produces data sampling
Signal (sampled data signal) Sd.Furthermore, edge sampler 115 is adopted according to edge clock eCLK
Sample superposition signal Sz simultaneously produces edge sampled signal (sampled edged signal) Sedg.
In addition, clock data recovery circuit 117 receives sampled data signal Sd and edge sampled signal
Sedg simultaneously produces data clock dCLK and edge clock eCLK.Decision feedback equalizer 119 is received
Sampled data signal Sd simultaneously produces feedback equalization signal Sf.
Substantially, the clock data recovery system 110 of Fig. 1 is to carry out data and its number to superposition signal Sz
According to the sampling along (data edge), and using clock data recovery circuit 117 producing data clock dCLK
And edge clock eCLK.Such clock data recovery system 110, its clock data recovery circuit 117
Need to produce the data clock dCLK and edge clock eCLK of double data rate, to excessively sampling
(over sampling) superposition signal Sz.Furthermore, data clock dCLK and edge clock eCLK are each other
Between phase contrast be 180 degree.
Explanation according to more than, needs in clock data recovery circuit 117 using spring spring phase detectors
(bang-bang phase detector), for receiving data sampled signal Sd and edge sampled signal
Sedg, and phase place fresh information (phase update information) is produced according to this to adjust data clock
The phase place of dCLK and edge clock eCLK.
, it is clear that known array device/solution sequence device is not particularly suited for the data transmission system of high speed.Citing
For, it is assumed that when the data rate of data signal S is 16Gbps, clock data recovery circuit 117 needs
Generation is up to what the data clock dCLK and edge clock eCLK of 8GHz speed was sampled with positive negative edge
Mode could obtain the information of clock phase difference, and then rebuild data signal S.
The content of the invention
An object of the present invention is to propose a kind of clock data recovery system, including：One consecutive hours top-stitching
Property equalizer, receives signal and produces one first equalizing signal；One summer, receive this first
Equalizing signal and a feedback equalization signal, and produce a superposition signal；One first error sickle, according to
One clock signal and one first killer voltage are cutting the superposition signal and produce one first error signal；
One second error sickle, cuts the superposition signal according to the clock signal and one second killer voltage
And produce one second error signal；One data slicer, according to the clock signal and one the 3rd cutting electricity
Press to cut the superposition signal and produce a data signal；One clock data recovery circuit, receives the data
Signal and second error signal, and the clock signal is produced according to this to the data slicer, first mistake
Difference sickle and the second error sickle；One adaptive filter, receive the data signal with this first
Error signal, and a reference voltage is produced according to this to the first error sickle, and it is anti-to produce a decision-making
Feedback equalizing coefficient group, the wherein reference voltage are equal to first killer voltage；And a decision feedback equalization
Device, receives the data signal and the decision feedback equalization coefficient sets, and produces the feedback equalization signal according to this
To the summer.
More preferably understand to have to the above-mentioned and other aspect of the present invention, preferred embodiment cited below particularly,
And coordinate accompanying drawing, it is described in detail below.
Description of the drawings
It is known array device/solution sequence device (Serdes) schematic diagram that Fig. 1 is depicted.
Impact of the passage of interconnection system to signal transmission is illustrated in Fig. 2 citings.
Fig. 3 citings are illustrated to disturb between symbol.
Fig. 4 is shown to the schematic diagram for answering 1 symbol of a logic.
The clock data recovery of the depicted serial device/solution sequence devices for first embodiment of the invention of Fig. 5 A
System schematic diagram.
The depicted coupling effects (coupling effect) between signal in first embodiment of Fig. 5 B are illustrated
Figure.
The clock data recovery of the depicted serial device/solution sequence devices for second embodiment of the invention of Fig. 6 A
System schematic diagram.
The depicted uncoupling effects (decoupling effect) between signal in second embodiment of Fig. 6 B are shown
It is intended to.
【Symbol description】
102：Pre- reinforcing wave filter
104：Passage
110：Clock data recovery system
111：Summer
113：Data sampler
115：Edge sampler
117：Clock data recovery circuit
119：Decision feedback equalizer
204：Passage
500、600：Clock data recovery system
510、610：Continuous time linear equalizer
520、620：Summer
530、630：Data slicer
540、640、645：Error sickle
550、650：Clock data recovery circuit
560、660：Adaptive filter
570、670：Decision feedback equalizer
Specific embodiment
Fig. 2 is refer to, its citing impact of schematic channel to signal transmission.In fig. 2, a transmitting terminal
Mono- passages 204 of Tx Jing and be connected to a receiving terminal Rx, when transmitting terminal Tx to send a filtration data letter
When number Sw is to receiving terminal, data signal Sw of filtration can form reception letter via the propagation of passage 204
Number Sx, is received by receiving terminal Rx.In the example in figure 2, data signal Sw of filtration is in time point t0
One 1 symbol of logic is carried with the square wave for continuing a period UI.Due to waveform caused by passage 204
Distortion, the square wave in data signal Sw of filtration can be presented a slow ripple for rising slow drop in signal Sx is received
Shape.Received end Rx docks the sampling of collection of letters Sx, and 1 symbol of logic can be corresponded to the peak of time point t [k0]
Value sampling Sx [k0], forms main cursor.Relative to main cursor, signal Sx is before time point t [k0] for reception
Part be front vernier, the sampling Sx [k0-1] of such as time point t [k0-1]；Signal Sy is after time point t [k0]
Part be rear vernier, the sampling Sx [k0+1] of such as time point t [k0+1].Time point t [k0-1], t [k0] and t [k0+1]
Between interval can be equal to period UI.
Ideally, front vernier should be zero with the intensity of rear vernier, leave behind main cursor.No
Cross, the front trip of suitable intensity because non-ideal effects caused by channel characteristic, in receiving signal Sx, can be left
Mark and rear vernier, and cause interference between symbol.
Continue Fig. 2, please continue to refer to Fig. 3, its citing is illustrated to disturb between symbol.In the example in figure 3,
Data signal Sw of filtration carries three symbols between time point t0 to t3, is sequentially logic 1,0 and 1.
Via the transmission of passage 204,1 square wave of logic between time point t0 to t1 can form waveform in receiving terminal Rx
Wa, 1 square wave of logic between time point t2 to t3 then form waveform Wb, and receiving terminal Rx in receiving terminal Rx
Reception signal Sx be to be synthesized by waveform Wa and Wb, logic 1 in data signal Sw of filtration,
0 with sampling Sx [k0], the Sx [k0+1] in 1 respectively corresponding reception signal Sx and Sx [k0+2].
As seen from Figure 3, because the rear vernier of waveform Wa (part after time point t [k0]) and waveform Wb
Front vernier (part before time point t [k0+2]) can in time point t [k0+1] addition, therefore sampling Sx [k0+1]
Intensity will not drop to zero, make the sampling Sx [k0+1] that originally should represent logical zero can be because disturbing between symbol
And it is mistaken for logic 1.From the discussion of Fig. 2 and Fig. 3, in order to compensate the characteristic of passage and subtract suppression
Disturb between symbol, it should will completely consider the impact of front vernier and rear vernier.
Substantially, the decision feedback equalizer in clock data recovery system is by after receiving and reducing in signal Sx
The impact of vernier and form superposition signal Sz；The effect of this equilibrating mechanism can be illustrated with Fig. 4.Such as
Shown in Fig. 4, to 1 symbol of a logic is answered, reception signal Sx can be presented slow a liter and delay drop waveform, in superposition
Sampling Sz [k] the reflection logics 1 of signal Sz, but still there is suitable signal intensity vernier part thereafter.But,
After decision feedback equalizer, the rear vernier part received in signal Sx can be supported by feedback equalization signal
Subtract, make the corresponding sampling Sz [k+1] in rear vernier part, Sz [k+2] etc. level off to zero, to suppress symbol
Between disturb.
Furthermore, in order to reduce the rear vernier part received in signal Sx, decision feedback equalizer needs basis
Decision feedback equalization coefficient sets (DFE coefficient set) h1, the change of h2, h3, h4, h5 are anti-to produce
Feedback equalizing signal.As shown in figure 4, because superposition signal Sz is more than time point t [k+2] in the intensity of time point t [k+1]
Intensity, therefore coefficient h 1 also be more than coefficient h 2.
Fig. 5 A are refer to, the clock of its depicted serial device/solution sequence device for first embodiment of the invention
Data recovery system schematic diagram.Clock data recovery system 500 includes：Continuous time linear equalizer 510,
Data slicer (data slicer) 530, error sickle (error slicer) 540, clock data recovery circuit
550th, adaptive filter (adaptive filter) 560, decision feedback equalizer 570 and summer 520.
Wherein, adaptive filter 560 may be based on an adaptive filter (the least mean of lowest mean square
square based adaptive filter)。
As shown in Figure 5A, the other end in passage 204 is connected to the electronic circuit of receiving terminal Rx so that
The continuous time linear equalizer 510 of signal Sx input clocks data recovery system 500 is received, to carry
Height receives the size of the HFS in signal Sx and becomes the first equalizing signal (first equalized
signal)Sy.Furthermore, the feedback equalization signal Sf that decision feedback equalizer 570 is produced by summer 520
Superposition signal Sz is produced after being added up with the first equalizing signal Sy.
Data slicer 530 is according to clock signal clk and fixes killer voltage (slicing voltage) Ss,
Such as 0V, cuts (slice) superposition signal Sz and produces data signal Sd.Furthermore, error sickle
540 according to clock signal clk and reference voltage (reference voltage) Vref, cuts (slice) repeatedly
Plus signal Sz simultaneously produces error signal Serr.
550 receiving data signal Sd of clock data recovery circuit produces clock letter with error signal Serr
Number CLK is to data slicer 530 and error sickle 540.Furthermore, adaptive filter 560 is received
Data signal Sd produces a reference voltage Vref to error sickle 540 with error signal Serr, and
And decision feedback equalization coefficient sets (DFE coefficient set) h1, h2, h3, h4 is produced, h5 is to decision-making
Feedback equalizer 570.
Furthermore, 570 receiving data signal Sd of decision feedback equalizer and decision feedback equalization coefficient sets h1,
Feedback equalization signal Sf is produced after h2, h3, h4, h5 to summer 520, to reduce the first balanced letter
Rear vernier part in number Sy.Substantially, signal Sf is balanced with first for superposition signal Sz, feedback equalization
Relation between signal Sy is：
Substantially, the clock data recovery system 500 of Fig. 5 A is using identical clock signal clk pair
Superposition signal Sz carries out the sampling of data and phase error.Such clock data recovery system 500, its
The clock signal that clock data recovery circuit 550 is produced is identical with data rate.Therefore, data recovery system
System 500 can be referred to as Bao rate data recovery system (baud rate clock data recovering system).Again
Person, also includes in clock data recovery circuit 550 that mesh is strangled mesh and strangles phase detectors (Muler-Muler phase
Detector) come receiving data signal Sd and error signal Serr, and produce phase place fresh information according to this
(phase update information), to adjust the phase place of clock signal clk.
Fig. 5 B are refer to, its depicted coupling effect (coupling between signal in first embodiment
Effect) schematic diagram.As shown in Figure 5 B, before dotted line I is not input into superposer 520 for feedback equalization signal Sf
Superposition signal Sz；Solid line II is the superposition signal Sz after feedback equalization signal Sf is input into superposer 520.
Before feedback equalization signal Sf is not input into superposer 520, superposition signal Sz becomes dotted line I.Now,
Error signal Serr can be in 1 transition of phase place ψ, and the sampling phase (sampled phase) of clock signal clk
1 position of phase place ψ can be locked.However, after feedback equalization signal Sf is input into superposer 520, superposition
Signal Sz becomes solid line II.Error signal Serr can be in 2 transition of phase place ψ, and clock signal clk is adopted
Sample phase place (sampled phase) can be locked 2 position of phase place ψ.That is, locking phase produces the meeting of Δ ψ
Skew.In other words, coupling effect can be produced between the first equalizing signal Sy and feedback equalization signal Sf,
And the phase place of clock signal clk can be affected so that system is unstable by feedback equalization signal Sf.
Fig. 6 A are refer to, the clock of its depicted serial device/solution sequence device for second embodiment of the invention
Data recovery system schematic diagram.Clock data recovery system 600 includes：Continuous time linear equalizer 610,
Data slicer 630, the first error sickle 640, the second error sickle 645, clock and data recovery
Circuit 650, adaptive filter 660, decision feedback equalizer 670 and summer 620.Wherein, fit
Answering property wave filter 660 may be based on an adaptive filter (the least mean square based of lowest mean square
adaptive filter)。
As shown in Figure 6A, the other end in passage 204 is connected to the electronic circuit of receiving terminal Rx so that
The continuous time linear equalizer 610 of signal Sx input clocks data recovery system 600 is received, to carry
Height receives the size of the HFS in signal Sx and becomes the first equalizing signal Sy.And summer 620
The feedback equalization signal Sf that decision feedback equalizer 670 is produced is added up with the first equalizing signal Sy
Superposition signal Sz is produced afterwards.
Data slicer 630 comes according to clock signal clk and fixed killer voltage Ss, such as 0V
Cutting superposition signal Sz simultaneously produces data signal Sd.Furthermore, the first error sickle 640 is according to clock
Signal CLK and reference voltage Vref, cut superposition signal Sz and produce the first error signal Serr1.
It is anti-that second error sickle 645 deducts the first decision-making according to clock signal clk and reference voltage Vref
The result (Vref-h1) of feedback equalizing coefficient h1, cuts superposition signal Sz and produces the second error signal
Serr2。
Furthermore, 650 receiving data signal Sd of clock data recovery circuit and the second error signal Serr2 are come
Produce clock signal clk to cut to data slicer 630, the first error sickle 640 and the second error
Device 645.
According to the second embodiment of the present invention, 660 receiving data signal Sd of adaptive filter and first is missed
Difference signal Serr1 is producing a reference voltage Vref to the first error sickle 640, and produces a decision-making
Feedback equalization coefficient sets (DFE coefficient set) h1, h2, h3, h4, h5 is to decision feedback equalizer
670.Wherein, reference voltage Vref deducts the result (Vref-h1) of the first decision feedback equalization coefficient h 1 then
It is transferred to the second error sickle 645.Substantially, adaptive filter 660 is according to data signal Sd
Come the dynamic change reference voltage Vref and decision feedback equalization coefficient with first error signal Serr1
Group h1, h2, h3, h4, h5.
Furthermore, 670 receiving data signal Sd of decision feedback equalizer and decision feedback equalization coefficient sets h1,
Feedback equalization signal Sf is produced after h2, h3, h4, h5 to summer 620, to reduce the first balanced letter
Rear vernier part in number Sy.Substantially, signal Sf is balanced with first for superposition signal Sz, feedback equalization
Relation between signal Sy is：
In the same manner, the clock data recovery system 600 of Fig. 6 A is to repeatedly using identical clock signal clk
Plus signal Sz carries out the sampling of data and phase error.Such clock data recovery system 600, at that time
The clock signal that clock data recovery circuit 650 is produced is identical with data rate.Therefore, data recovery system
600 are also referred to as Bao rate data recovery system.Furthermore, also include in clock data recovery circuit 650
Mesh is strangled mesh Le phase detectors and comes receiving data signal Sd and the second error signal Serr2, and produces according to this
Raw phase place fresh information, to adjust the phase place of clock signal clk.
Fig. 6 B are refer to, its depicted uncoupling effect between signal in second embodiment
(decoupling effect) schematic diagram.As shown in Figure 6B, dotted line I is not input into repeatedly for feedback equalization signal Sf
Plus the superposition signal Sz before device 620；After solid line II is feedback equalization signal Sf input superposers 620
Superposition signal Sz.
Before feedback equalization signal Sf is not input into superposer 620, superposition signal Sz becomes dotted line I.Now,
Second error signal Serr2 can be in 1 transition of phase place ψ, and the sampling phase of clock signal clk can be locked
1 position of phase bit ψ.Furthermore, after feedback equalization signal Sf is input into superposer 620, superposition signal Sz
Become solid line II.Second error signal Serr2 also can be in 1 transition of phase place ψ, and clock signal clk is adopted
Sample phase place can also be locked 1 position of phase place ψ.That is, locking phase will not produce skew.In other words,
Coupling effect, clock signal clk can or can not be produced between first equalizing signal Sy and feedback equalization signal Sf
Phase place will not be affected by feedback equalization signal Sf so that system is more stable.
Compared to first embodiment, one in the clock data recovery system 600 of second embodiment, is increased
Two error sicklies 645, and (reference voltage Vref deducts the first decision feedback to provide another killer voltage
The result (Vref-h1) of equalizing coefficient h1) to the second error sickle 645.Thus, clock can be caused to believe
The phase place of number CLK will not be affected by feedback equalization signal Sf so that system is more stable.
Furthermore, in the clock data recovery system 600 of the present invention, can also amplify including a variable gain
Device (variable gain amplifier, abbreviation VGA), is configured at the input of clock data recovery system 600
Between end and continuous time linear equalizer 610, to the size of leading amplification channel signal, and become
After receiving signal Sx, then it is input into continuous time linear equalizer 610.
In sum, although the present invention is disclosed as above with preferred embodiment, so which is not limited to this
Invention.Those skilled in the art of the invention are without departing from the spirit and scope of the present invention, each when making
The change planted and retouching.Therefore, protection scope of the present invention when regard appended claims confining spectrum as
It is accurate.
Claims (9)
1. a kind of clock data recovery system, including：
Continuous time linear equalizer, receives signal and produces the first equalizing signal；
Summer, receives first equalizing signal and feedback equalization signal, and produces superposition signal；
First error sickle, cuts the superposition signal simultaneously according to clock signal and the first killer voltage
Produce the first error signal；
Second error sickle, cuts the superposition signal according to the clock signal and the second killer voltage
And produce the second error signal；
Data slicer, cuts the superposition signal and produces according to the clock signal and the 3rd killer voltage
Raw data signal；
Clock data recovery circuit, receives the data signal and second error signal, and generation should according to this
Clock signal is to the data slicer, the first error sickle and the second error sickle；
Adaptive filter, receives the data signal and first error signal, and is produced with reference to electricity according to this
The first error sickle is depressed into, and produces decision feedback equalization coefficient sets, wherein the reference voltage etc.
In first killer voltage；And
Decision feedback equalizer, receives the data signal and the decision feedback equalization coefficient sets, and produces according to this
The raw feedback equalization signal is to the summer.
2. clock data recovery system as claimed in claim 1, wherein the decision feedback equalization coefficient sets
Include the first decision feedback equalization coefficient, and second killer voltage equal to the reference voltage deduct this
One decision feedback equalization coefficient.
3. clock data recovery system as claimed in claim 1, the wherein continuous time linear equalizer
Passage is connected to receive the reception signal of the passage output.
4. clock data recovery system as claimed in claim 1, also includes：Variable gain amplifier,
Passage is connected to receive the channel signal of the passage output, and amplifies the size of the channel signal and formed
For the reception signal, and it is input into the continuous time linear equalizer.
5. clock data recovery system as claimed in claim 1, wherein, the 3rd killer voltage is solid
Determine killer voltage.
6. clock data recovery system as claimed in claim 1, wherein, the adaptive filter according to
The data signal and the next dynamic change of first error signal second killer voltage.
7. clock data recovery system as claimed in claim 6, the wherein adaptive filter were according to should
Data signal and the first error signal next dynamic change decision feedback equalization coefficient sets.
8. clock data recovery system as claimed in claim 1, wherein in the clock data recovery circuit
Also include that mesh is strangled mesh and strangles phase detectors, receive the data signal and second error signal, and according to this
Phase place fresh information is produced to adjust the phase place of the clock signal.
9. clock data recovery system as claimed in claim 1, wherein, the adaptive filter is base
In the adaptive filter of lowest mean square.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111786669A (en) * | 2019-04-04 | 2020-10-16 | 智原微电子(苏州)有限公司 | Apparatus for adaptive control of decision feedback equalizer |
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| CN104253606A (en) * | 2013-06-26 | 2014-12-31 | 创意电子股份有限公司 | Receiving circuit |
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| CN100496032C (en) * | 2003-12-19 | 2009-06-03 | 美国博通公司 | Method and communication system to set loop delay of a decision feedback equalizer |
| US20120170621A1 (en) * | 2011-01-03 | 2012-07-05 | Paul Tracy | Decoupling sampling clock and error clock in a data eye |
| CN104253606A (en) * | 2013-06-26 | 2014-12-31 | 创意电子股份有限公司 | Receiving circuit |
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