CN106528456A - Method and system for improving system bus efficiency in video decoding display - Google Patents
Method and system for improving system bus efficiency in video decoding display Download PDFInfo
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- CN106528456A CN106528456A CN201611006083.0A CN201611006083A CN106528456A CN 106528456 A CN106528456 A CN 106528456A CN 201611006083 A CN201611006083 A CN 201611006083A CN 106528456 A CN106528456 A CN 106528456A
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- request
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
- G06F12/1054—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently physically addressed
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/44—Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
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Abstract
The invention discloses a method and system for improving system bus efficiency in video decoding display. A method for combining requests and separating modules is added in a video decoding display system, so that the number of requests of each line of data of a video display module is decreased and the efficiency of the system is greatly improved. According to the method and system, the problems of multiple requests and easy interruption caused by a YUV efficiency storage scheme in the decoding system to the display system are solved, and the overall performance of the system bus is improved.
Description
Technical field
The present invention relates to a kind of method and system for improving system bus efficiency during video decoding shows.
Background technology
With the digital products such as numerous such as DTVs, internet high-resolution video, superb clear DTV STB by
Gradually popularize, the standardization of video coding and decoding technology is causing the technology commercialization in the field.For coding and decoding video,
ITU-T is H.264, the standard such as the H265 and AVS/AVS+/AVS2 with independent intellectual property right is just used widely.Video
The broadcast request real-time of data is high, so as to need bandwidth demand also increasing when bringing high definition, super clear real-time decoding, is
The efficiency performance of system bus also increasingly becomes bottleneck.
In order to put forward efficient packed pixel information, also image can be carried out in the process for processing 16x16 macro blocks less
Segmentation, such as 16x16,16x8,8x16,8x8 these segmentations, H.264, in the standard such as AVS, for bigger compression video code
Rate employs the image segmentation of the 4x4 of minimum, and finer have compressed video image information, so as to have compressed code check, but
But the reading and use of digital independent during considerably increasing coding and decoding, the reading of block data become a certainty
Trend, and the size of various video images is also habitually using 16 or 8 as its width both horizontally and vertically, so as to
In process, so what is read in decoding process is read out according to the mode of block, in order to improve the efficiency majority of reading
Decoder is all yuv data to be stored using special storage mode.
Fig. 1 is the storage scheme of typical decoder storage decoding yuv data.The storage decoder of this mode can be with one
The block of one 8x8 of secondary reading need not enter a new line the continuous effect for reading, improve the block digital independent during coding decoder
Rate.But display module is also had in our system in addition to decoder module, essentially all of display be all according to
Capable mode is processed.For example in the decoding display system of 1080P, for the storage mode of the YUV beneficial to coding and decoding video, show
Show that module reads a line YUV and needs to send 1920/8=240 request, request length only has 8 pixels every time, has a strong impact on
The efficiency of system BUS, is that the subject matter of current system problem is located.
The content of the invention
The technical problem to be solved is, not enough for prior art, there is provided a kind of to improve video decoding display
The method and system of middle system bus efficiency.
To solve above-mentioned technical problem, the technical solution adopted in the present invention is：In a kind of raising video decoding display it is
The method of system bus efficiency, it is characterised in that comprise the following steps：
1）System BOOT starts control system and resets, DDR initialization；
2）Obtain video data source；
3）Decoder reading video data source is decoded, and the yuv data of decoding is sent to DDR controls by system bus then
In device processed, then write in DDR by DDR PHY；
4）System control module control video display module work, video display module is by the multiple request of data line according to being
The maximum length mode of system bus merges request and is sent to system bus；
5）System bus receives the request that video display module is sent, and passes to DDR controller, and DDR controller is resolved to request
Mode is synthesis request, and synthesis request is resolved into the request of data of multiple YUV, and the reverse manner meter by synthetic schemes
The actual physical address of each request is calculated, gradation serial sends reading order and gives DDR PHY, complete multiple multi-address DDR
Read operation；
6）The DDR of return is read data and returns to system bus by DDR controller again, is then returned in video display module.
Step 4）In, actual physical address Address=frame initial address+play information x field address offset+Y-coordinate ground
The x pixel address skews of location x column address skew+X-coordinate address.
Present invention also offers a kind of system for improving system bus efficiency during video decoding shows, including：
Video source：The source of the video data source in conventional system, passes through Ethernet or passes through in similar network Set Top Box
Video data source in the hard disk or USB flash disk of USB connections；For obtaining video data source；
Decoder：Reading video data source is used to decode, and decoded video data source, i.e. yuv data are passed through system then
Bus is sent in DDR controller, is then write in DDR by DDR PHY；
System control module：For dispatching and controlling video display module work；
Video display module：Request for video data and work is shown, by the multiple request of a line video data according to being
The maximum length mode of system bus merges request and is sent to system bus；
System bus：For receiving what video source, decoder, system control module, video display module, DDR controller sent
The request of data, passes to DDR controller；
DDR controller：For the data interaction between connection system bus and DDR PHY, analysis request mode, if be resolved to please
Ask mode to be synthesis request, then synthesis request is resolved into the request of data of multiple YUV, and the reverse side by synthetic schemes
Formula calculates the actual physical address of each request, and gradation serial sends reading order and gives DDR PHY, completes repeatedly multi-address
The read operation of DDR；The DDR of return is read into data again and returns to system bus, then returned in video display module.
The video display module includes：
Request synthesis module：Send out for the multiple request of data line is merged request according to the maximum length mode of system bus
Give system bus.
The DDR controller includes：
Request separation module：For synthesis request to be resolved into the request of data of multiple YUV, and by the reverse of synthetic schemes
Mode calculates the actual physical address of each request, and gradation serial sends reading order and gives DDR PHY, completes multiple multiaddress
DDR read operation；The DDR of return is read into data again and returns to system bus, then returned in video display module.
Compared with prior art, the present invention it is had the advantage that for：The present invention solves the YUV effects in code system
Rate storage scheme is more to the request that display system is brought, the problem being easily interrupted；Improve the overall performance of system bus.
Description of the drawings
Fig. 1 is the storage scheme of typical decoder storage decoding yuv data；
Fig. 2 is one embodiment of the invention system architecture diagram.
Specific embodiment
The characteristics of such as Fig. 2, invention and flow process are as follows：
1) system BOOT starts control system and resets, a series of flow processs such as DDR initialization.
2) video source module starts the video data source for obtaining needing to show.
3) decoder reading video data source decoding, then will be the yuv data for being used for showing after decoding total by 203 systems
Line is sent in DDR controller, is then write in DDR by DDR PHY, and DDR controller confirms it is actual address operation herein
Separation need not be made requests on.
4) system control module control video display module work, video display module is by asking synthesis module by a line
The multiple request of data merges request according to the maximum length mode of system bus and is sent to system bus.
5) system bus receives the request that video display module is sent, and passes to DDR controller module, DDR controller solution
It is synthesis request to analyse request method, asks the request of data for resolving into multiple YUV by asking separation module synthesize, and
Calculated by the reverse manner of synthetic schemes（Request separation module is given）Go out the actual physical address of each request, gradation serial
Transmission reading order completes the read operation of multiple multi-address DDR to DDRPHY, reduces middle by being stranded that other requests are interrupted
Disturb.
6) ask separation module that the DDR of return is read data again and return to system bus, return video display module
In, as the data for returning are spliced according to the mode for reading row sequencing requirement, so the data for returning can be straight
Connect by video display module directly using without the need for processing again, changing for this mode can be so that be previously required to the behaviour of multiple request
Work is completed by way of request once, substantially increases the efficiency of the bus in decoding display system.
The demand mode that request synthesis module is mainly shown according to current video, with the number that behavior unit is shown to needs
According to being read out, process is merged to the original row Visual Display Data for needing repeatedly request in the request read, originally
The data length of request should be linear 8 pixel of data length, the 64 bit data of YUV storages every time, ask merging
Afterwards using the maximum burst size of bus, so as to the request amount for mitigating bus improves bus efficiency, certainly for the total of request
Carry out on wire protocol specifically defined, it is necessary first to define the fixed ID of the mode that a fixed ID value synthesizes as request, when
So this ID value fixed can not be used by other modules, and secondly we need to carry out the address asked from new definition, close
And X of the request address afterwards comprising request row, Y-coordinate information and reading play information, this needs and asks splitting die
The decomposition addresses match of block, just can guarantee that the data got on the address that you want.
Request separation module main task be to be parsed according to the request of special fixed ID on system bus, according to please
The inverse process of the address signal asked parses X, the Y-coordinate of the play information of current demand and request row, according to the length of request
Degree resolves into corresponding several segment datas, is the data of 8 pixels per segment data（According to the conventional storage side of YUV set forth above
Formula determines）, then enter the calculating of row address, according to Address=Frame base address（Frame initial address）+ play
Information x Filed offset（Field address offset）+ Y-coordinate address x line offset（Column address offsets）+ X-coordinate address x
pixel offset（Pixel address offsets）, the accurate location of per section of 8 pixels is accurately calculated, it is straight by DDR controller
Connect and send the requests to DDR PHY, the address of next section of 8 pixels is calculated while often sending a request, then
The request of next address is sent, it is so as to reach the output of the request of high-speed and high-efficiency serial, corresponding to ask separation module by DDR
The data of the pixel that PHY is returned are saved using FIFO, after the data of all of request are all obtained from DDR, then are passed through
The data efficient of original dispersion storage is fed back to request synthesis module according to the protocol mode of system bus by system bus, is reduced
The impact of system effectiveness for bringing is asked repeatedly.
Claims (5)
1. it is a kind of to improve the method that video decodes system bus efficiency in display, it is characterised in that to comprise the following steps：
1）System BOOT starts control system and resets, DDR initialization；
2）Obtain video data source；
3）Decoder reading video data source is decoded, and the yuv data of decoding is sent to DDR controls by system bus then
In device processed, then write in DDR by DDR PHY；
4）System control module control video display module work, video display module is by the multiple request of data line according to being
The maximum length mode of system bus merges request and is sent to system bus；
5）System bus receives the request that video display module is sent, and passes to DDR controller, and DDR controller is resolved to request
Mode is synthesis request, and synthesis request is resolved into the request of data of multiple YUV, and the reverse manner meter by synthetic schemes
The actual physical address of each request is calculated, gradation serial sends reading order and gives DDR PHY, complete multiple multi-address DDR
Read operation；
6）The DDR of return is read data and returns to system bus by DDR controller again, is then returned in video display module.
2. it is according to claim 1 to improve the method that video decodes system bus efficiency in display, it is characterised in that step
4）In, actual physical address Address=frame initial address+play information x field address offset+Y-coordinate address x column address is inclined
The x pixel address skews of shifting+X-coordinate address.
3. it is a kind of to improve the system that video decodes system bus efficiency in display, it is characterised in that to include：
Video source：The source of the video data source in conventional system, passes through Ethernet or passes through in similar network Set Top Box
Video data source in the hard disk or USB flash disk of USB connections；For obtaining video data source；
Decoder：Reading video data source is used to decode, and decoded video data source, i.e. yuv data are passed through system then
Bus is sent in DDR controller, is then write in DDR by DDR PHY；
System control module：For dispatching and controlling video display module work；
Video display module：Request for video data and work is shown, by the multiple request of a line video data according to being
The maximum length mode of system bus merges request and is sent to system bus；
System bus：For receiving what video source, decoder, system control module, video display module, DDR controller sent
The request of data, passes to DDR controller；
DDR controller：For the data interaction between connection system bus and DDR PHY, analysis request mode, if be resolved to please
Ask mode to be synthesis request, then synthesis request is resolved into the request of data of multiple YUV, and the reverse side by synthetic schemes
Formula calculates the actual physical address of each request, and gradation serial sends reading order and gives DDR PHY, completes repeatedly multi-address
The read operation of DDR；The DDR of return is read into data again and returns to system bus, then returned in video display module.
4. it is according to claim 3 to improve the system that video decodes system bus efficiency in display, it is characterised in that described
Video display module includes：
Request synthesis module：Send out for the multiple request of data line is merged request according to the maximum length mode of system bus
Give system bus.
5. it is according to claim 3 to improve the system that video decodes system bus efficiency in display, it is characterised in that described
DDR controller includes：
Request separation module：For synthesis request to be resolved into the request of data of multiple YUV, and by the reverse of synthetic schemes
Mode calculates the actual physical address of each request, and gradation serial sends reading order and gives DDR PHY, completes multiple multiaddress
DDR read operation；The DDR of return is read into data again and returns to system bus, then returned in video display module.
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Cited By (1)
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| CN113573072A (en) * | 2021-09-22 | 2021-10-29 | 苏州浪潮智能科技有限公司 | Image processing method and device and related components |
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Application publication date: 20170322 Assignee: Shandong industry research information and Artificial Intelligence Integration Research Institute Co.,Ltd. Assignor: HUNAN GOKE MICROELECTRONICS Co.,Ltd. Contract record no.: X2021430000001 Denomination of invention: A method and system for improving system bus efficiency in video decoding and display Granted publication date: 20200221 License type: Common License Record date: 20210115 |