CN106528453B - Page table partition management device and method based on compound scale page - Google Patents
Page table partition management device and method based on compound scale page Download PDFInfo
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Abstract
Multiple dimensioned compound page table is used the present invention relates to a kind of, carries out the optimization method of partition space page table mapping management.Operating system towards safety-critical needs to complete the logical address of each subregion and the mapping of physical address using the page table formula storage management mechanism of processor when realizing space partition zone.The logical space of one subregion in an optimized fashion, is converted to the combination of multiple and different size pages by the page table management method based on variable page table size of the invention.The page table of subregion carries out space reflection using the page of large scale as far as possible first, and remaining space is just managed using 4K pages.Using the present invention, in the case where not will cause space junk, page table the space occupied can not only be reduced, while reducing the number for generation of skipping leaf, the final time and space resource for saving operating system space protection function consumption.
Description
Technical field
The present invention relates to a kind of page table partition management device and method based on compound scale page.
Background technique
As safety-critical neighborhood system requirement is increasingly complexity, the especially need of physical synthesis and function synthesized
It asks and is introduced in the fields such as Aeronautics and Astronautics, it is desirable that the embedded OS in safety-critical field can provide for upper layer application
Comprehensive use and insulation blocking function under different subregions.For this purpose, operating system needs to make full use of the storage management of processor
Unit (MMU), especially page table management method are different subregions logical space, different physical address spaces are mapped, to be
Subregion provides the space isolation for being unable to interleaving access each other.
Classical page table management method, by logical address space and physical address space, be divided into the page of 4KB size come into
Row management, while every 4KB logical address being saved in memory to the mapping relations of physical address, form page table.4KB page table,
Using the base address of page directory tables as the basic Context identifier of entire page table, when in use, by the of 32 page logical addresses
31 to the 22nd, as index, are found corresponding page directory entry in page directory tables, obtain second level page table base address；Basis later
The 21st of 32 logical addresses, as index, finds corresponding page table entry, in page table entry to the 12nd in second level page table
Obtain corresponding page physical address.The basic principle of classical 4KB page table mapping is as shown in Figure 1.
The design of classical operating system need to be capable of handling user repeatedly due to the requirement towards complicated applications occasion
, variation scale space application and release process.It, will be so that physical address be empty using the page of 4KB scale under the conditions of this
Between, will not because of the space size for being applied and discharging variation and cause too many space junk and the wasting of resources.
But the application for Safety-Critical System, it is required according to safety specification, is the dynamic for not allowing use space
Application and release.Towards this demand, page management as unit of 4KB has just embodied two defects.One defect is
Page table needs to occupy larger space.With in a subregion, for needing to manage 4GB logical space, if being managed with 4KB pages,
Then a subregion needs the page table space of 4MB+4KB in total.For realizing subregion isolation features, if each subregion is owned by one
Independent page table, as soon as only page table needs to occupy very big space then in system.Another defect, at Most current
Reason device all employs the buffer technology of space reflection relationship, to reduce the expense for frequently obtaining page table entry from memory and being spent.
Many processors provide the buffering of the mapping of a variety of scale spaces including 256B, 4KB to 256MB, under the conditions of this, if
4KB pages is still only used, then since the range mapped every time is smaller, it is larger a possibility that address is not mapped to occur, can be frequent
There is the case where mapping buffer misses, the time overhead of system increases.
Therefore, it is necessary to the application scenarios according to Safety-Critical System, propose that one kind makes full use of processor different scale to reflect
The page table management mechanism of buffering is penetrated, in a kind of dedicated page table management method, subregion under Safety-Critical System is promoted and is isolated
The realization efficiency of function.
Summary of the invention
The object of the present invention is to the design of page table scale can be carried out according to the dedicated usage scenario of Safety-Critical System,
And the mapping of each partition space is gradually carried out, on the basis of realizing space isolation features, hardware resource is made full use of, is finally reached
To the purpose of optimization partition management functions expense.
It is of the invention a kind of using multiple dimensioned compound page table, the device and method for carrying out partition space page table mapping management,
I.e. based on the page table partition management device of compound scale page, comprising: have the processor, memory, page table mould of memory management module
Block, physical address space, logical address space, division module；
Processor executes building and the handoff procedure of entire page table, while carrying out the management of division module, internal necessary
Include memory management module；Memory management module provides page table and maps the place to play a role, completes logical address to physically
The mapping of location；Memory is for storing page table and providing running space for subregion；Physical address space identifies actual physical equipment
The address space accessed on computer address line；The logical address space address space that then identification processor can be accessed；
The rule of page table module definition page table building and switching, also definition management mapping relations of the logical space to physical space；Subregion
Module is used to manage the data of related resource, and related resource includes privately owned physical address space and logical address space, difference
The physical address space of subregion is not identical；
In division module, each subregion has corresponding logical space, including logical space initial address and subregion
Size, the logical start address of each subregion are one 32 data；
In division module, each subregion has corresponding physical space, including physical space initial address, each point
The physical start address in area is one 32 data；
In division module, according to multiple sections of the attribute of access point, the type of section includes code segment, only reads each subregion
According to section, read-write data segment and stack segment；
The logical address of each subregion and the mapping relations of physical address, be by be under the jurisdiction of each subregion spatially under
What text was managed.
Page table module includes page directory tables, page directory tables plot and second level page table；
Page directory tables are the one piece of data in memory, and page directory tables plot is maintained in the spatial context of each subregion,
Indicate which subregion is the page table be under the jurisdiction of；
Each of page directory tables member is page directory entry or big page table entry, and page directory entry or big page table entry are in page mesh
The position in table is recorded, is indexed by highest m of 32 logical addresses, a page directory entry or big page table entry
The logical space that can be managed is 2 (32-m) power, arbitrary integer of the m between 6-14；
The field that page directory entry is 32,32 fields are divided into " page directory entry marker ", " second level page table
Base address " and " second level page table attribute ", " page directory entry marker " shows page directory entry identity；" second level page table base address " shows
The base address of the second level page table of direction, " second level page table attribute " show the access authority attribute of second level page table；
Field that big page table entry is 32,32 fields are divided into " page directory entry marker ", " page base
Location ", " page scale " and " page attribute ", wherein " page directory entry marker " shows big page table entry identity；" page base address " mark
The physical base address of big page, " page scale " determine all pages of the size that big page table entry can manage, and " page attribute " determines that page is visited
Ask permission；
The scale for the big page that big page table entry can manage for 2 (32-m) power byte, to 2 32 power bytes within greatly
Small page, if (32-x) power byte that the page scale of big page table entry management is 2 (x be 0 to the value between m), page directory tables
In 2 m-x power big page table entry, it should repeat same content；
Each of second level page table member is page table entry, and position of the page table entry in page table is patrolled by 32
What the position n after collecting highest m in address was indexed, n is 1 to the arbitrary integer between 24-m, page table in second level page table
The logical space of Xiang Suoneng management is 2 32-m-n power；Page table entry is 32 bit fields, is divided into " page base address ", " page ruler
Degree ", and " page attribute ", wherein the physical base address of " page base address " mark page, " page scale " determines that page table entry can map
All pages of sizes, page attribute determines all possible access to web page permission, page table entry manages the page of a variety of scales, wherein 2
32-m-n power byte, for the page for the smallest dimension that page table entry can manage, 2 32-m-1 power byte, for page table entry institute energy
The page of the out to out of management, if the 32-m-y power byte that the page scale of page table entry management is 2, y is 1 to the integer between n
It is worth, then the page table entry of the n-y power of 2 in page table, it should repeat same content；
In addition, the page table partition management method based on compound scale page:
It include: the processor for having memory management module, memory, page table module, physical address space, logical address sky
Between, division module；
Processor executes building and the handoff procedure of entire page table, while carrying out the management of division module, internal necessary
Include memory management module；Memory management module provides page table and maps the place to play a role, completes logical address to physically
The mapping of location；Memory is for storing page table and providing running space for subregion；Physical address space identifies actual physical equipment
The address space accessed on computer address line；The logical address space address space that then identification processor can be accessed；
The rule of page table module definition page table building and switching, also definition management mapping relations of the logical space to physical space；Subregion
Module is used to manage the data of related resource, and related resource includes privately owned physical address space and logical address space, difference
The physical address space of subregion is not identical；
Step 1): in 32 logical address spaces, division module be each subregion distribute logical start address and
Partition size；The logical start address of subregion, is one 32 data, the logical start address of subregion not with practical object
The physical address for managing equipment is overlapped, and is aligned with 4KB size, the size of subregion, is the integral multiple of 4KB.
Step 2): being divided into multiple sections for the space of subregion, the integral multiple that each section of space be continuous and size is 4KB, in subregion
It is each section of distribution logical address space in logical space, in the memory of physical address space, for each section of corresponding physics of distribution
Address space；
Step 3): the page scale selected in page table module, page scale are reflecting for actual hardware memory management module support
Penetrate the subset in size, can the size of page selection should be with partition space planning process, the size of obtained section amount having the same
Grade；
Step 4): an independent page table is constructed for each subregion, each subregion in memory, applies for a page directory
Table space, the space management context by the first address of the page directory tables, as the subregion；
Step 5): carrying out partition space mapping management, by the space of subregion according to the attribute segments for allowing to access, the class of section
Type includes but is not limited to code segment, read-only data section, read-write data segment or stack segment；
Step 6): by subregion page table, successively mapping each section of space,
Step 7): since each section of logic first address, being mapped using the maximum page of scale first, if cannot be at
Function then selects the page of time large scale to be mapped, until finding a suitable most big page, completes the first page in this section of space
Mapping of the logical address to physical address；
Step 8): to each section of remaining space, continuing to use the maximum page of scale and mapped, if cannot succeed,
Then the page of time large scale is selected to be mapped, until finding a suitable most big page, until this section of space all maps
Until into page table；
7) step 9): if subregion has remaining section, thening follow the steps, if subregion is without remaining section, subregion page table is to each section of space
Successively mapping terminates.
Further, in step 7): if the scale of selected page is greater than or equal to the size 2 that page directory entry can manage
When (32-m) power byte, then according to logical address, obtain in page directory tables after the page directory entry of corresponding position, by " page directory
Item marker " is set to " big page table entry " state, and in the big page table entry, successively in the physics of " page base address " field filling page
Page size is inserted in base address, " page scale " field, and " page attribute " field inserts page attribute parameter, completes the mapping of big page.
Further, in step 7): if the scale of selected page is less than (32-m) for the size 2 that page directory entry can manage
When power byte, then according to logical address, obtain in page directory tables after the page directory entry of corresponding position, it will " page directory entry mark
Position " is set to " page directory entry " state, and from memory, applies for a second level page table space, which is inserted page mesh
" second level page table base address " field in item is recorded, and fills in " second level page table attribute " field.In the second level page table space newly applied,
According to the logical address of institute's application page, page table entry of this page in second level page table is indexed, and in the page table entry, is successively filled
" page base address ", " page scale ", and " page attribute " field.
Further, the big page table entry either in page directory tables or the page table entry in second level page table, if mapping
Page scale, greater than the space that a page table entry can manage, then multiple page table entries can repeat the content of this page table entry, until
The scale summation of multiple page table entries, until being equal to mapped page scale.
Further, when the miss exception of page table mapping occurs for processor operation partition content, processor is from subregion
In context space, page table base address is obtained, and according to the logical address for leading to page table mapping miss exception, the rope from page table
Corresponding page table entry is guided to, the page physical address and page table that will be saved in the page logical address and page table entry that index page table entry
Corresponding page attribute in, is placed in memory management module, mapping of the logical space to physical space can be completed.
The present invention has the advantage that and the utility model has the advantages that the present invention is a kind of using multiple dimensioned compound page table, progress subregion is empty
Between page table mapping management optimization method, by this method, the page table space that each subregion occupies can greatly reduce；Subregion
In operational process, the probability of page mapping miss can also greatly reduce.Meanwhile towards Safety-Critical System, the method with 4KB pages
Table management method is compared, and space utilization rate there will not be any additional increase.
Detailed description of the invention
Fig. 1 is the schematic illustration that logical address conversion is carried out towards 4KB pages；
Fig. 2 is the schematic illustration that compound page table carries out space management；
Fig. 3 is the example schematic of page directory entry design；
Fig. 4 is the example schematic of one big page table entry design；
Fig. 5 is the example schematic of page table entry design；
Fig. 6 is the example schematic 1 that this method carries out partition management；
Fig. 7 is the example schematic 2 that this method carries out partition management；
Fig. 8 is the example schematic 3 that this method carries out partition management；
Specific embodiment
The description of implementation method is carried out in conjunction with specific chart.As shown in Fig. 2, being that the compound page table of possible use carries out
Space management, finally obtained space reflection schematic diagram.To be directed to the MMU mechanism of MPC8548 processor, carried out using this method
For design.The MMU mechanism of MPC8548, provides only the mapping mode of TLB, does not have to the concrete methods of realizing of page table any
It limits, operating system is needed to be designed according to the actual situation.
The MMU of MPC8548 processor, TLB support the page of following nine kinds of scales:
Table 1
| Scale | 4KB | 16KB | 64KB | 256KB | 1MB | 4MB | 16MB | 64MB | 256MB |
In addition, the application of each subregion, is estimated according to scale, each subregion can about occupy the space 1MB to 20MB.
At this point, carrying out the design of compound page table first according to the above processor information.
1. compound page table design:
1.1 determine the selection of available page size first.The available page table scale of comprehensive treatment device, and apply each point
The use demand in area, in that case it can be decided that the page table scale of selection includes following 8 kinds:
Table 2
| PS0 | PS1 | PS2 | PS3 | PS4 | PS5 | PS6 | PS7 | |
| Scale | 4KB | 16KB | 64KB | 256KB | 1MB | 4MB | 16MB | 64MB |
Scale above, the scale that TLB is supported in all MPC8548 processors, while the sky of application partition can be covered
Between range.
The design of page directory entry is carried out after 1.2.The key of this step is the space size that page directory entry is managed.Through
The space of the page table of allusion quotation, page directory entry management is 4MB, at this point, the size of page directory tables and page table is 4KB.In this case,
When the page used is 4MB or more, so that it may save the page table space of 4KB.But come from the demand scale of each application partition
See the section possibility very little of 4MB size occur.If the space of page directory entry management is set as 1MB, at this time page directory tables size
For 16KB, the size of page table is 1KB.Therefore, using the method, the page of 12 1MB if it exists, it is ensured that than page directory entry pipe
The mode of reason saves more page table spaces.The space for selecting page directory entry management herein is that 1MB mode is managed.I.e. PDS is
1MB。
1.3 by 32 of page directory entry, last position is defined as " page directory entry mark ", when this position be 1, when, indicate
For page directory entry；When being 0, it is expressed as a big page table entry.
1.4 are used as page directory entry, are directed toward the page table of a 1KB, it is therefore desirable to and 22 in 32, to indicate page table
Address.It is remaining 9 last, it can be used to identify the read and write access attribute of page table.Finally design such as Fig. 3:
Wherein, page table attribute is designed as follows according to the TLB attribute of MPC8548:
Table 3
If 1.5, as big page table entry, support tetra- kinds of page scales of 1MB, 4MB, 16MB, 64MB, need 2 to distinguish a page ruler
Degree.Most 12 are needed to identify page base address, and 9 are carried out the access attribute of mark page.Final design such as Fig. 4:
The page scale properties of the wherein feature of page table attribute such as table 3, big page table are as follows:
Table 4
| bit[11 10] | Big page scale |
| 0 0 | 64MB |
| 0 1 | 1MB |
| 1 0 | 4MB |
| 1 1 | 16MB |
Tetra- kinds of page scales of 4KB, 16KB, 64KB, 256KB are supported in 1.6 design for page table entry, and needing 2 is to distinguish
Page scale, needs most 20 to identify page base address, 9 be the access attribute for carrying out mark page.Final design such as Fig. 5:
Wherein, the page scale properties of page table are as follows:
Table 5
| bit[11 10] | Big page scale |
| 0 0 | 256KB |
| 0 1 | 4KB |
| 1 0 | 16KB |
| 1 1 | 64KB |
2. the planning of subregion
In this example, using 2 subregions, each subregion is divided into code segment, read-only data section, read-write data segment, heap
Four parts of stack segment.
The space of two subregions is allocated as follows:
6 subregion A of table
7 subregion B of table
| Name section | Length | Initial address | Read-write properties |
| Code segment | 0x44C000 | 0xC000 0000 | It can be performed, can not read and write |
| Read-only data section | 0x7 4000 | 0xC044C000 | Not can be performed it is unreadable, it is writeable |
| Read-write data segment | 0x5E A000 | 0xC04C 0000 | It not can be performed, it is read-write |
| Stack segment | 0x10 0000 | 0xC0AA A000 | It not can be performed, it is read-write |
3. management of the page table to partition space
3.1 be one independent page table of each subregion application.Apply for a page directory tables first, by the base of this page directory tables
Address is stored in the partition space context of subregion, when so as to subregion switching, carries out the operation of page table switching.
3.2 as shown in table 6, table 7, and the logical address of subregion A and subregion B are since 0xC,000 0000, each section big
Small is the integral multiple of 4KB, therefore the total size of subregion is also the integral multiple of 4KB.
Physical address for subregion A distribution is as follows:
| Name section | Length | Initial address | Physical start address |
| Code segment | 0x5E 1000 | 0xC000 0000 | 0x0800 0000 |
| Read-only data section | 0x8 2000 | 0xC05E 1000 | 0x085E 1000 |
| Read-write data segment | 0x84 1000 | 0xC066 3000 | 0x0866 3000 |
| Stack segment | 0x15 0000 | 0xC0EA 4000 | 0x08EA 4000 |
Section one by one in 3.3 pairs of subregions, gradually maps in page table.By taking subregion A as an example, code segment is mapped first.It rises
Beginning address be 0xC,000 0000, size be 0x5E 1000, at this time attempt use maximum page 64MB, to subregion A code segment into
Row mapping.
The criterion whether page can map code segment is following two condition:
A) this section of logical start address with can page selection size be aligned?
Does is b) segment length greater than or equal to this page of size?
Since 0x 400 0000 is greater than 0x5E 1000,64MB cannot be selected, secondly selects 16MB.
Since 0x 100 0000 is greater than 0x5E 1000,16MB cannot be selected, secondly selects 4MB.
Since 0x 40 0000 is less than 0x5E 1000,4MB is selected for the first time.In the offset 0xC000 of page directory tables
At 0000/0x10 0000=0xC00, page directory entry is obtained.Since 4MB is greater than the space 1MB that page directory entry can manage,
Therefore application second level page table is not needed, the big page table entry of 4MB is used directly in page directory entry, while occupying 4 page directory entries.This
When obtained page table such as Fig. 6:
The mapping that 4MB is completed in the code segment of 3.4 subregion A, there remains 0x1E 1000 at this time, be left the starting in space
Logical address is 0xC,040 0000, continues to use the selection that the two above criterions carry out page mapping.
At this time from can successively judge from big to small in page selection, 1MB pages of selection is obtained.In the offset 0xC04 of page directory tables
Place, obtains page directory entry.Since 1MB is equal to the space 1MB that page directory entry can manage, application second level page is not needed
Table uses the big page table entry of 1MB directly in page directory entry, occupies a page directory entry.The page table obtained at this time such as Fig. 7:
The mapping in the space 5MB is completed in the code segment of subregion A, there remains 0xE 1000 at this time, is left the starting in space
Logical address is 0xC,050 0000, continues to use the selection that the two above criterions carry out page mapping.
At this time from can successively judge from big to small in page selection, 256KB pages of selection is obtained.In the offset of page directory tables
At 0xC05, page directory entry is obtained.Since 256KB is less than the space 1MB that page directory entry can manage, apply for the two of 1KB at this time
Grade page table space.And at the offset of second level page table 0, page table entry is obtained, carries out 256KB pages of mapping.Since 256KB is 4KB
64 times, therefore occupy 64 page table entries simultaneously.The page table obtained at this time such as Fig. 8:
The code segment of subregion A there remains space 0xA 1000 at this time, and initial logical address is 0xC,054 0000.It is subsequent
It is continuous that page distribution is carried out to code segment, successively also obtain the page of 2 256KB, the page of 2 64KB and the page of a 4KB.At this point, point
The code segment of area A all complete by mapping.
3.5 start to be managed the read-only data section of subregion A at this time.
The logical start address of this section is 0xC05E 1000, and length is 0x8 2000.Due to logical start address only with
The alignment of 4KB size, therefore mapped first from 4KB scale page.It is sequentially allocated the page to 3 4KB.
At this point, the logical start address in remaining space is 0xC05E 4000, length 0x7F000.Address and 16KB
(0x4000) alignment, and residue length is greater than 16KB, therefore uses 16KB pages.It is sequentially allocated continuous 3 16KB pages.
At this point, the logical start address in remaining space is 0xC05F 0000, length is 0x7 3000.Address and 64KB
(0x1 0000) alignment, and residue length is greater than 64KB, therefore uses 64KB pages.
At this point, the logical start address in remaining space is 0xC,060 0000, length is 0x6 3000.Address and 256KB
(0x4 0000) alignment, and residue length is greater than 256KB, therefore uses 256KB pages.At this point, since logical address crosses one
In a new 1MB alignment address, therefore, at the 0xC06 offset of page directory tables, it is directed toward a second level page table newly applied,
In new page table, this 256KB pages is mapped.
According to above criterion, continue to judge, continues to obtain the page of 2 64KB and the page of 3 4KB, it is complete later
The mapping of the data segment of Composition Region A.
According to preceding method, it is finally completed the space reflection management of subregion A and subregion B.
By actual verification, the above method can be realized the function of subregion isolation in MPC8548 processor, and have
Effect reduces the probability in page table space and TLB miss.
The present invention can also have other various embodiments, without departing from the spirit and substance of the case in the present invention, be familiar with this
The technical staff in field makes various corresponding changes and modifications in accordance with the present invention, but these corresponding changes and modifications are all
It should fall within the scope of protection of the appended claims of the present invention.
Claims (7)
1. the page table partition management device based on compound scale page characterized by comprising have the processing of memory management module
Device, memory, page table module, physical address space, logical address space, division module；
Processor executes building and the handoff procedure of entire page table, while carrying out the management of division module, the storage tube of processor
Reason module provides page table and maps the place to play a role, completes mapping of the logical address to physical address；Memory is used for memory page
Table simultaneously provides running space for subregion；Physical address space identifies the ground that actual physical equipment accesses on computer address line
Location space；The logical address space address space that then identification processor can be accessed；Page table module definition page table is constructed and is cut
The rule changed, also definition management mapping relations of the logical space to physical space；Division module is used to manage the number of related resource
According to related resource includes privately owned physical address space and logical address space, and the physical address space of different subregions is not identical；
In division module, each subregion has corresponding logical space, including logical space initial address and partition size,
The logical start address of each subregion is one 32 data；
In division module, each subregion has corresponding physical space, including physical space initial address, each subregion
Physical start address is one 32 data；
In division module, according to multiple sections of the attribute of access point, multiple sections of type includes code segment, only reads each subregion
According to section, read-write data segment and stack segment；
The logical address of each subregion and the mapping relations of physical address, be by be under the jurisdiction of the spatial context of each subregion into
Row management；
Page table module includes page directory tables, page directory tables plot and second level page table；
Page directory tables are the one piece of data in memory, and page directory tables plot is maintained in the spatial context of each subregion, indicates
Which subregion is the page table be under the jurisdiction of；
Each of page directory tables member is page directory entry or big page table entry, and page directory entry or big page table entry are in page directory tables
In position, be to be indexed by highest m of 32 logical addresses, a page directory entry or big page table entry institute energy
The logical space enough managed is 2 32-m power, arbitrary integer of the m between 6-14；
The field that page directory entry is 32,32 fields are divided into " page directory entry marker ", " second level page table base
Location " and " second level page table attribute ", " page directory entry marker " shows page directory entry identity；" second level page table base address " shows to be directed toward
Second level page table base address, " second level page table attribute " shows the access authority attribute of second level page table；
The field that big page table entry is 32,32 fields be divided into " page directory entry marker ", " page base address ",
" page scale " and " page attribute ", wherein " page directory entry marker " shows big page table entry identity；" page base address " identifies big page
Physical base address, " page scale " determines all pages of the size that big page table entry can manage, and " page attribute " decision access to web page is weighed
Limit；
The scale of the big page that big page table entry can manage for 2 32-m power byte, to 2 32 power bytes within size
Page, if the 32-x power byte that the page scale of big page table entry management is 2, x is 0 to the value between m, then 2 in page directory tables
The big page table entry of m-x power, it should repeat same content；
Each of second level page table member, be page table entry, position of the page table entry in page table be by 32 logically
What the position n after highest m in location was indexed, n is 1 to the arbitrary integer between 24-m, page table entry institute in second level page table
The logical space that can be managed is 2 32-m-n power；Page table entry is 32 bit fields, is divided into " page base address ", " page scale ", with
And " page attribute ", wherein the physical base address of " page base address " mark page, " page scale " determines that page table entry can map all
Page size, page attribute determine all possible access to web page permission, and page table entry manages the page of a variety of scales, wherein 32-m-n times of 2
Square cards for learning characters section, for the page for the smallest dimension that page table entry can manage, 2 32-m-1 power byte can manage most for page table entry
The page of large scale, if the 32-m-y power byte that the page scale of page table entry management is 2, y is 1 to the integer value between n, then page table
In 2 n-y power page table entry, it should repeat same content.
2. the page table partition management method based on compound scale page, it is characterised in that:
It include: processor, memory, page table module, physical address space, logical address space, division module；
Processor has memory management module, and processor executes building and the handoff procedure of entire page table, while carrying out subregion mould
The management of block；The memory management module provides page table and maps the place to play a role, completes logical address to physical address
Mapping；Memory is for storing page table and providing running space for subregion；Physical address space identifies actual physical equipment and is counting
The address space accessed in calculation machine address wire；The logical address space address space that then identification processor can be accessed；Page table
The rule of module definition page table building and switching, also definition management mapping relations of the logical space to physical space；Division module
For managing the data of related resource, related resource includes privately owned physical address space and logical address space, different subregions
Physical address space it is not identical；
Step 1): in 32 logical address spaces, division module is that each subregion distributes logical start address and subregion
Size；The logical start address of subregion, is one 32 data, and the logical start address of subregion does not set with actual physics
Standby physical address is overlapped；
Step 2): being divided into multiple sections for the space of subregion, the integral multiple that each section of space be continuous and size is 4KB, in zoned logic
It is each section of distribution logical address space in space, in the memory of physical address space, for each section of corresponding physical address of distribution
Space；
Step 3): selecting page scale in page table module, and page scale is the mapping size that actual hardware memory management module is supported
In subset, can page selection the size magnitude having the same of section that should be obtained with partition space planning process of size；
Step 4): an independent page table is constructed for each subregion, each subregion in memory, applies for a page directory tables sky
Between, the space management context by the first address of the page directory tables, as the subregion；
Step 5): carrying out partition space mapping management, by the space of subregion according to the attribute segments for allowing to access, the type packet of section
Include code segment, read-only data section, read-write data segment or stack segment；
Step 6): by subregion page table, each section of space is successively mapped；
Step 7): since each section of logic first address, being mapped using the maximum page of scale first, if cannot succeed,
Then the page of time large scale is selected to be mapped, until finding a suitable most big page, completes the first page in this section of space and patrol
Collect mapping of the address to physical address；
Step 8): it to each section of remaining space, continues to use the maximum page of scale and is mapped, if cannot succeed, selected
It is mapped with the page of secondary large scale, until finding a suitable most big page, until this section of space is all mapped to page
Until in table；
7) step 9): if subregion has remaining section, thening follow the steps, if subregion without remaining section, subregion page table to each section of space successively
Mapping terminates.
3. the page table partition management method according to claim 2 based on compound scale page, in step 7): if selected page
When scale is greater than or equal to the 32-m power byte for the size 2 that page directory entry can manage, then according to logical address, page is obtained
In catalogue listing after the page directory entry of corresponding position, " page directory entry marker " is set to " big page table entry " state, and in the big page
In list item, page size, " page attribute " successively are inserted in the physical base address of " page base address " field filling page, " page scale " field
Field inserts page attribute parameter, completes the mapping of big page, wherein arbitrary integer of the m between 6-14.
4. the page table partition management method according to claim 2 based on compound scale page, in step 7): if selected page
When scale is less than the 32-m power byte for the size 2 that page directory entry can manage, then according to logical address, page directory tables are obtained
After the page directory entry of middle corresponding position, " page directory entry marker " is set to " page directory entry " state, and from memory, application one
The page table base address is inserted " second level page table base address " field in page directory entry, and fills in " second level page by a second level page table space
Table Properties " field, according to the logical address of institute's application page, indexes the page in second level in the second level page table space newly applied
Page table entry in page table, and in the page table entry, successively fill " page base address ", " page scale ", and " page attribute " field.
5. the page table partition management method according to claim 2 based on compound scale page, which is characterized in that either page
The page table entry in big page table entry or second level page table in catalogue listing is greater than a page table entry institute energy if the page scale of mapping
The space enough managed, then multiple page table entries can repeat the content of this page table entry, until the scale summation of multiple page table entries, be equal to
Until mapped page scale.
6. the page table partition management method according to claim 2 based on compound scale page, which is characterized in that work as processor
When running the miss exception of partition content generation page table mapping, processor obtains page table base from subregion context space
Location, and according to the logical address for leading to page table mapping miss exception, corresponding page table entry is indexed from page table, by index page
Corresponding page attribute in the page physical address and page table entry saved in the page logical address and page table entry of list item, is placed in and deposits
It stores up in management module, mapping of the logical space to physical space can be completed.
7. the page table partition management method according to claim 2 based on compound scale page, it is characterised in that: step 1)
In, the logical start address of subregion is aligned with 4KB size, and the size of subregion is the integral multiple of 4KB.
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