CN106526996B - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
- Publication number
- CN106526996B CN106526996B CN201611076298.XA CN201611076298A CN106526996B CN 106526996 B CN106526996 B CN 106526996B CN 201611076298 A CN201611076298 A CN 201611076298A CN 106526996 B CN106526996 B CN 106526996B
- Authority
- CN
- China
- Prior art keywords
- film transistor
- tft
- thin film
- grid
- voltage signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
- G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Mathematical Physics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Optics & Photonics (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
This application discloses a kind of array substrate, display panel and display devices, wherein, array substrate includes: scan line and data line, scan line is intersected with data line insulation limits multiple pixel units, pixel unit includes n concatenated thin film transistor (TFT)s and pixel electrode, wherein, n is positive integer, and n≤2；The drain electrode of the 1st thin film transistor (TFT) in n concatenated thin film transistor (TFT)s is connect with the pixel electrode, and the source electrode of n-th of thin film transistor (TFT) is connected to a data line, for receiving data voltage signal；The grid of each thin film transistor (TFT) in the n concatenated thin film transistor (TFT)s receives a scanning voltage signal, wherein, the grid of i-th of thin film transistor (TFT) received scanning voltage signal less than the received scanning voltage signal of the grid of j-th thin film transistor (TFT) institute, i, j is positive integer, 1≤i≤n, 1≤j≤n, and i ≠ j.The embodiment of the present invention reduces the leakage current of display panel, improves display quality.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of array substrates, display panel and display device.
Background technique
As shown in FIG. 1, FIG. 1 is a thin film transistor (TFT) control pixel in the prior art is aobvious for pixel circuit in the prior art
The pixel circuit shown；The pixel circuit include storage capacitance Cst, display capacitor Clc, thin film transistor (TFT) T1 and scan line G with
And data line SD, wherein storage capacitance Cst, display capacitor Clc are in parallel, and one common end connects public voltage signal source Vcom,
The drain electrode of another common end connection thin film transistor (TFT) T1；The second end of thin film transistor (TFT) T1 is connect with data line SD；Film crystal
The grid of pipe T1 is connect with scan line G, and thin film transistor (TFT) T1 is used to control the display of display.
During the display of display is kept, storage capacitance Cst carries out electric discharge and keeps display.But since thin film transistor (TFT) is deposited
Larger leakage current (i.e. there are leakage currents between AC node in Fig. 1), and the display quality of display is influenced, particularly with low
When frequency is shown, display is longer during keeping, and the influence of leakage current becomes apparent.
Summary of the invention
In view of this, the present invention provides a kind of array substrate, display panel and display device, with solve in the prior art as
The problem of leakage current in plain circuit is larger, is affected to display quality.
To achieve the above object, the invention provides the following technical scheme:
A kind of array substrate, comprising:
Scan line and data line, the scan line is intersected with data line insulation limits multiple pixel units, the picture
Plain unit includes n concatenated thin film transistor (TFT)s and pixel electrode, wherein n is positive integer, and n≤2；
The drain electrode of the 1st thin film transistor (TFT) in the n concatenated thin film transistor (TFT)s is connect with the pixel electrode, the
The source electrode of n thin film transistor (TFT) is connected to a data line, for receiving data voltage signal；
The grid of each thin film transistor (TFT) in the n concatenated thin film transistor (TFT)s receives a scanning voltage signal,
In, the grid of i-th of thin film transistor (TFT) received scanning voltage signal it is received less than the grid of j-th thin film transistor (TFT) institute
Scanning voltage signal, i, j are positive integer, 1≤i≤n, 1≤j≤n, and i ≠ j.
The present invention also provides a kind of display panel, the display panel includes array substrate recited above.
In addition, the display device includes display panel recited above the present invention also provides a kind of display device.
It can be seen via above technical scheme that including n concatenated in the pixel unit of array substrate provided by the invention
The grid reception of thin film transistor (TFT) and pixel electrode, each thin film transistor (TFT) in the n concatenated thin film transistor (TFT)s is swept
Retouch voltage signal, wherein received less than j-th thin film transistor (TFT) of scanning voltage signal of grid institute of i-th of thin film transistor (TFT)
The received scanning voltage signal of grid institute, i, j are positive integer, 1≤i≤n, 1≤j≤n, and i ≠ j.Pass through i-th of setting
The grid of thin film transistor (TFT) received scanning voltage signal less than the received scanning voltage of the grid of j-th thin film transistor (TFT) institute
Signal, so that the standoff voltage of n concatenated thin film transistor (TFT)s is not identical, and the standoff voltage of i-th of thin film transistor (TFT) is less than
The originally standoff voltage of thin film transistor (TFT) thereby reduces n to reduce the leakage current by i-th of thin film transistor (TFT)
The leakage current of concatenated thin film transistor (TFT), and then influence of the leakage current to display is reduced, improve display quality.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is that a thin film transistor (TFT) controls the pixel circuit that pixel is shown in the prior art；
Fig. 2 is that two thin film transistor (TFT)s control the pixel circuit that pixel is shown in the prior art；
Fig. 3 A is the ID-VG characteristic curve of single a-Si thin film transistor (TFT)；
Fig. 3 B is the ID-VG characteristic curve of single LTPS thin film transistor (TFT)；
Fig. 4 is a kind of schematic diagram of the corresponding equivalent pixel circuit figure of array substrate provided in an embodiment of the present invention；
Fig. 5 is the schematic diagram of the corresponding equivalent pixel circuit figure of another array substrate provided in an embodiment of the present invention；
Fig. 6 is the schematic diagram of the corresponding equivalent pixel circuit figure of another array substrate provided in an embodiment of the present invention；
Fig. 7 is that the sectional pressure element in a kind of corresponding equivalent pixel circuit figure of array substrate provided in an embodiment of the present invention is
The schematic diagram of multiple series connection bleeder transistors；
Fig. 8 is the sectional pressure element in the corresponding equivalent pixel circuit figure of another array substrate provided in an embodiment of the present invention
For the schematic diagram of multiple bleeder transistors in parallel；
Fig. 9 is a kind of schematic diagram of display panel provided in an embodiment of the present invention；
Figure 10 is a kind of schematic diagram of display device provided in an embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Fig. 2 is the pixel circuit that two thin film transistor (TFT)s control pixels are shown in the prior art, pixel circuit shown in Fig. 2,
Than pixel circuit shown in Fig. 1 more connect a thin film transistor (TFT) T2, thin film transistor (TFT) T1 and thin film transistor (TFT) T2 grid simultaneously
It is connected on scan line G1, same scanning voltage signal is received, for controlling the display of display.But similarly, due to film
There are larger leakage current (i.e. there are leakage currents between AC node in Fig. 2) for transistor, and influence the display quality of display, especially
When it shows low frequency, display is longer during keeping, and the influence of leakage current becomes apparent.
The ID-VG characteristic curve that Fig. 3 A and Fig. 3 B, Fig. 3 A are single a-Si thin film transistor (TFT) is referred to, thin film transistor (TFT) is worked as
Drain-source between voltage VDS when remaining unchanged, the relationship of leakage current ID and gate source voltage VGS, from Fig. 3 A as can be seen that pair
Definite value is taken in VGS, when such as -10V (standoff voltage of a-Si thin film transistor (TFT) being generally -10V), the leakage current ID of thin film transistor (TFT)
It is reduced with the reduction of drain-source voltage VDS；Fig. 3 B is single LTPS (low temperature polycrystalline silicon, Low Temperature Ploy
Silicon) the ID-VG characteristic curve of thin film transistor (TFT), it can also be seen that taking definite value for VGS from Fig. 3 B, such as -4V (LTPS
The standoff voltage of thin film transistor (TFT) is generally -4V) when, the leakage current ID of thin film transistor (TFT) is dropped with the reduction of drain-source voltage VDS
It is low.
Therefore, the leakage current of thin film transistor (TFT) can be reduced by reducing the drain-source voltage VDS of thin film transistor (TFT).This hair
Bright to provide a kind of array substrate based on the above principles, the array substrate includes:
Scan line and data line, the scan line is intersected with data line insulation limits multiple pixel units, the picture
Plain unit includes n concatenated thin film transistor (TFT)s and pixel electrode, wherein n is positive integer, and n≤2；
The drain electrode of the 1st thin film transistor (TFT) in the n concatenated thin film transistor (TFT)s is connect with the pixel electrode, the
The source electrode of n thin film transistor (TFT) is connected to a data line, for receiving data voltage signal；
The grid of each thin film transistor (TFT) in the n concatenated thin film transistor (TFT)s receives a scanning voltage signal,
In, the grid of i-th of thin film transistor (TFT) received scanning voltage signal it is received less than the grid of j-th thin film transistor (TFT) institute
Scanning voltage signal, i, j are positive integer, 1≤i≤n, 1≤j≤n, and i ≠ j.
The embodiment of the present invention is less than jth by the received scanning voltage signal of grid institute of i-th of thin film transistor (TFT) of setting
The received scanning voltage signal of grid institute of a thin film transistor (TFT), so that the standoff voltage of n concatenated thin film transistor (TFT)s not phase
Together, make the source and drain electrode resistance of i-th of thin film transistor (TFT) less than the source and drain electrode resistance of j-th of thin film transistor (TFT), so that i-th
The partial pressure of thin film transistor (TFT) reduces, so that the carrier quantity passed through in the unit time in i-th of thin film transistor (TFT) reduces,
The leakage current by i-th of thin film transistor (TFT) is reduced, to reduce the leakage current of n concatenated thin film transistor (TFT)s, in turn
Influence of the leakage current to display is reduced, display quality is improved.
It should be noted that the received scanning voltage signal of grid institute that the present invention does not limit i-th of thin film transistor (TFT) is small
In j-th of thin film transistor (TFT) grid received scanning voltage signal specific implementation, each film crystal can be made
The grid of pipe is all connected with a scan line, realizes that i-th of film is brilliant by increasing different scanning voltage signals in scan line
The grid of body pipe received scanning voltage signal less than the received scanning voltage signal of the grid of j-th thin film transistor (TFT) institute,
The grid of i-th of thin film transistor (TFT) in the i.e. described n thin film transistor (TFT) is connected with a scan line, j-th of film crystal
The grid of pipe is connected with another scan line, and added scanning voltage signal is different in this two scan lines, so that i-th of film
Scanning voltage signal in the connected scan line of the grid of transistor is less than in the connected scan line of grid of j-th of thin film transistor (TFT)
Scanning voltage signal.
It can also be by the grid of i-th of thin-film transistor gate and j-th of thin film transistor (TFT) and identical scan line
Between increase different sectional pressure element and realize the received scanning voltage signal of grid institute of i-th of thin film transistor (TFT) less than j-th
The received scanning voltage signal of grid institute of thin film transistor (TFT).Such as increase between i-th of thin-film transistor gate and scan line
The biggish sectional pressure element of voltage dividing ability, so that the received scanning voltage signal of grid institute of i-th of thin film transistor (TFT) is less than
The received scanning voltage signal of grid institute of j-th of thin film transistor (TFT).
The present invention is introduced so that two film crystalline substance pipes are connected as an example below, Fig. 4 is provided in an embodiment of the present invention one
The schematic diagram of the corresponding equivalent pixel circuit figure of kind array substrate, the array substrate include:
Scan line and data line SD, scan line is intersected with data line SD insulation limits multiple pixel units, pixel unit packet
Include two concatenated thin film transistor (TFT)s and pixel electrode；Pixel unit can also include display capacitor and/or deposit in the present embodiment
Storage is held, and shows that a pole plate of capacitor and/or storage capacitance is pixel electrode.
Usual situation, as shown in figure 4, Fig. 4 is the corresponding equivalent pixel circuit of array substrate provided in an embodiment of the present invention
The schematic diagram of figure, pixel unit includes display capacitor Clc and storage capacitance Cst simultaneously, and shows that capacitor and storage capacitance are mutual
Parallel connection, a pole plate of display capacitor Clc and storage capacitance Cst are pixel electrode.
Two concatenated thin film transistor (TFT)s as shown in figure 4, first film transistor T1 drain electrode connection storage capacitance Cst and
The common end of display capacitor Clc namely the pixel electrode；The source electrode of first film transistor T1 connects the second thin film transistor (TFT)
The drain electrode of T2；The source electrode of second thin film transistor (TFT) T2 connects data line SD；The grid connection first of first film transistor T1 is swept
Line G1 is retouched, the grid of the second thin film transistor (TFT) T2 connects the second scan line G2；Wherein, the scanning voltage letter on the first scan line G1
Number be less than or greater than the second scan line on scanning voltage signal.
Specifically, the scanning voltage signal on the first scan line G1 is different from the scanning voltage signal in the second scan line.
As shown in figure 4, the current potential of node Q ' is different from the current potential of node Q, so that first film transistor T1 and the second thin film transistor (TFT)
T2 is in different states, so that resistance (namely the source/drain of first film transistor T1 between node A and node B
Resistance between pole) RABNot equal between node B and node C resistance (namely the source/drain of the second thin film transistor (TFT) T2 it
Between resistance) RBC, so that the voltage V between node A and node BABNot equal to the voltage V between node B and node CBC,
Always there is the standoff voltage of a thin film transistor (TFT) to be less than 1/2 (V in this wayAB+VBC), such as by increasing in different scan lines
Different scanning voltage signal, so that RAB=1/4RBC, V at this timeAB=1/5VAC(it is assumed that VAC=5V) so, VAB=1V, namely
Voltage V between the drain/source of first film transistor T1dsFor 1V, corresponding leakage current is significantly less than thin in the prior art
The corresponding leakage current of voltage 2.5V between the drain-source of film transistor.
Optionally, it is scanned in the connected scan line of grid of i-th of thin film transistor (TFT) in n concatenated thin film transistor (TFT)s
Voltage signal (in the present embodiment namely the received scanning voltage signal of the grid of i-th of thin film transistor (TFT) institute) is less than j-th
Scanning voltage signal in the connected scan line of the grid of thin film transistor (TFT) is (in the present embodiment namely j-th of thin film transistor (TFT)
The received scanning voltage signal of grid institute), and i < j.Specifically, the grid institute by i-th of thin film transistor (TFT) is received
Scanning voltage signal is smaller, and passable carrier quantity is smaller in the unit time, defines n concatenated thin film transistor (TFT)s
Whole leakage current, by be arranged i < j so that can be by the lesser thin film transistor (TFT) of carrier quantity close to picture in the unit time
Plain electrode side ensure that the leakage current for flowing to pixel electrode is smaller, to reduce influence of the leakage current to display, improve
Display quality.
Illustratively, with continued reference to FIG. 4, the scanning voltage signal on the first scan line G1 is less than on the second scan line G2
Scanning voltage signal divide smaller, passable load in the unit time so that the resistance of first film transistor T1 is smaller
It is smaller to flow subnumber amount, to define the whole leakage current of concatenated two thin film transistor (TFT)s.And first film transistor T1 is leaned on
Nearly pixel electrode side, ensure that the leakage current for flowing to pixel electrode is smaller, reduces influence of the leakage current to display, improve
Display quality.
Fig. 5 is the corresponding equivalent pixel circuit figure of another array substrate provided in an embodiment of the present invention.Including scan line G
Intersect with data line SD, scan line G and data line SD insulation and limit multiple pixel units, pixel unit includes 2 concatenated thin
Film transistor and pixel electrode, illustratively, as shown in figure 5, pixel unit further includes display capacitor Clc and deposits in the present embodiment
Storage holds Cst, and display capacitor Clc and storage capacitance Cst is parallel with one another, and a pole plate of display capacitor Clc and storage capacitance Cst is
The pixel electrode.Wherein the drain electrode of first film transistor T1 is connect with pixel electrode, the source electrode of the second thin film transistor (TFT) T2
It is connected to a data line SD, for receiving data voltage signal.
The pixel unit further includes at least one sectional pressure element, described in the grid and one of i-th of thin film transistor (TFT)
Sectional pressure element connection, the sectional pressure element are connect with a scan line.The grid of i.e. i-th thin film transistor (TFT) and scan line it
Between further include sectional pressure element；And it should be noted that the grid of j-th of thin film transistor (TFT) can directly with the scan line phase
Even, can also be connected by sectional pressure element with the scan line.It should be noted that the grid phase with i-th of thin film transistor (TFT)
The voltage dividing ability of sectional pressure element even and the sectional pressure element being connected with the grid of j-th of thin film transistor (TFT) is not identical, so that
The grid of i-th of thin film transistor (TFT) received scanning voltage signal is received less than the grid of j-th thin film transistor (TFT) institute sweeps
Retouch voltage signal.
In the present embodiment, the sectional pressure element can be also possible to thin film transistor (TFT), not done in the present embodiment to this with resistance
It limits, optionally, the sectional pressure element includes at least one bleeder transistor, and the grid of at least one bleeder transistor is equal
Connect the scan line.And in the sectional pressure element described at least one bleeder transistor the scanning that connect of grid
Line is connect with the grid of j-th of thin film transistor (TFT), that is, the grid of j-th of thin film transistor (TFT) is directly and institute in the present embodiment
Scan line is stated to be connected.It should be noted that when in the sectional pressure element including multiple thin film transistor (TFT)s, multiple thin film transistor (TFT)s
It can connect, or in parallel, not limited this in the present embodiment.
As shown in figure 5, in the present embodiment optionally, sectional pressure element includes a bleeder transistor T0；Bleeder transistor T0
Grid be connected with its source electrode, and be connected to scan line G, the drain electrode of bleeder transistor T0 and the grid of first film transistor T1
It is connected.Due to the presence of bleeder transistor T0, so that the current potential of node Q ' is less than the current potential of node Q, so that the first film crystal
Pipe T1 and the second thin film transistor (TFT) T2 is in different states, so that the resistance (namely first between node A and node B
Resistance between the source/drain of thin film transistor (TFT) T1) RABLess than the resistance between node B and node C, (namely the second film is brilliant
Resistance between the source/drain of body pipe T2) RBC, voltage V between node A and node BABLess than between node B and node C
Voltage VBC, voltage V between the drain-source of first film transistor T1dsIt is brilliant that corresponding leakage current is significantly less than film in the prior art
1/2 (V between the drain-source of body pipeAB+VBC) corresponding leakage current.
Realize that the received scanning voltage signal of grid institute of i-th of thin film transistor (TFT) is small by sectional pressure element in the present embodiment
In the received scanning voltage signal of grid institute of j-th thin film transistor (TFT) so that the partial pressure of i-th of thin film transistor (TFT) compared with
Small, the negligible amounts of the carrier passed through in the unit time, i-th of thin film transistor (TFT) defines n concatenated thin film transistor (TFT)s
Whole leakage current, and then ensure that the display quality of picture.
It should be noted that it includes three concatenated thin for also providing a kind of array substrate pixel unit in the embodiment of the present invention
The drain electrode of film transistor and multi-strip scanning line and data line, first film transistor is electrically connected with pixel electrode, in this implementation
The pixel electrode is a public pole plate for showing capacitor and storage capacitance, the source electrode and data line of third thin film transistor (TFT) T3
Electrical connection；The grid of first film transistor received scanning voltage signal, the second thin film transistor (TFT) grid institute it is received
At least there is a scanning voltage letter in the received scanning voltage signal of the grid of scanning voltage signal and third thin film transistor (TFT) institute
It is number different from other two scanning voltage signals.
Optionally, as shown in fig. 6, being a kind of signal of the corresponding equivalent pixel circuit figure of array substrate in the present embodiment
Figure, the grid of first film transistor T1 are electrically connected the grid electrical connection second of the first scan line G1, the second thin film transistor (TFT) T2
Scan line G2, third thin film transistor (TFT) T3 grid be electrically connected third scan line G3, the first scan line G1, the second scan line G2 and
Apply different voltage signals respectively on third scan line G3, is swept so that the grid institute of first film transistor T1 is received
Retouch the grid of voltage signal, the second thin film transistor (TFT) T2 received scanning voltage signal and third thin film transistor (TFT) T3 grid
The received scanning voltage signal of institute is different.
It further optionally, can also be as shown in fig. 7, Fig. 7 be a kind of array base provided in an embodiment of the present invention in the present embodiment
Sectional pressure element in the corresponding equivalent pixel circuit figure of plate is the schematic diagram of multiple series connection bleeder transistors, wherein the first film
It include sectional pressure element T01 between the grid and scan line G of transistor T1, sectional pressure element T01 includes multiple thin film transistor (TFT)s, multiple
Thin film transistor (TFT) is serially connected, and also may include sectional pressure element T02 between the second thin film transistor (TFT) T2 and scan line G, partial pressure member
Part T02 can be thin film transistor (TFT), be also possible to resistance, without limiting in the present embodiment.In addition, sectional pressure element T02 can be with
Only include a thin film transistor (TFT), also may include multiple thin film transistor (TFT)s, in this implementation optionally, an only film crystal
Pipe.It should be noted that when sectional pressure element T02 includes multiple thin film transistor (TFT)s, it can be with the film crystal of sectional pressure element T01
Pipe number is identical, and structure is similar, can also be different setting.
As shown in figure 8, Fig. 8 is in the corresponding equivalent pixel circuit figure of another array substrate provided in an embodiment of the present invention
Sectional pressure element be multiple bleeder transistors in parallel schematic diagram, wherein multiple thin film transistor (TFT)s in sectional pressure element T01 ' are also
It can be arranged in parallel, likewise, also may include sectional pressure element T02 ' between the second thin film transistor (TFT) T2 and scan line G, partial pressure
Element T02 ' can be thin film transistor (TFT), be also possible to resistance, without limiting in the present embodiment.In addition, sectional pressure element T02 '
It can only include a thin film transistor (TFT), also may include multiple thin film transistor (TFT)s, in this implementation optionally, an only film
Transistor.It should be noted that when sectional pressure element T02 ' includes multiple thin film transistor (TFT)s, it can be thin with sectional pressure element T01 '
Film transistor number is identical, and structure is similar, can also be different setting.
It does not elaborate in the present embodiment to this, as long as partial pressure can be played the role of, can also set in series and parallel certainly
It sets.In addition, the sectional pressure element can also be resistance, equally without limiting in the present embodiment.
Fig. 7 and Fig. 8 are referred to, by the received scanning voltage signal of grid Q1 institute of first film transistor T1, second
The grid Q2 of thin film transistor (TFT) T2 the grid Q3 institute of received scanning voltage signal and third thin film transistor (TFT) T3 received sweep
Retouch voltage signal difference.VABNot equal to VBC, and it is not equal to VCD, always there is the standoff voltage of a thin film transistor (TFT) to be less than in this way
1/3(VAB+VBC+VCD), the small thin film transistor (TFT) of standoff voltage can limit three concatenated thin film transistor (TFT)s and flow to pixel electrode
Whole leakage current size.
Optionally, any film into m-th of thin film transistor (TFT) of the 1st in the n concatenated thin film transistor (TFT)s is brilliant
The grid of body pipe received scanning voltage signal be less than m+1 in the n concatenated thin film transistor (TFT) to n-th thin
The received scanning voltage signal of grid institute of any thin film transistor (TFT) in film transistor, m is positive integer, and 1≤m < n.It sets in this way
It sets, so that the side of close pixel electrode can be respectively positioned in the unit time by the lesser thin film transistor (TFT) of carrier quantity, into
One step ensure that smaller by the leakage current of pixel electrode, and then reduces influence of the leakage current to display, improves display product
Matter.
Optionally, the received scanning electricity of grid institute of the 1st thin film transistor (TFT) in the n concatenated thin film transistor (TFT)s
Signal is pressed to be less than the received scanning voltage signal of grid institute of other thin film transistor (TFT)s, in this way, making the 1st film crystal
The partial pressure of pipe is minimum, and the quantity of the carrier passed through in the unit time is minimum, and the 1st thin film transistor (TFT) is defined is connected by n
Thin film transistor (TFT) flow to pixel electrode whole leakage current size, directly and pixel electrode due to the 1st thin film transistor (TFT)
Electrical connection ensure that the leakage current passed through in pixel electrode is minimum.It should be noted that the grid of other thin film transistor (TFT)s is connect
The scanning voltage signal of receipts can be identical, can not also be identical, does not limit this in the present embodiment.
Optionally, the received scanning electricity of grid institute of n-th of thin film transistor (TFT) in the n concatenated thin film transistor (TFT)s
Signal is pressed to be greater than the received scanning voltage signal of grid institute of other thin film transistor (TFT)s.In this way, making n-th of film crystal
Pipe partial pressure is maximum, in the unit time can by carrier it is most, be easy to be affected by other factors the electric leakage for causing to flow through
Stream increases, and by n-th of thin film transistor (TFT) of setting far from pixel electrode, avoids the influence of other factors, ensure that and flow through picture
The leakage current of plain electrode is smaller.It should be noted that the received scanning voltage signal of grid institute of other thin film transistor (TFT)s can be with
It is identical, can not also be identical, it is not limited this in the present embodiment.
Optionally, n concatenated thin film transistor (TFT)s are low-temperature polysilicon film transistor.Specifically, low temperature polycrystalline silicon is thin
Film transistor electron transfer rate with higher ensure that pixel unit has so that the reaction speed of thin film transistor (TFT) is exceedingly fast
There is faster charge/discharge speed；Furthermore such that area occupied of the thin film transistor (TFT) in pixel unit can do it is smaller, thinner,
On the one hand display panel power consumption can be reduced, on the other hand, ensure that pixel unit aperture opening ratio with higher.
It should be noted that above embodiment only carries out the present invention by taking the array substrate of liquid crystal display panel as an example
Illustrate, not limitation of the invention, the present disclosure additionally applies for organic light emitting display panels.In addition, the present embodiment is only with two
The present invention is described for thin film transistor (TFT) series connection and three thin film transistor (TFT) series connection, not limitation of the invention.
The embodiment of the invention also provides a kind of display panel, Fig. 9 is a kind of display panel provided in an embodiment of the present invention
Schematic diagram, with reference to Fig. 9, the display panel includes array substrate 100 described in any embodiment of that present invention.
Optionally, the display panel further includes the color membrane substrates 300 being oppositely arranged with array substrate 100, and setting
Liquid crystal layer 200 between array substrate 100 and color membrane substrates 300.Black matrix, the n string are provided on color membrane substrates 300
The thin film transistor (TFT) of connection is located in the black matrix in the orthographic projection of color membrane substrates 300.
Optionally, the picture refreshing frequency range of the display panel is 0.5Hz-45Hz, when picture refreshing frequency is greater than
When 45Hz, biggish power consumption can be brought, causes the loss of resource and energy, and display panel provided by the invention, by above-mentioned
Structure design in embodiment, can be effectively reduced the picture refreshing frequency of display panel, while display panel is existed
Still there is stable display picture, to reduce while guaranteeing image display quality with higher under lower frequency
The power consumption of display panel.
The embodiment of the invention also provides a kind of display device, Figure 10 is a kind of display device provided in an embodiment of the present invention
Schematic diagram, with reference to Figure 10, display device 400 includes display panel 500, and display panel 500 includes any embodiment of that present invention
The array substrate, wherein display device 400 can be mobile phone as illustrated in the drawing, or computer, television set, intelligence
Display device etc. can be dressed, the present embodiment is not particularly limited this.
It should be noted that all the embodiments in this specification are described in a progressive manner, each embodiment weight
Point explanation is the difference from other embodiments, and the same or similar parts between the embodiments can be referred to each other.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (17)
1. a kind of array substrate, comprising:
Scan line and data line, the scan line is intersected with data line insulation limits multiple pixel units, the pixel list
Member includes n concatenated thin film transistor (TFT)s and pixel electrode；
The drain electrode of the 1st thin film transistor (TFT) in the n concatenated thin film transistor (TFT)s is connect with the pixel electrode, and n-th
The source electrode of thin film transistor (TFT) is connected to a data line, for receiving data voltage signal；
The grid of each thin film transistor (TFT) in the n concatenated thin film transistor (TFT)s receives a scanning voltage signal；
It is characterized in that, n is positive integer, and n≤2；The received scanning voltage signal of grid institute of i-th of thin film transistor (TFT) is less than
The received scanning voltage signal of grid institute of j-th of thin film transistor (TFT), i, j are positive integer, 1≤i≤n, 1≤j≤n, and i ≠ j.
2. array substrate according to claim 1, which is characterized in that the pixel unit further include display capacitor and/or
One pole plate of storage capacitance, the display capacitor and/or the storage capacitance is the pixel electrode.
3. array substrate according to claim 1, which is characterized in that i-th of film in the n thin film transistor (TFT) is brilliant
The grid of body pipe is connected with a scan line, and the grid of j-th of thin film transistor (TFT) is connected with another scan line.
4. array substrate according to claim 1, which is characterized in that the pixel unit further includes at least one partial pressure member
Part, the grid of i-th of thin film transistor (TFT) are connect with a sectional pressure element, and the sectional pressure element and a scan line connect
It connects.
5. array substrate according to claim 4, which is characterized in that the sectional pressure element includes at least one partial pressure crystal
Pipe, the grid of at least one bleeder transistor are all connected with the scan line.
6. array substrate according to claim 5, which is characterized in that in the sectional pressure element described at least one point
The scan line of the grid connection of piezoelectric crystal is connect with the grid of j-th of thin film transistor (TFT).
7. array substrate according to claim 5, which is characterized in that include that at least two partial pressures are brilliant in the sectional pressure element
Body pipe, at least two bleeder transistor are serially connected or parallel with one another.
8. array substrate according to claim 5, which is characterized in that include a partial pressure crystal in the sectional pressure element
Pipe, the grid of i-th of thin film transistor (TFT) connect with the drain electrode of the bleeder transistor, the source electrode of the bleeder transistor and
Grid is connected.
9. array substrate according to any one of claims 1 to 8, which is characterized in that the n concatenated film crystals
The received scanning voltage signal of grid institute of the 1st any thin film transistor (TFT) into m-th of thin film transistor (TFT) in pipe is less than institute
The grid for stating the m+1 in n concatenated thin film transistor (TFT)s thin film transistor (TFT) any into n-th of thin film transistor (TFT) is received
Scanning voltage signal, m is positive integer, and 1≤m < n.
10. array substrate according to any one of claims 1 to 8, which is characterized in that the n concatenated film crystals
The grid of the 1st thin film transistor (TFT) in pipe received scanning voltage signal be less than other thin film transistor (TFT)s grid received
Scanning voltage signal, the received scanning voltage signal of grid institute of other thin film transistor (TFT)s is identical.
11. array substrate according to any one of claims 1 to 8, which is characterized in that the n concatenated film crystals
The grid of n-th of thin film transistor (TFT) in pipe received scanning voltage signal be greater than other thin film transistor (TFT)s grid received
Scanning voltage signal, the received scanning voltage signal of grid institute of other thin film transistor (TFT)s is identical.
12. array substrate according to any one of claims 1 to 8, which is characterized in that the n concatenated film crystals
The grid of i-th of thin film transistor (TFT) in pipe received scanning voltage signal connect less than the grid of j-th of thin film transistor (TFT)
The scanning voltage signal of receipts, and i < j.
13. array substrate according to claim 1, which is characterized in that the n concatenated thin film transistor (TFT)s are that low temperature is more
Polycrystal silicon film transistor.
14. a kind of display panel, which is characterized in that including the described in any item array substrates of claim 1-13.
15. display panel according to claim 14, which is characterized in that further include:
The color membrane substrates being oppositely arranged with the array substrate；
Black matrix, orthographic projection of the n concatenated thin film transistor (TFT)s in the color membrane substrates are provided on the color membrane substrates
In the black matrix.
16. display panel according to claim 14, which is characterized in that the picture refreshing frequency of the display panel is
0.5Hz-45Hz, including endpoint value.
17. a kind of display device, which is characterized in that including the described in any item display panels of claim 14-16.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611076298.XA CN106526996B (en) | 2016-11-29 | 2016-11-29 | Array substrate, display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611076298.XA CN106526996B (en) | 2016-11-29 | 2016-11-29 | Array substrate, display panel and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106526996A CN106526996A (en) | 2017-03-22 |
| CN106526996B true CN106526996B (en) | 2019-06-28 |
Family
ID=58355155
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611076298.XA Active CN106526996B (en) | 2016-11-29 | 2016-11-29 | Array substrate, display panel and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106526996B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107425013B (en) | 2017-05-11 | 2018-11-16 | 成都京东方光电科技有限公司 | Dot structure, array substrate and display device |
| CN106990574B (en) * | 2017-06-02 | 2021-02-02 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof, display device and driving method thereof |
| CN107170405B (en) * | 2017-07-24 | 2020-08-18 | 京东方科技集团股份有限公司 | Circuit driving method and apparatus, electronic apparatus, storage medium, and display device |
| CN109917595B (en) * | 2017-12-12 | 2021-01-22 | 京东方科技集团股份有限公司 | Pixel structure, driving method thereof, display panel and display device |
| CN110794631B (en) | 2019-11-21 | 2022-09-30 | 京东方科技集团股份有限公司 | Sub-pixel structure, liquid crystal panel and reflective liquid crystal display device |
| CN113035117A (en) * | 2021-03-15 | 2021-06-25 | 京东方科技集团股份有限公司 | Array substrate, driving method thereof and display device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20050043410A (en) * | 2003-11-06 | 2005-05-11 | 삼성전자주식회사 | Switching element for driving circuit of liquid crystal display |
| CN101144947A (en) * | 2007-10-18 | 2008-03-19 | 上海广电光电子有限公司 | Vertical orientation mode liquid crystal display device |
| CN201097057Y (en) * | 2007-10-18 | 2008-08-06 | 上海广电光电子有限公司 | LCD device with vertical direction mode |
| CN102169668A (en) * | 2010-02-25 | 2011-08-31 | 索尼公司 | Pixel circuit, liquid-crystal device, and electronic device |
| CN104635396A (en) * | 2015-03-13 | 2015-05-20 | 京东方科技集团股份有限公司 | Pixel structure, array substrate, liquid crystal panel and pixel driving method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1331627B1 (en) * | 2002-01-24 | 2012-04-18 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of driving the semiconductor device |
-
2016
- 2016-11-29 CN CN201611076298.XA patent/CN106526996B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20050043410A (en) * | 2003-11-06 | 2005-05-11 | 삼성전자주식회사 | Switching element for driving circuit of liquid crystal display |
| CN101144947A (en) * | 2007-10-18 | 2008-03-19 | 上海广电光电子有限公司 | Vertical orientation mode liquid crystal display device |
| CN201097057Y (en) * | 2007-10-18 | 2008-08-06 | 上海广电光电子有限公司 | LCD device with vertical direction mode |
| CN102169668A (en) * | 2010-02-25 | 2011-08-31 | 索尼公司 | Pixel circuit, liquid-crystal device, and electronic device |
| CN104635396A (en) * | 2015-03-13 | 2015-05-20 | 京东方科技集团股份有限公司 | Pixel structure, array substrate, liquid crystal panel and pixel driving method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106526996A (en) | 2017-03-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106526996B (en) | Array substrate, display panel and display device | |
| CN105321462B (en) | Show equipment | |
| US9041453B2 (en) | Pulse generation circuit and semiconductor device | |
| US6600472B1 (en) | Liquid crystal display device | |
| US8633889B2 (en) | Display device, driving method thereof, and electronic appliance | |
| CN103927984B (en) | The pixel-driving circuit and its driving method of a kind of OLED display | |
| CN108281124A (en) | Shift register cell and its driving method, gate driving circuit and display device | |
| CN101750813B (en) | Liquid crystal display and control method thereof | |
| CN105047161B (en) | Pixel unit driving device, method and display device | |
| CN104537989B (en) | The charge share-type pixel structure and its driving method of a kind of bilateral scanning | |
| CN103035201B (en) | Organic light-emitting diode pixel circuit, driving method and display panel thereof | |
| TW588320B (en) | Liquid crystal display | |
| TW200837695A (en) | Liquid crystal display and pulse adjustment circuit thereof | |
| CN104376826B (en) | Shifting register unit, grid driving circuit and displaying device | |
| CN105047155B (en) | Liquid crystal display device and its GOA scanning circuits | |
| CN106252363A (en) | Array base palte, display floater and display device | |
| US20210201838A1 (en) | Driving method of display device and display device | |
| KR20110081637A (en) | Switching apparatus for active display device and method of driving the same | |
| CN104464680B (en) | A kind of array base palte and display device | |
| CN103761938B (en) | Shift register cell, shift register, array base palte and display device | |
| CN108777130A (en) | Pixel circuit and display device | |
| CN105405415A (en) | Display Device And Display Method Thereof For Compensating Pixel Voltage Loss | |
| CN109658881A (en) | Shift register and the display device for having shift register | |
| CN104062824A (en) | Pixel structure and display panel with same | |
| CN107342048A (en) | Image element circuit and its driving method, display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |