CN106526996A - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
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- CN106526996A CN106526996A CN201611076298.XA CN201611076298A CN106526996A CN 106526996 A CN106526996 A CN 106526996A CN 201611076298 A CN201611076298 A CN 201611076298A CN 106526996 A CN106526996 A CN 106526996A
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- thin film
- film transistor
- tft
- grid
- voltage signal
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
- G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels
Abstract
The invention discloses an array substrate, a display panel and a display device. The array substrate comprises a scanning line and a data line. The scanning line and the data line are intercrossed in an insulated mode to define a plurality of pixel units. Each pixel unit comprises n tandem thin film transistors and a pixel electrode, wherein n is a positive integer and larger than or equal to 2. The drain electrode of the first thin film transistor in the n tandem thin film transistors is connected with the pixel electrode. The source electrode of the nth thin film transistor in the n tandem thin film transistors is connected to the data line and used for receiving data voltage signals. The grid electrode of each thin film transistor in the n tandem thin film transistors receives a scanning voltage signal, wherein the scanning voltage signal received by the grid electrode of the ith thin film transistor is smaller than the scanning voltage signal received by the grid electrode of the jth thin film transistor, i and j are both positive integers, i is larger than or equal to 1 and smaller than or equal to n, j is larger than or equal to 1 and smaller than or equal to n, and i is unequal to j. According to the array substrate, the display panel and the display device, leak currents of the display panel are decreased, and the display quality is improved.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of array base palte, display floater and display device.
Background technology
Image element circuit of the prior art is as shown in figure 1, Fig. 1 shows for a thin film transistor (TFT) control pixel in prior art
The image element circuit for showing；The image element circuit include storage capacitance Cst, show electric capacity Clc, thin film transistor (TFT) T1 and scan line G with
And data wire SD, wherein electric capacity Clc is in parallel for storage capacitance Cst, display, one common port connection public voltage signal source Vcom,
Another common port connects the drain electrode of thin film transistor (TFT) T1；Second end of thin film transistor (TFT) T1 is connected with data wire SD；Film crystal
The grid of pipe T1 is connected with scan line G, and thin film transistor (TFT) T1 is used for the display for controlling display.
During the display of display keeps, storage capacitance Cst carries out electric discharge and keeps showing.But as thin film transistor (TFT) is deposited
Larger leakage current (i.e. there is leakage current between AC nodes in Fig. 1), and the display quality of display is affected, particularly with low
When frequency shows, show longer during keeping, the impact of leakage current becomes apparent from.
The content of the invention
In view of this, the present invention provides a kind of array base palte, display floater and display device, to solve picture in prior art
Leakage current in plain circuit is larger, affects larger problem to display quality.
For achieving the above object, the present invention provides following technical scheme：
A kind of array base palte, including：
Scan line and data wire, the scan line intersect the multiple pixel cells of restriction, the picture with data wire insulation
Plain unit includes the thin film transistor (TFT) and pixel electrode of n series connection, wherein, n is positive integer, and n 2；
The drain electrode of the 1st thin film transistor (TFT) in the thin film transistor (TFT) of the n series connection is connected with the pixel electrode, the
The source electrode of n thin film transistor (TFT) is connected to data wire described in, for receiving data voltage signal；
The grid of each thin film transistor (TFT) in the thin film transistor (TFT) of the n series connection receives scan voltage signal, its
In, scanning voltage signal that the grid of i-th thin film transistor (TFT) is received is received less than the grid of j-th thin film transistor (TFT)
Scanning voltage signal, i, j are positive integer, 1≤i≤n, 1≤j≤n, and i ≠ j.
Present invention also offers a kind of display floater, the display floater includes array base palte recited above.
In addition, present invention also offers a kind of display device, the display device includes display floater recited above.
Understand via above-mentioned technical scheme, the pixel cell of the array base palte that the present invention is provided includes n series connection
Thin film transistor (TFT) and pixel electrode, the grid of each thin film transistor (TFT) in the thin film transistor (TFT) of the n series connection are received and are swept
Voltage signal is retouched, wherein, the scanning voltage signal received by the grid of i-th thin film transistor (TFT) is less than j-th thin film transistor (TFT)
The scanning voltage signal that received of grid, i, j are positive integer, 1≤i≤n, 1≤j≤n, and i ≠ j.I.e. by arranging i-th
The scanning voltage signal received by the grid of thin film transistor (TFT) is less than the scanning voltage received by the grid of j-th thin film transistor (TFT)
Signal so that the standoff voltage of the thin film transistor (TFT) of n series connection is differed, and the standoff voltage of i-th thin film transistor (TFT) is less than
Originally the standoff voltage of thin film transistor (TFT), so as to reduce the leakage current by i-th thin film transistor (TFT), and then reduces n
The leakage current of the thin film transistor (TFT) of series connection, and then impact of the leakage current to showing is reduced, improve display quality.
Description of the drawings
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
Accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are only this
Inventive embodiment, for those of ordinary skill in the art, on the premise of not paying creative work, can be with basis
The accompanying drawing of offer obtains other accompanying drawings.
The image element circuit that Fig. 1 is shown for a thin film transistor (TFT) control pixel in prior art；
The image element circuit that Fig. 2 is shown for two thin film transistor (TFT)s control pixels in prior art；
Fig. 3 A are the ID-VG characteristic curves of single a-Si thin film transistor (TFT)s；
Fig. 3 B are the ID-VG characteristic curves of single LTPS thin film transistor (TFT)s；
Fig. 4 is a kind of schematic diagram of the corresponding equivalent pixel circuit figure of array base palte provided in an embodiment of the present invention；
Fig. 5 is the schematic diagram of the corresponding equivalent pixel circuit figure of another array base palte provided in an embodiment of the present invention；
Fig. 6 is the schematic diagram of the corresponding equivalent pixel circuit figure of another array base palte provided in an embodiment of the present invention；
Fig. 7 is that the sectional pressure element in a kind of corresponding equivalent pixel circuit figure of array base palte provided in an embodiment of the present invention is
The schematic diagram of multiple series connection bleeder transistors；
Fig. 8 is the sectional pressure element in the corresponding equivalent pixel circuit figure of another array base palte provided in an embodiment of the present invention
For the schematic diagram of multiple bleeder transistors in parallel；
Fig. 9 is a kind of schematic diagram of display floater provided in an embodiment of the present invention；
Figure 10 is a kind of schematic diagram of display device provided in an embodiment of the present invention.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than the embodiment of whole.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
The image element circuit that Fig. 2 is shown for two thin film transistor (TFT)s control pixels in prior art, image element circuit shown in Fig. 2,
Connect than image element circuit shown in Fig. 1 a thin film transistor (TFT) T2 more, and the grid of thin film transistor (TFT) T1 and thin film transistor (TFT) T2 is simultaneously
It is connected in scan line G1, receives with scan voltage signal, for controlling the display of display.But similarly, due to thin film
There is larger leakage current (i.e. there is leakage current between AC nodes in Fig. 2) in transistor, and affect the display quality of display, especially
Its for low frequency show when, show keep during it is longer, the impact of leakage current becomes apparent from.
Fig. 3 A and Fig. 3 B are referred to, Fig. 3 A are the ID-VG characteristic curves of single a-Si thin film transistor (TFT)s, work as thin film transistor (TFT)
Drain-source between voltage VDS when keeping constant, the relation of leakage current ID and gate source voltage VGS, as can be seen that right from Fig. 3 A
Definite value is taken in VGS, during such as -10V (standoff voltage of a-Si thin film transistor (TFT)s is generally -10V), the leakage current ID of thin film transistor (TFT)
Reduce with the reduction of drain-source voltage VDS；Fig. 3 B are single LTPS (low temperature polycrystalline silicon, Low Temperature Ploy
Silicon) the ID-VG characteristic curves of thin film transistor (TFT), it can also be seen that for VGS takes definite value from Fig. 3 B, such as -4V (LTPS
The standoff voltage of thin film transistor (TFT) is generally -4V) when, the leakage current ID of thin film transistor (TFT) is dropped with the reduction of drain-source voltage VDS
It is low.
Therefore, it can by the drain-source voltage VDS of reduction thin film transistor (TFT) reduce the leakage current of thin film transistor (TFT).This
It is bright based on above-mentioned principle, there is provided a kind of array base palte, the array base palte include：
Scan line and data wire, the scan line intersect the multiple pixel cells of restriction, the picture with data wire insulation
Plain unit includes the thin film transistor (TFT) and pixel electrode of n series connection, wherein, n is positive integer, and n 2；
The drain electrode of the 1st thin film transistor (TFT) in the thin film transistor (TFT) of the n series connection is connected with the pixel electrode, the
The source electrode of n thin film transistor (TFT) is connected to data wire described in, for receiving data voltage signal；
The grid of each thin film transistor (TFT) in the thin film transistor (TFT) of the n series connection receives scan voltage signal, its
In, scanning voltage signal that the grid of i-th thin film transistor (TFT) is received is received less than the grid of j-th thin film transistor (TFT)
Scanning voltage signal, i, j are positive integer, 1≤i≤n, 1≤j≤n, and i ≠ j.
The embodiment of the present invention is less than jth by arranging the scanning voltage signal received by the grid of i-th thin film transistor (TFT)
The scanning voltage signal received by the grid of individual thin film transistor (TFT) so that the standoff voltage not phase of the thin film transistor (TFT) of n series connection
Together, the source and drain electrode resistance of i-th thin film transistor (TFT) is made less than the source and drain electrode resistance of j-th thin film transistor (TFT) so that i-th
The partial pressure of thin film transistor (TFT) reduces, so that the carrier quantity passed through in the unit interval in i-th thin film transistor (TFT) is reduced,
The leakage current by i-th thin film transistor (TFT) is reduced, so as to reduce the leakage current of the thin film transistor (TFT) of n series connection, and then
Impact of the leakage current to showing is reduced, display quality is improve.
It should be noted that the present invention not limit the scanning voltage signal received by the grid of i-th thin film transistor (TFT) little
The specific implementation of the scanning voltage signal received in the grid of j-th thin film transistor (TFT), can make each film crystal
The grid of pipe is all connected with a scan line, realizes that i-th thin film is brilliant by increasing different scanning voltage signals in scan line
The scanning voltage signal received by the grid of body pipe is less than the scanning voltage signal received by the grid of j-th thin film transistor (TFT),
The grid of i-th thin film transistor (TFT) in i.e. described n thin film transistor (TFT) is connected with scan line described in, j-th film crystal
The grid of pipe is connected with another scan line, and in this two scan lines, added scanning voltage signal is different so that i-th thin film
Scanning voltage signal in the connected scan line of grid of transistor is less than in the connected scan line of grid of j-th thin film transistor (TFT)
Scanning voltage signal.
Can also be by the grid in i-th thin-film transistor gate and j-th thin film transistor (TFT) and identical scan line
Between increase the scanning voltage signal that different sectional pressure elements realize that the grid of i-th thin film transistor (TFT) received and be less than j-th
The scanning voltage signal received by the grid of thin film transistor (TFT).Increase such as between i-th thin-film transistor gate and scan line
The larger sectional pressure element of voltage dividing ability, and then the scanning voltage signal received by the grid of i-th thin film transistor (TFT) is less than
The scanning voltage signal received by the grid of j-th thin film transistor (TFT).
The present invention is introduced by taking two thin film crystalline substance pipe series connection as an example below, Fig. 4 is provided in an embodiment of the present invention one
The schematic diagram of the corresponding equivalent pixel circuit figure of array base palte is planted, the array base palte includes：
Scan line and data wire SD, scan line intersect the multiple pixel cells of restriction, pixel cell bag with data wire SD insulation
Include the thin film transistor (TFT) and pixel electrode of two series connection；In the present embodiment, pixel cell can also include showing electric capacity and/or deposit
Storing up electricity is held, and a pole plate of display electric capacity and/or storage capacitance is pixel electrode.
Normal conditions, as shown in figure 4, Fig. 4 is the corresponding equivalent pixel circuit of array base palte provided in an embodiment of the present invention
The schematic diagram of figure, pixel cell include showing electric capacity Clc and storage capacitance Cst simultaneously, and show that electric capacity and storage capacitance are mutual
One pole plate of parallel connection, display electric capacity Clc and storage capacitance Cst is pixel electrode.
Two series connection thin film transistor (TFT)s as shown in figure 4, first film transistor T1 drain electrode connection storage capacitance Cst and
Show the common port of electric capacity Clc, namely the pixel electrode；The source electrode of first film transistor T1 connects the second thin film transistor (TFT)
The drain electrode of T2；The source electrode connection data wire SD of the second thin film transistor (TFT) T2；The grid connection first of first film transistor T1 is swept
Line G1 is retouched, the grid of the second thin film transistor (TFT) T2 connects the second scan line G2；Wherein, the scanning voltage letter in the first scan line G1
Number less than or greater than the scanning voltage signal in the second scan line.
Specifically, the scanning voltage signal in the first scan line G1 is different from the scanning voltage signal in the second scan line.
As shown in figure 4, the current potential of node Q ' is different from the current potential of node Q so that first film transistor T1 and the second thin film transistor (TFT)
T2 is in different states, so that resistance between node A and node B (namely the source/drain of first film transistor T1
Resistance between pole) RABBe not equal to resistance between node B and node C (namely the source/drain of the second thin film transistor (TFT) T2 it
Between resistance) RBC, and then cause the voltage V between node A and node BABThe voltage V being not equal between node B and node CBC,
So always there is the standoff voltage of a thin film transistor (TFT) to be less than 1/2 (VAB+VBC), such as by increasing in different scan lines
Different scanning voltage signal so that RAB=1/4RBC, now VAB=1/5VAC(it is assumed that VAC=5V) so, VAB=1V, namely
Voltage V between the drain/source of first film transistor T1dsFor 1V, its corresponding leakage current is significantly less than thin in prior art
The corresponding leakage currents of voltage 2.5V between the drain-source of film transistor.
Optionally, scan in the connected scan line of grid of i-th thin film transistor (TFT) in the thin film transistor (TFT) of n series connection
The voltage signal scanning voltage signal that received of grid of i-th thin film transistor (TFT) (in the present embodiment, namely) is less than j-th
Scanning voltage signal in the connected scan line of grid of thin film transistor (TFT) is (in the present embodiment, namely j-th thin film transistor (TFT)
The scanning voltage signal that received of grid), and i<j.Specifically, received due to the grid of i-th thin film transistor (TFT)
Scanning voltage signal is less, and the carrier quantity that can pass through in its unit interval is less, defines the thin film transistor (TFT) of n series connection
Overall leakage current, by arrange i<J so that can be by the less thin film transistor (TFT) of carrier quantity near picture in the unit interval
Plain electrode side, it is ensured that the leakage current for flowing to pixel electrode is less, so as to reduce impact of the leakage current to showing, improves
Display quality.
Exemplary, please continue to refer to Fig. 4, the scanning voltage signal in the first scan line G1 is less than in the second scan line G2
Scanning voltage signal so that the resistance of first film transistor T1 is less, and partial pressure is less, the load that can pass through in its unit interval
Stream quantum count is less, so as to define the overall leakage current of two thin film transistor (TFT)s of series connection.And first film transistor T1 is leaned on
Nearly pixel electrode side, it is ensured that the leakage current for flowing to pixel electrode is less, reduces impact of the leakage current to showing, improves
Display quality.
Fig. 5 is the corresponding equivalent pixel circuit figure of another array base palte provided in an embodiment of the present invention.Including scan line G
With data wire SD, scan line G and data wire SD insulation intersects the multiple pixel cells of restriction, pixel cell include 2 connect it is thin
Film transistor and pixel electrode, it is exemplary, as shown in figure 5, pixel cell also includes showing electric capacity Clc and deposits in the present embodiment
Storing up electricity holds Cst, shows that electric capacity Clc and storage capacitance Cst are parallel with one another, and a pole plate of display electric capacity Clc and storage capacitance Cst is
The pixel electrode.The drain electrode of wherein first film transistor T1 is connected with pixel electrode, the source electrode of the second thin film transistor (TFT) T2
A data wire SD is connected to, for receiving data voltage signal.
The pixel cell also includes at least one sectional pressure element, described in the grid of i-th thin film transistor (TFT) and
Sectional pressure element connects, and the sectional pressure element is connected with scan line described in.That is the grid of i-th thin film transistor (TFT) and scan line it
Between also include sectional pressure element；And it should be noted that the grid of j-th thin film transistor (TFT) can directly with the scan line phase
Even, it is also possible to be connected with the scan line by sectional pressure element.It should be noted that the grid phase with i-th thin film transistor (TFT)
The voltage dividing ability of sectional pressure element even and the sectional pressure element being connected with the grid of j-th thin film transistor (TFT) is differed, so that
Grid sweeping of being received of the scanning voltage signal received by the grid of i-th thin film transistor (TFT) less than j-th thin film transistor (TFT)
Retouch voltage signal.
In the present embodiment, the sectional pressure element can not be done to this in the present embodiment with resistance, or thin film transistor (TFT)
Limit, alternatively, the sectional pressure element includes at least one bleeder transistor, and the grid of at least one bleeder transistor is equal
Connect the scan line.And the scanning being connected with the grid of at least one bleeder transistor in the sectional pressure element
Line is connected with the grid of j-th thin film transistor (TFT), i.e. in the present embodiment, the grid of j-th thin film transistor (TFT) is directly and institute
State scan line to be connected.It should be noted that when the sectional pressure element includes multiple thin film transistor (TFT)s, multiple thin film transistor (TFT)s
Can connect, or it is in parallel, this is not limited in the present embodiment.
As shown in figure 5, in the present embodiment alternatively, sectional pressure element includes a bleeder transistor T0；Bleeder transistor T0
Grid be connected with its source electrode, and be connected to scan line G, the drain electrode of bleeder transistor T0 and the grid of first film transistor T1
It is connected.Due to the presence of bleeder transistor T0 so that current potential of the current potential of node Q ' less than node Q so that the first film crystal
Pipe T1 and the second thin film transistor (TFT) T2 is in different states, so that resistance between node A and node B (namely first
Resistance between the source/drain of thin film transistor (TFT) T1) RABLess than the resistance between node B and node C, (namely the second thin film is brilliant
Resistance between the source/drain of body pipe T2) RBC, the voltage V between node A and node BABLess than between node B and node C
Voltage VBC, voltage V between the drain-source of first film transistor T1dsDuring corresponding leakage current is significantly less than prior art, thin film is brilliant
1/2 (V between the drain-source of body pipeAB+VBC) corresponding leakage current.
Realize that the scanning voltage signal received by the grid of i-th thin film transistor (TFT) is little by sectional pressure element in the present embodiment
In the scanning voltage signal received by the grid of j-th thin film transistor (TFT) so that the partial pressure of i-th thin film transistor (TFT) compared with
Little, the negligible amounts of the carrier passed through in the unit interval, i-th thin film transistor (TFT) define the thin film transistor (TFT) of n series connection
Overall leakage current, and then ensure that the display quality of picture.
It should be noted that a kind of array base palte pixel cell is also provided in the embodiment of the present invention includes the thin of three series connection
Film transistor and multi-strip scanning line, and data wire, the drain electrode of first film transistor are electrically connected with pixel electrode, in this enforcement
The pixel electrode is a public pole plate for showing electric capacity and storage capacitance, the source electrode and data wire of the 3rd thin film transistor (TFT) T3
Electrical connection；Scanning voltage signal that the grid of first film transistor is received, the grid of the second thin film transistor (TFT) are received
At least there is a scanning voltage letter in the scanning voltage signal received by the grid of scanning voltage signal and the 3rd thin film transistor (TFT)
It is number different from other two scanning voltage signals.
Alternatively, as shown in fig. 6, for a kind of signal of the corresponding equivalent pixel circuit figure of array base palte in the present embodiment
Figure, the grid of first film transistor T1 electrically connect the grid electrical connection second of the first scan line G1, the second thin film transistor (TFT) T2
Scan line G2, the 3rd thin film transistor (TFT) T3 grid electrical connection three scan line G3, the first scan line G1, the second scan line G2 and
Apply different voltage signals on three scan line G3 respectively, so that sweeping of being received of the grid of first film transistor T1
Retouch the grid of voltage signal, the scanning voltage signal received by the grid of the second thin film transistor (TFT) T2 and the 3rd thin film transistor (TFT) T3
The scanning voltage signal for being received is different.
Further optionally, can also be as shown in fig. 7, Fig. 7 be a kind of array base provided in an embodiment of the present invention in the present embodiment
Sectional pressure element in the corresponding equivalent pixel circuit figure of plate is the schematic diagram of multiple series connection bleeder transistors, wherein, the first film
Include sectional pressure element T01 between the grid and scan line G of transistor T1, sectional pressure element T01 includes multiple thin film transistor (TFT)s, multiple
Thin film transistor (TFT) is serially connected, and can also include sectional pressure element T02, partial pressure unit between the second thin film transistor (TFT) T2 and scan line G
Part T02 can be thin film transistor (TFT), or resistance, not be defined in the present embodiment.In addition, sectional pressure element T02 can be with
Only include a thin film transistor (TFT), it is also possible to including multiple thin film transistor (TFT)s, in this enforcement alternatively, only one film crystal
Pipe.It should be noted that when sectional pressure element T02 includes multiple thin film transistor (TFT)s, can be with the film crystal of sectional pressure element T01
Pipe number is identical, and structure is similar, it is also possible to different to arrange.
As shown in figure 8, during Fig. 8 is the corresponding equivalent pixel circuit figure of another array base palte provided in an embodiment of the present invention
Sectional pressure element be multiple bleeder transistors in parallel schematic diagram, wherein, the multiple thin film transistor (TFT)s in sectional pressure element T01 ' are also
Can be arranged in parallel, likewise, sectional pressure element T02 ', partial pressure can also be included between the second thin film transistor (TFT) T2 and scan line G
Element T02 ' can be thin film transistor (TFT), or resistance, not be defined in the present embodiment.In addition, sectional pressure element T02 '
A thin film transistor (TFT) can only be included, it is also possible to including multiple thin film transistor (TFT)s, in this enforcement alternatively, only one thin film
Transistor.It should be noted that when sectional pressure element T02 ' is including multiple thin film transistor (TFT)s, can be thin with sectional pressure element T01 '
Film transistor number is identical, and structure is similar, it is also possible to different to arrange.
This is not elaborated in the present embodiment, as long as partial pressure effect can be played, can be set with connection in series-parallel certainly
Put.In addition, the sectional pressure element can also be resistance, equally it is not defined in the present embodiment.
Fig. 7 and Fig. 8 is referred to, the scanning voltage signal that received due to the grid Q1 of first film transistor T1, second
What the scanning voltage signal and the grid Q3 of the 3rd thin film transistor (TFT) T3 received by the grid Q2 of thin film transistor (TFT) T2 was received sweeps
Retouch voltage signal different.VABIt is not equal to VBC, and it is not equal to VCD, the standoff voltage for so always having a thin film transistor (TFT) is less than
1/3(VAB+VBC+VCD), the little thin film transistor (TFT) of standoff voltage can limit the thin film transistor (TFT) of three series connection and flow to pixel electrode
Overall leakage current size.
Optionally, the 1st in the thin film transistor (TFT) of the n series connection is brilliant to arbitrary thin film in m-th thin film transistor (TFT)
The scanning voltage signal received by the grid of body pipe is less than m+1 in the thin film transistor (TFT) of described n series connection to thin n-th
In the film transistor scanning voltage signal received by the grid of arbitrary thin film transistor (TFT), m is positive integer, and 1≤m ＜ n.So set
Put so that can be respectively positioned near the side of pixel electrode by the less thin film transistor (TFT) of carrier quantity in the unit interval, be entered
One step ensure that it is less by the leakage current of pixel electrode, and then reduce leakage current to show impact, improve display product
Matter.
Optionally, the scanning electricity received by the grid of the 1st thin film transistor (TFT) in the thin film transistor (TFT) of the n series connection
Pressure signal is less than the scanning voltage signal received by the grid of other thin film transistor (TFT)s, so arranges so that the 1st film crystal
The partial pressure of pipe is minimum, and the quantity of the carrier passed through in the unit interval is minimum, and the 1st thin film transistor (TFT) is defined is connected by n
Thin film transistor (TFT) flow to pixel electrode overall leakage current size, due to the 1st thin film transistor (TFT) directly and pixel electrode
Electrical connection, it is ensured that the leakage current passed through in pixel electrode is minimum.It should be noted that the grid of other thin film transistor (TFT)s is connect
The scanning voltage signal of receipts can be with identical, it is also possible to differs, this is not limited in the present embodiment.
Optionally, the scanning electricity received by the grid of n-th thin film transistor (TFT) in the thin film transistor (TFT) of the n series connection
Pressure signal is more than the scanning voltage signal received by the grid of other thin film transistor (TFT)s.So arrange so that n-th film crystal
Pipe partial pressure is maximum, and the carrier that can pass through in its unit interval at most, is easily affected by other factors the electric leakage for causing to flow through
Stream increase, by arranging n-th thin film transistor (TFT) away from pixel electrode, it is to avoid the impact of other factors, it is ensured that flow through picture
The leakage current of plain electrode is less.It should be noted that the scanning voltage signal that received of the grid of other thin film transistor (TFT)s can be with
It is identical, it is also possible to differ, this is not limited in the present embodiment.
Optionally, the thin film transistor (TFT) of n series connection is low-temperature polysilicon film transistor.Specifically, low temperature polycrystalline silicon is thin
Film transistor has higher electron transfer rate so that the response speed of thin film transistor (TFT) is exceedingly fast, it is ensured that pixel cell has
There are charge/discharge rates faster；Furthermore such that area occupied of the thin film transistor (TFT) in pixel cell can do it is less, thinner,
On the one hand display floater power consumption can be reduced, on the other hand, it is ensured that pixel cell has higher aperture opening ratio.
It should be noted that above-mentioned embodiment is carried out to the present invention only by taking the array base palte of display panels as an example
Illustrate, not limitation of the invention, the present disclosure additionally applies for organic electroluminescence display panel.In addition, the present embodiment is only with two
Thin film transistor (TFT) is connected and three thin film transistor (TFT) series connection describe the present invention, not limitation of the invention.
The embodiment of the present invention additionally provides a kind of display floater, and Fig. 9 is a kind of display floater provided in an embodiment of the present invention
Schematic diagram, with reference to Fig. 9, the display floater includes the array base palte 100 described in any embodiment of the present invention.
Optionally, the display floater also includes the color membrane substrates 300 being oppositely arranged with array base palte 100, and arranges
Liquid crystal layer 200 between array base palte 100 and color membrane substrates 300.Black matrix, the n string are provided with color membrane substrates 300
The thin film transistor (TFT) of connection is located in the black matrix in the orthographic projection of color membrane substrates 300.
Optionally, the picture refreshing frequency range of the display floater is 0.5Hz-45Hz, when picture refreshing frequency is more than
During 45Hz, larger power consumption can be brought, cause the loss of resource and energy, and the display floater that the present invention is provided, by above-mentioned
Structure design in embodiment, can be effectively reduced the picture refreshing frequency of display floater, while so that display floater exists
Still there is stable display picture, so as to, while ensureing with higher image display quality, reduce under lower frequency
The power consumption of display floater.
The embodiment of the present invention additionally provides a kind of display device, and Figure 10 is a kind of display device provided in an embodiment of the present invention
Schematic diagram, with reference to Figure 10, display device 400 includes display floater 500, and display floater 500 includes any embodiment of the present invention
Described array base palte, wherein, display device 400 can be mobile phone as illustrated in the drawing, or computer, television set, intelligence
Display device etc. can be dressed, the present embodiment is not particularly limited to this.
It should be noted that each embodiment in this specification is described by the way of progressive, each embodiment weight
Point explanation is all difference with other embodiment, between each embodiment identical similar part mutually referring to.
The foregoing description of the disclosed embodiments, enables professional and technical personnel in the field to realize or using the present invention.
Various modifications to these embodiments will be apparent for those skilled in the art, as defined herein
General Principle can be realized without departing from the spirit or scope of the present invention in other embodiments.Therefore, the present invention
The embodiments shown herein is not intended to be limited to, and is to fit to and principles disclosed herein and features of novelty phase one
The most wide scope for causing.
Claims (17)
1. a kind of array base palte, it is characterised in that include：
Scan line and data wire, the scan line intersect the multiple pixel cells of restriction, the pixel list with data wire insulation
Unit includes the n thin film transistor (TFT) connected and pixel electrode, wherein, n is positive integer, and n 2；
The drain electrode of the 1st thin film transistor (TFT) in the thin film transistor (TFT) of the n series connection is connected with the pixel electrode, n-th
The source electrode of thin film transistor (TFT) is connected to data wire described in, for receiving data voltage signal；
The grid of each thin film transistor (TFT) in the thin film transistor (TFT) of the n series connection receives scan voltage signal, wherein, the
The scanning voltage signal received by the grid of i thin film transistor (TFT) is less than the scanning received by the grid of j-th thin film transistor (TFT)
Voltage signal, i, j are positive integer, 1≤i≤n, 1≤j≤n, and i ≠ j.
2. array base palte according to claim 1, it is characterised in that the pixel cell also include showing electric capacity and/or
One pole plate of storage capacitance, the display electric capacity and/or the storage capacitance is the pixel electrode.
3. array base palte according to claim 1, it is characterised in that i-th thin film in the n thin film transistor (TFT) is brilliant
The grid of body pipe is connected with scan line described in, and the grid of j-th thin film transistor (TFT) is connected with another scan line.
4. array base palte according to claim 1, it is characterised in that the pixel cell also includes at least one partial pressure unit
Part, the grid of i-th thin film transistor (TFT) are connected with sectional pressure element described in, and scan line described in the sectional pressure element and connects
Connect.
5. array base palte according to claim 4, it is characterised in that the sectional pressure element includes at least one partial pressure crystal
Pipe, the grid of at least one bleeder transistor are all connected with the scan line.
6. array base palte according to claim 5, it is characterised in that with described at least one point in the sectional pressure element
The scan line of the grid connection of piezoelectric crystal is connected with the grid of j-th thin film transistor (TFT).
7. array base palte according to claim 5, it is characterised in that the sectional pressure element includes that at least two partial pressures are brilliant
Body pipe, at least two bleeder transistor are serially connected or parallel with one another.
8. array base palte according to claim 5, it is characterised in that the sectional pressure element includes a partial pressure crystal
Pipe, the grid of i-th thin film transistor (TFT) be connected with the drain electrode of the bleeder transistor, the source electrode of the bleeder transistor and
Grid is connected.
9. the array base palte according to claim 1-8 any one, it is characterised in that the film crystal of the n series connection
The scanning voltage signal received to the grid of arbitrary thin film transistor (TFT) in m-th thin film transistor (TFT) by the 1st in pipe is less than institute
State the individual grids to arbitrary thin film transistor (TFT) in n-th thin film transistor (TFT) of the m+1 in the thin film transistor (TFT) of n series connection to be received
Scanning voltage signal, m is positive integer, and 1≤m ＜ n.
10. the array base palte according to claim 1-8 any one, it is characterised in that the film crystal of the n series connection
The scanning voltage signal received by the grid of the 1st thin film transistor (TFT) in pipe is received less than the grid of other thin film transistor (TFT)s
Scanning voltage signal, the scanning voltage signal received by the grid of other thin film transistor (TFT)s is identical.
11. array base paltes according to claim 1-8 any one, it is characterised in that the film crystal of the n series connection
The scanning voltage signal received by the grid of n-th thin film transistor (TFT) in pipe is received more than the grid of other thin film transistor (TFT)s
Scanning voltage signal, the scanning voltage signal received by the grid of other thin film transistor (TFT)s is identical.
12. array base paltes according to claim 1-8 any one, it is characterised in that the film crystal of the n series connection
The scanning voltage signal received by the grid of i-th thin film transistor (TFT) in pipe is connect less than the grid of j-th thin film transistor (TFT)
The scanning voltage signal of receipts, and i<j.
13. array base paltes according to claim 1, it is characterised in that the thin film transistor (TFT) of the n series connection is that low temperature is more
Polycrystal silicon film transistor.
14. a kind of display floaters, it is characterised in that including the array base palte described in any one of claim 1-13.
15. display floaters according to claim 14, it is characterised in that also include：
The color membrane substrates being oppositely arranged with the array base palte；
Black matrix, orthographic projection of the described n thin film transistor (TFT) connected in the color membrane substrates are provided with the color membrane substrates
In the black matrix.
16. display floaters according to claim 14, it is characterised in that the picture refreshing frequency of the display floater is
0.5Hz-45Hz, including endpoint value.
17. a kind of display devices, it is characterised in that including the display floater described in any one of claim 14-16.
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