CN106507139A - Multi-path high-definition video multiplex display packing and device - Google Patents
Multi-path high-definition video multiplex display packing and device Download PDFInfo
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- CN106507139A CN106507139A CN201611009357.1A CN201611009357A CN106507139A CN 106507139 A CN106507139 A CN 106507139A CN 201611009357 A CN201611009357 A CN 201611009357A CN 106507139 A CN106507139 A CN 106507139A
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- 238000012856 packing Methods 0.000 title claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 59
- 230000008569 process Effects 0.000 claims abstract description 55
- 230000008014 freezing Effects 0.000 claims description 11
- 238000007710 freezing Methods 0.000 claims description 11
- 238000010257 thawing Methods 0.000 claims description 10
- 239000011159 matrix material Substances 0.000 claims description 8
- 241001269238 Data Species 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
- H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
- H04N21/234—Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs
- H04N21/2343—Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs involving reformatting operations of video signals for distribution or compliance with end-user requests or end-user device requirements
- H04N21/234363—Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs involving reformatting operations of video signals for distribution or compliance with end-user requests or end-user device requirements by altering the spatial resolution, e.g. for clients with a lower screen resolution
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
- H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
- H04N21/236—Assembling of a multiplex stream, e.g. transport stream, by combining a video stream with other content or additional data, e.g. inserting a URL [Uniform Resource Locator] into a video stream, multiplexing software data into a video stream; Remultiplexing of multiplex streams; Insertion of stuffing bits into the multiplex stream, e.g. to obtain a constant bit-rate; Assembling of a packetised elementary stream
- H04N21/2365—Multiplexing of several video streams
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0117—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving conversion of the spatial resolution of the incoming video signal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/015—High-definition television systems
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Computer Graphics (AREA)
- Television Systems (AREA)
Abstract
The present invention discloses a kind of multi-path high-definition video multiplex display packing and device, and wherein, the method comprises the steps：Collection at least two-way high-definition video signal；Process is zoomed in and out respectively at least two-way high-definition video signal, at least two-way video standard signal is obtained；Multiplexing process is carried out at least two-way video standard signal using self-defining video format, multiplexed video signal all the way is obtained, the multiplexed video signal is from top to bottom combined by arbitrary two field picture of each road video signal；Demultiplexing process is carried out to multiplexed video signal, and selects either standard video signal as output video signal；Process is amplified to exporting video signal, the HD video all the way for exporting is obtained.Technical scheme can select arbitrarily all the way/multiple-channel output, output video flexibly can select, and improve the utilization ratio of interface；Also having reduces hardware cost and avoids slowed-down video.
Description
Technical field
The present invention relates to a kind of technical field of video communication, more particularly to a kind of multi-path high-definition video multiplex display packing and
Device.
Background technology
Texas Instrument (TI) releases TI8168 Leonardo da Vinci's video frequency processing chips, and the chip includes that two 1080P60 high definitions are regarded
Frequency output interface, can simultaneously 2 road 1080P60 HD videos of output display, or defeated by two HD video display ports
Go out 16 road D1 videos (resolution is 720 × 480, is standard definition signal).
But in such scheme, it is only capable of by two HD video display ports to two-way high definition or multichannel SD video
Signal is transmitted display, it is impossible to high-definition video signal more than two-way is exported by two HD video display ports
Show.Two panels TI8168 chip is needed to the video signal output display of 4 tunnel high definitions 1080P30 for example, or needs to increase
Processing, hardware cost is too high for FPGA, and it is complicated that the FPGA of increase also results in hardware configuration, easily causes the time delay of video to ask
Topic.
Content of the invention
For solving an above-mentioned at least technical problem, the main object of the present invention is to provide a kind of multi-path high-definition video multiplex and shows
Show method.
For achieving the above object, one aspect of the present invention is：There is provided a kind of multi-path high-definition video multiplex to show
Show method, comprise the steps：
Collection at least two-way high-definition video signal；
Process is zoomed in and out respectively at least two-way high-definition video signal, at least two-way video standard signal is obtained；
Multiplexing process is carried out at least two-way video standard signal using self-defining video format, is multiplexed all the way and is regarded
Frequency signal, the multiplexed video signal are from top to bottom combined by arbitrary two field picture of each road video signal；
Demultiplexing process is carried out to multiplexed video signal, and selects either standard video signal as output video letter
Number；
Process is amplified to exporting video signal, the HD video all the way for exporting is obtained.
Preferably, described carry out demultiplexing process to multiplexed video signal, and select either standard video signal conduct
The step of output video signal, specifically include：
Configure the line of input pixel and line number deviant of each road video standard signal；
The valid data that the row pixel of video standard signal is constituted with line number deviant sum are used as input source offset；
Either standard video signal is selected as output video signal according to input source offset.
Preferably, described collection at least two-way high-definition video signal the step of before, also include：
Receive at least two railway digitals or analog video and be input into and change the parallel signal that is output as YCbCr422 forms.
Preferably, described in the step of at least two-way high-definition video signal zooms in and out process respectively, the standard is regarded
The ratio of width to height in frequency signal per two field picture is 16:9.
Preferably, described pair output video signal be amplified processs, obtain output HD video all the way the step of it
Afterwards, also include：
Before output HD video is changed, carry out freezing to process to exporting video pictures, and select high definition to regard changing
After frequency, defrosting process is carried out to exporting video pictures, and export variation HD video.
For achieving the above object, another technical solution used in the present invention is：A kind of multi-path high-definition video multiplex is provided
Display device, including：First video frequency processing chip, the chip matrix electrically connected with the first video frequency processing chip, and and matrix
Second video frequency processing chip of chip electrical connection；
First video frequency processing chip is specifically included,
Video acquisition module, in order to gather at least two-way high-definition video signal；
Video scaling module, in order to zoom in and out process respectively at least two-way high-definition video signal, obtains at least two-way
Video standard signal；
Video multiplex module, in order to be carried out at multiplexing at least two-way video standard signal using self-defining video format
Reason, obtains multiplexed video signal all the way, arbitrary two field picture from top to bottom group of the multiplexed video signal by each road video signal
Conjunction is formed；
Second video frequency processing chip is specifically included,
Video demultiplexing module, for carrying out demultiplexing process to multiplexed video signal, and selects either standard video
Signal is used as output video signal；
Video amplifier module, for being amplified process to exporting video signal, obtains the HD video all the way for exporting.
Preferably, the video demultiplexing module, specifically for：
Configure the line of input pixel and line number deviant of each road video standard signal；
The valid data that the row pixel of video standard signal is constituted with line number deviant sum are used as input source offset；
Either standard video signal is selected as output video signal according to input source offset.
Preferably, the multi-path high-definition video multiplex display device also includes：
Video capture processor, is output as YCbCr422 lattice in order to receive at least two railway digitals or analog video and be input into and change
The parallel signal of formula.
Preferably, the ratio of width to height in the video standard signal per two field picture is 16:9.
Preferably, second video frequency processing chip also includes freezing/thawing module, for changing output HD video
Before, carry out freezing to process to exporting video pictures, and after selecting to change HD video, thaw to exporting video pictures
Process, and export variation HD video.
Technical scheme, can be in multiplexing by zooming in and out process using at least two-way high-definition video signal
During avoid the effective maximum number of lines of every frame video image, it is not necessary to be configured to interlaced video signal or increase odd even field signal/
Frame signal, can keep the integrity of primary signal, be not required to de interlacing relevant treatment；Arbitrarily all the way/multiple-channel output, output can be selected
Video flexibly can be selected, and improve the utilization ratio of interface.Simultaneous processor interface rear end need not add the high costs such as FPGA, answer
Miscellaneous peripheral apparatus, reduce hardware cost, and can avoid the delay of video.
Description of the drawings
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
Accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Structure according to these accompanying drawings obtains other accompanying drawings.
Schematic flow sheets of the Fig. 1 for one embodiment of the invention multi-path high-definition video multiplex display packing；
Fig. 2 is multiplexed video signal sequential chart in step S30 of the present invention；
Block diagrams of the Fig. 3 for one embodiment of the invention multi-path high-definition video multiplex display device；
The block diagram of the second video frequency processing chip of Fig. 4 bitmaps 3.
The realization of the object of the invention, functional characteristics and advantage will be described further in conjunction with the embodiments referring to the drawings.
Specific embodiment
Accompanying drawing in below in conjunction with the embodiment of the present invention, to the embodiment of the present invention in technical scheme carry out clear, complete
Site preparation is described, it is clear that described embodiment a part of embodiment only of the invention, rather than whole embodiments.Base
Embodiment in the present invention, those of ordinary skill in the art obtained under the premise of creative work is not made all its
His embodiment, belongs to the scope of protection of the invention.
It is to be appreciated that the description for being related to " first ", " second " etc. in the present invention be only used for describe purpose, and it is not intended that
Indicate or imply its relative importance or the implicit quantity for indicating indicated technical characteristic.Thus, define " first ",
The feature of " second " can be expressed or implicitly include at least one this feature.In addition, the technical side between each embodiment
Case can be combined with each other, but must can be implemented as basis with those of ordinary skill in the art, when the combination of technical scheme
Will be understood that the combination of this technical scheme is not present when appearance is conflicting or cannot realize, also not in the guarantor of application claims
Within the scope of shield.
Fig. 1 and Fig. 2 is refer to, in embodiments of the present invention, the multi-path high-definition video multiplex display packing, including following step
Suddenly：
Step S10, collection at least two-way high-definition video signal；
Step S20, process is zoomed in and out respectively at least two-way high-definition video signal, obtain at least two-way normal video letter
Number；
Step S30, multiplexing process is carried out at least two-way video standard signal using self-defining video format, obtain one
Road multiplexed video signal, the multiplexed video signal are from top to bottom combined by arbitrary two field picture of each road video signal；
Step S40, demultiplexing process is carried out to multiplexed video signal, and select either standard video signal as output
Video signal；
Step S50, to export video signal be amplified processs, obtain output HD video all the way.
As the ti8168 chips of this TI companies are used as primary processor, it is 2048 rows per frame maximum number of lines, and supports to make by oneself
Adopted video format.In a specific example, two-way 1920 × 1080p60 of high-definition video signal can be gathered, if directly right
Two-way high-definition video signal is multiplexed, and the video after will certainly causing to be multiplexed will certainly exceed the ultimate value of 2048 line numbers, because
This, is that 1920 × 1080p60 of high-definition video signal is zoomed in and out by the requirement needs for meeting par-ticular processor, obtain by frame per second be
The video standard signal of 1792 × 1008p30, the ratio of width to height of the video standard signal is 16:9, thus, could meet specific
Ti8168 chips are required.It should be understood that after the line number of chip valid data exceeds 2048, the ratio of scaling has wider model
The selection that encloses, it is allowed to which the high-definition video signal of collection may be three kinds or more, without being configured to interlaced video letter
Number or increase odd even field signal/frame signal, the integrity of primary signal can be kept, de interlacing relevant treatment is not required to, is reduced and regard
Frequency postpones, and is capable of the resource of maximum optimum decision system.By taking this programme collection two-way high-definition video signal as an example, Fig. 2, Fig. 2 is refer to
For multiplexed video signal sequential chart, multiplexed video signal is from top to bottom combined by arbitrary two field picture of two-path video signal,
Ensure maximum video clock in the range of, while the effectively line number of the maximum per frame is less than 2048 rows, and consider multiple
With with demultiplexing during need scaling with amplify, will zoom in and out per road 1920 × 1080p60 of original video, drop frame per second size
1792 × 1008p30, so can remain that the ratio of width to height is 16 during video amplifier with diminution:9, it is to avoid video
Loss；By configuring appropriate shoulder in front and back, synchronous width, in multiplexing rear video frame, the total pixel of a line is 2200, total line number
For 2250, frame per second is 30fps.Video clock is 2200 × 2250 × 30=148.5Mhz.Wherein, row, field synchronization width difference
For 5,44；Before and after row, shoulder breadth degree is respectively 36,193；Before and after, shoulder breadth is respectively 276,88.
Technical scheme, can be in multiplexing by zooming in and out process using at least two-way high-definition video signal
During avoid the effective maximum number of lines of every frame video image, it is not necessary to be configured to interlaced video signal or increase odd even field signal/
Frame signal, can keep the integrity of primary signal, be not required to de interlacing relevant treatment；Arbitrarily all the way/multiple-channel output, output can be selected
Video flexibly can be selected, and improve the utilization ratio of interface.Simultaneous processor interface rear end need not add the high costs such as FPGA, answer
Miscellaneous peripheral apparatus, reduce hardware cost, and can avoid the delay of video.
In a specific embodiment, described demultiplexing process is carried out to multiplexed video signal, and select either standard
Video signal is specifically included as S40 the step of output video signal：
Configure the line of input pixel and line number deviant of each road video standard signal；
The valid data that the row pixel of video standard signal is constituted with line number deviant sum are used as input source offset；
Either standard video signal is selected as output video signal according to input source offset.
By taking two-path video multiplexed signals as an example, if the first via video standard signal (upper half of a frame being multiplexed will be selected
Part), can be 0 for the configuration line number skew of first via video standard signal, be that first via video standard signal configuration line number is inclined
Move as 255.And the valid pixel of video standard signal is 1792 × 1008.So, the valid pixel in multiplexed video, just only takes
Top half, i.e., 1792 × 1008 are written with SRAM, through internal processing and amplifying after, obtain 1920 × 1080p30 videos, that is, export
First via HD video data have just been got.If will correspondingly remove the second road normal video data of half part, only need by
Line number skew is set to 1333 (1008+225).It should be understood that for video standard signals more than three tunnels or three tunnels
Can complete according to above-mentioned scheme.
In a specific embodiment, described collection at least two-way high-definition video signal the step of S10 before, also include：
Receive at least two railway digitals or analog video and be input into and change the parallel signal that is output as YCbCr422 forms.
In the present embodiment, the two-way high-definition video signal of collection can be that digital video input signal or analog video are defeated
Enter signal, in order to ensure the synchronization of at least two-way high-definition video signal for gathering, in addition it is also necessary to which the form of high-definition video signal is entered
Row conversion, unified output parallel signals, is subsequently processed to two-way high-definition video signal with facilitating.
In a specific embodiment, described pair of output video signal is amplified process, obtains the high definition all the way for exporting
After the step of video S50, also include：
Before output HD video is changed, carry out freezing to process to exporting video pictures, and select high definition to regard changing
After frequency, defrosting process is carried out to exporting video pictures, and export variation HD video.
In order to avoid the video not blank screen in the handover of this programme, not splashette, do not shake, the problem for realizing being switched fast,
In the present embodiment, need, to changing before output HD video, to carry out freezing to process to exporting video pictures, and select changing
After HD video, defrosting process is carried out to exporting video pictures, and export variation HD video.Wherein, the variation selects high definition
The scheme of video may be referred to the above embodiments, and here is omitted.
Fig. 3 and Fig. 4 is refer to, in embodiments of the invention, the multi-path high-definition video multiplex display device, including：First
Video frequency processing chip 10, the chip matrix 20 electrically connected with the first video frequency processing chip 10, and electrically connect with chip matrix 20
The second video frequency processing chip 30；
First video frequency processing chip 10 is specifically included,
Video acquisition module 11, in order to gather at least two-way high-definition video signal；
Video scaling module 12, in order to zoom in and out process respectively at least two-way high-definition video signal, obtains at least two
Road video standard signal；Wherein, the ratio of width to height of the video standard signal is 16:9.
Video multiplex module 13, in order to be multiplexed at least two-way video standard signal using self-defining video format
Process, obtain multiplexed video signal all the way, the multiplexed video signal by each road video signal arbitrary two field picture from top to bottom
Combine；
Second video frequency processing chip 30 is specifically included,
Video demultiplexing module 31, for carrying out demultiplexing process to multiplexed video signal, and selects either standard and regards
Frequency signal is used as output video signal；
Video amplifier module 32, for being amplified process to exporting video signal, obtains the HD video all the way for exporting.
In the present embodiment, the first video frequency processing chip 10 selects TI8168, and the second video frequency processing chip 30 is selected
MDIN380, quantity are four, and four road video output datas can be processed, and chip matrix 20 selects ADN4605, specifically
, this programme can also include 40 model ADV7604 of video capture processor, 50 model ADV7611 of HDMI decoding chips.Should
First video frequency processing chip 10 is mainly used in gathering or decoding obtaining original high-definition video signal, constructs multiple after inter-process
Use video signal；Chip matrix 20 is used as HDMI matrixes, the 2 tunnel HDMI video signals effectively switching that processor can be exported or
4 tunnels or more signal is copied into, central in actual use, 4 local/far-end videos, or this can be shown simultaneously in outfan
2 tunnels of ground, 2 road different video of distal end show simultaneously, and can realize according to specific needs being switched fast；Second video frequency processing chip
30, for processing the signal after multiplexing, select output video all the way therein.HDMI decoding chips 50, with anti-equalization function, defeated
Go out the parallel signal for YCbCr422 16bit, facilitate the process of the second video frequency processing chip 30.
Assembly of the invention can utilize two high definition video interfaces of the first video frequency processing chip 10, transmit 4 road 1080P30
HD video, and can select to export video all the way by the second video frequency processing chip 30.Can accomplish simultaneously not black in the handover
Screen, not splashette, do not shake, realize being switched fast.The limit of TI8168 chip per frame effective line number maximum 2048 rows is effectively avoided
System, in scaling with amplification process, remain wide high, it is to avoid the loss of video, and need not be multiplexed into interlaced video
Or increase odd even field signal, using self-defining video format, without the need for FPGA or other complex devices, just quickly correctly can demultiplex
With, and reach the effect of professional video level.In limited system resources and the scheme higher to cost requirement, there is bigger valency
Value.
In a specific embodiment, the video demultiplexing module 31, specifically for：
Configure the line of input pixel and line number deviant of each road video standard signal；
The valid data that the row pixel of video standard signal is constituted with line number deviant sum are used as input source offset；
Either standard video signal is selected as output video signal according to input source offset.
By taking two-path video multiplexed signals as an example, if the first via video standard signal (upper half of a frame being multiplexed will be selected
Part), it is 0 that can offset for first via video standard signal configuration line number on the second video frequency processing chip 30, is the first via
Video standard signal configuration line number skew is 255.And the valid pixel of video standard signal is 1792 × 1008.So, it is multiplexed
Valid pixel in video, just only takes top half, i.e., 1792 × 1008 and is written with SRAM, through internal processing and amplifying after, obtain
1920 × 1080p30 videos, that is, export and just got first via HD video data.If will correspondingly remove the of half part
Line number skew only need to be set to 1333 (1008+225) by two road normal video datas.It should be understood that for three tunnels or three
Video standard signal more than road can also be completed according to above-mentioned scheme.
In a specific embodiment, the multi-path high-definition video multiplex display device also includes：
Video capture processor 40, is output as YCbCr422 in order to receive at least two railway digitals or analog video and be input into and change
The parallel signal of form.
In the present embodiment, the quantity of video capture processor 40 is two panels, supports numeral HDMI/DVI and simulation VGA/ components
Video input, same is output as YCbCr422 16bit parallel signals.
In a specific embodiment, second video frequency processing chip 30 also includes freezing/thawing module, for becoming
Before dynamic output HD video, carry out freezing to process to exporting video pictures, and after selecting to change HD video, output is regarded
Frequency picture carries out defrosting process, and exports variation HD video.
In order to avoid the video not blank screen in the handover of this programme, not splashette, do not shake, the problem for realizing being switched fast,
In the present embodiment, need, to changing before output HD video, to carry out freezing to process to exporting video pictures, and select changing
After HD video, defrosting process is carried out to exporting video pictures, and export variation HD video.Wherein, the variation selects high definition
The scheme of video may be referred to the above embodiments, and here is omitted.
The preferred embodiments of the present invention are the foregoing is only, the scope of the claims of the present invention is not thereby limited, every at this
Under the inventive concept of invention, the equivalent structure transformation made using description of the invention and accompanying drawing content, or directly/use indirectly
In the scope of patent protection that other related technical fields are included in the present invention.
Claims (10)
1. a kind of multi-path high-definition video multiplex display packing, it is characterised in that the multi-path high-definition video multiplex display packing bag
Include following steps：
Collection at least two-way high-definition video signal；
Process is zoomed in and out respectively at least two-way high-definition video signal, at least two-way video standard signal is obtained；
Multiplexing process is carried out at least two-way video standard signal using self-defining video format, multiplexed video letter all the way is obtained
Number, the multiplexed video signal is from top to bottom combined by arbitrary two field picture of each road video signal；
Demultiplexing process is carried out to multiplexed video signal, and selects either standard video signal as output video signal；
Process is amplified to exporting video signal, the HD video all the way for exporting is obtained.
2. multi-path high-definition video multiplex display packing as claimed in claim 1, it is characterised in that described to multiplexed video signal
The step of carrying out demultiplexing process, and select either standard video signal as output video signal, specifically includes：
Configure the line of input pixel and line number deviant of each road video standard signal；
The valid data that the row pixel of video standard signal is constituted with line number deviant sum are used as input source offset；
Either standard video signal is selected as output video signal according to input source offset.
3. multi-path high-definition video multiplex display packing as claimed in claim 1, it is characterised in that the collection at least two-way is high
Before the step of clear video signal, also include：
Receive at least two railway digitals or analog video and be input into and change the parallel signal that is output as YCbCr422 forms.
4. multi-path high-definition video multiplex display packing as claimed in claim 1, it is characterised in that described at least two-way high definition
In the step of video signal zooms in and out process respectively, the ratio of width to height in the video standard signal per two field picture is 16:9.
5. the multi-path high-definition video multiplex display packing as described in any one of Claims 1-4, it is characterised in that described to defeated
Go out video signal and be amplified process, obtain export HD video all the way the step of after, also include：
Before output HD video is changed, carry out freezing to process to exporting video pictures, and after selection HD video is changed,
Defrosting process is carried out to exporting video pictures, and exports variation HD video.
6. a kind of multi-path high-definition video multiplex display device, it is characterised in that the multi-path high-definition video multiplex display device bag
Include：First video frequency processing chip, the chip matrix electrically connected with the first video frequency processing chip, and electrically connect with chip matrix
Second video frequency processing chip；
First video frequency processing chip is specifically included,
Video acquisition module, in order to gather at least two-way high-definition video signal；
Video scaling module, in order to zoom in and out process respectively at least two-way high-definition video signal, obtains at least two-way standard
Video signal；
Video multiplex module, in order to carry out multiplexing process using self-defining video format at least two-way video standard signal,
Obtain multiplexed video signal all the way, the multiplexed video signal from top to bottom combined by arbitrary two field picture of each road video signal and
Into；
Second video frequency processing chip is specifically included,
Video demultiplexing module, for carrying out demultiplexing process to multiplexed video signal, and selects either standard video signal
As output video signal；
Video amplifier module, for being amplified process to exporting video signal, obtains the HD video all the way for exporting.
7. multi-path high-definition video multiplex display device as claimed in claim 1, it is characterised in that the video demultiplexes mould
Block, specifically for：
Configure the line of input pixel and line number deviant of each road video standard signal；
The valid data that the row pixel of video standard signal is constituted with line number deviant sum are used as input source offset；
Either standard video signal is selected as output video signal according to input source offset.
8. multi-path high-definition video multiplex display device as claimed in claim 1, it is characterised in that the multi-path high-definition video is multiple
Also included with display device：
Video capture processor, is output as YCbCr422 forms in order to receive at least two railway digitals or analog video and be input into and change
Parallel signal.
9. multi-path high-definition video multiplex display device as claimed in claim 1, it is characterised in that in the video standard signal
The ratio of width to height per two field picture is 16:9.
10. the multi-path high-definition video multiplex display device as described in any one of claim 6 to 9, it is characterised in that described second
Video frequency processing chip also includes freezing/thawing module, for, before output HD video is changed, freezing to exporting video pictures
Knot process, and after selecting to change HD video, carry out defrosting process to exporting video pictures, and export variation high definition regarding
Frequently.
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| CN201611009357.1A CN106507139A (en) | 2016-11-16 | 2016-11-16 | Multi-path high-definition video multiplex display packing and device |
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| CN201611009357.1A CN106507139A (en) | 2016-11-16 | 2016-11-16 | Multi-path high-definition video multiplex display packing and device |
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