CN106505994A - Sequence circuit and its operational approach - Google Patents

Sequence circuit and its operational approach Download PDF

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Publication number
CN106505994A
CN106505994A CN201610809106.5A CN201610809106A CN106505994A CN 106505994 A CN106505994 A CN 106505994A CN 201610809106 A CN201610809106 A CN 201610809106A CN 106505994 A CN106505994 A CN 106505994A
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China
Prior art keywords
nodal point
respond
voltage
nmos pass
pmos transistor
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Granted
Application number
CN201610809106.5A
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Chinese (zh)
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CN106505994B (en
Inventor
黄铉澈
金珉修
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/356121—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit with synchronous operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Abstract

A kind of sequence circuit and its operational approach are disclosed.In sequence circuit, the first order is configured to respond to clock and the voltage of primary nodal point is charged, and the voltage of primary nodal point is discharged in response to clock, the voltage of secondary nodal point and data；The second level is configured to respond to clock and the voltage of secondary nodal point is charged, and the voltage of secondary nodal point is discharged in response to clock and logical signal；Combination logic is configured to generate logical signal based on the voltage of primary nodal point, the voltage of secondary nodal point and data；And latch cicuit is configured to respond to clock to latch the voltage of secondary nodal point.

Description

Sequence circuit and its operational approach
Technical field
The example embodiment of inventive concept is related to sequence circuit and/or its operational approach.
Background technology
Using the data storage unit in digital circuit of the sequence circuit (for example, trigger) as semiconductor integrated circuit Part.Sequence circuit is sampled to input signal in the time point determined by clock signal, and by sampling after input signal Become output signal.Sequence circuit is used for semiconductor memory system (for example, dynamic random access memory (DRAM)), processes Device, computer etc..
Content of the invention
One or more example embodiments of inventive concept provide relatively high speed sequence circuit and/or its operational approach.
At least one example embodiment provides sequence circuit, including：The first order, is configured to respond to clock to first segment The voltage of point is charged, and the first order is additionally configured in response to clock, the voltage of secondary nodal point and data to primary nodal point Voltage is discharged；The second level, is configured to respond to clock and the voltage of secondary nodal point is charged, and the second level is also configured It is the voltage of secondary nodal point to be discharged in response to clock and logical signal；Combination logic, is configured to based on primary nodal point Voltage, the voltage of secondary nodal point and data to be generating logical signal；And latch cicuit, it is configured to respond to clock to lock Deposit the voltage of secondary nodal point.Combination logic is additionally configured to generate logical signal so that (i) when the voltage of primary nodal point is discharged When, the voltage of secondary nodal point is not discharged, or (ii) is when the voltage of secondary nodal point is discharged, the voltage of primary nodal point not by Electric discharge.
At least one other example embodiment provides a kind of sequence circuit, including：The first order；The second level；Combination logic And latch cicuit.The first order includes：The first transistor, with the first terminal being connected with primary nodal point；Transistor seconds, is matched somebody with somebody It is set to the voltage in response to secondary nodal point and primary nodal point is connected to power supply terminal；Third transistor, is configured to respond to sweep Retouch input and the Second terminal of the first transistor is connected to power supply terminal；4th transistor, is configured to respond to scanning and enables The Second terminal of the first transistor is connected to power supply terminal by signal；5th transistor, is configured to respond to clock by first Connecting node is connected to primary nodal point；6th transistor, with the first terminal for being connected to primary nodal point；And the 7th crystal Pipe, is configured to respond to the Second terminal that the second connecting node is connected to scan enable signal the 6th transistor.The second level Including：8th transistor, is configured to respond to clock and secondary nodal point is connected to power supply terminal；9th transistor, is configured It is, in response to the voltage of primary nodal point, secondary nodal point is connected to power supply terminal；Tenth transistor, with being connected with secondary nodal point The first terminal；And the 11st transistor, be configured to respond to that ground terminal is connected to clock the tenth transistor second Terminal.Combination logic is configured to the voltage based on data, the voltage of primary nodal point and secondary nodal point to generate logical signal, group Logical be additionally configured to by logical signal export to the first connecting node.Latch cicuit is configured to respond to clock to latch The voltage of secondary nodal point.
At least one other example embodiment provides a kind of operational approach of sequence circuit, and methods described includes：Response At least one of primary nodal point and secondary nodal point are charged in clock；The voltage of primary nodal point is carried out in response to clock Electric discharge；And the voltage of secondary nodal point is discharged in response to clock and logical signal.Voltage according to primary nodal point, second The voltage of node and the logical combination of data, generate logical signal.When the voltage of primary nodal point is discharged, the electricity of secondary nodal point Pressure is not discharged, and when the voltage of secondary nodal point is discharged, the voltage of primary nodal point is not discharged.
According at least some example embodiment, methods described may also include：Latch in response to clock and secondary nodal point The corresponding data of voltage；The data inversion that will be latched；Scanning pattern is formed in response to scan enable signal；And/or in response to The voltage of the voltage and secondary nodal point of primary nodal point is reset by reset signal.
At least one other example embodiment provides a kind of process including the first sequence circuit and the second sequence circuit Device.Second sequence circuit is connected in series to the first sequence circuit.Each in first sequence circuit and the second sequence circuit is matched somebody with somebody It is set to：The voltage of voltage, secondary nodal point in response to primary nodal point and data are generating logical signal；And believe in response to logic Number, it is determined whether the voltage of the voltage or secondary nodal point of primary nodal point is discharged.First sequence circuit and the second sequential electricity Each in road is further configured such that (i) when the voltage of primary nodal point is discharged, and the voltage of secondary nodal point is not discharged, and And (ii), when the voltage of secondary nodal point is discharged, the voltage of primary nodal point is not discharged.
At least one other example embodiment provides a kind of sequence circuit, including：First order circuit；Second level circuit； In conjunction with the combinational logic circuit between the secondary nodal point of the primary nodal point of first order circuit and second level circuit.Combination logic electricity Road is configured to based on the voltage of primary nodal point, the voltage of secondary nodal point and enters data to control primary nodal point and secondary nodal point Electric discharge, combination logic is additionally configured to the electric discharge for controlling primary nodal point and secondary nodal point so that in the interim very first time Primary nodal point is discharged and secondary nodal point is discharged during the second time interval, wherein, the very first time is spaced It is different underlapped time intervals with the second time interval.
Description of the drawings
By the description for carrying out with reference to the accompanying drawings, example embodiment will be clear from, wherein, unless otherwise noted, no Then run through various accompanying drawings, identical reference number refers to identical part, wherein：
Fig. 1 is the diagram of the sequence circuit for illustrating the example embodiment according to inventive concept；
Fig. 2 is the circuit diagram of the example embodiment for illustrating the combination logic illustrated in Fig. 1；
Fig. 3 is the circuit diagram of the example discharge path for illustrating the primary nodal point illustrated in Fig. 1；
Fig. 4 is the circuit diagram of another example discharge path for illustrating the primary nodal point illustrated in Fig. 1；
Fig. 5 is the circuit diagram of the example embodiment for illustrating the latch cicuit illustrated in Fig. 1；
Fig. 6 is the diagram of the sequence circuit for illustrating another example embodiment according to inventive concept；
Fig. 7 is the diagram of the sequence circuit for illustrating another example embodiment according to inventive concept；
Fig. 8 is the diagram of the sequence circuit for illustrating another example embodiment according to inventive concept；
Fig. 9 is the diagram for illustrating the sample scan path in the sequence circuit in Fig. 8；
Figure 10 is the diagram of the sequence circuit for illustrating another example embodiment according to inventive concept；
Figure 11 is to illustrate that AOI (AOI) door occurs the circuit diagram of the example embodiment of the sequence circuit for changing；
Figure 12 is to illustrate that AOI doors occur the circuit diagram of another example embodiment of the sequence circuit for changing；
Figure 13 is to illustrate that AOI doors occur the circuit diagram of another example embodiment of the sequence circuit for changing；
Figure 14 is the diagram of the sequence circuit for illustrating another example embodiment according to inventive concept；
Figure 15 is the flow chart of the operational approach of the sequential chart for illustrating the example embodiment according to inventive concept；
Figure 16 is the sequential chart of the exemplary operations sequential of the sequence circuit for illustrating the example embodiment according to inventive concept；
Figure 17 is the block diagram of the solid-state drive (SSD) for illustrating the example embodiment according to inventive concept；
Figure 18 is the block diagram of the electronic installation for illustrating the example embodiment according to inventive concept；And
Figure 19 is the block diagram of the mobile device for illustrating the example embodiment according to inventive concept.
Specific embodiment
By referring to the following the detailed description and the accompanying drawings to example embodiment, inventive concept will become more clearly understood from.So And, inventive concept can be implemented with many multi-forms and should not be construed as limited to the example embodiment for herein proposing. On the contrary, provide these example embodiments so that the disclosure will be thoroughly and completely, and by the concept present inventive concept Those skilled in the art is fully conveyed to, and present inventive concept will only be defined by the appended claims.Run through this specification, phase Same reference number represents identical element.
In the following description, the action with reference to operation and symbol are represented (for example, with flow chart, data flow diagram, structure Figure, block diagram etc.) describing illustrative embodiment, the operation can be implemented as including executing particular task or realize specific abstract The program module or function treatment of the routine of data type, program, object, component, data structure etc..Existing Department of Electronics can be used System (for example, display driver, SOC(system on a chip) (SoC) device, SoC systems, such as personal digital assistant (PDA), smart phone, The electronic installation of tablet personal computer (PC), laptop computer etc.) in existing hardware realizing.This existing hardware can Including on one or more CPU (CPU), digital signal processor (DSP), special IC (ASIC), piece being System (SoC), field programmable gate array (FPGA), computer etc..
In addition, one or more example embodiments can be (or including) hardware, firmware, the hardware for executing software or it Any combinations.This hardware may include one or more CPU, SoC, DSP, ASIC, FPGA, computer etc., and they are matched somebody with somebody It is set to for executing the special purpose machinery of any other known function of function described herein and these elements.At at least some In the case of, CPU, SoC, DSP, ASIC and FPGA may be referred to generally as process circuit, process circuit, processor and/or microprocessor Device.
Although flow chart can describe the operations as the process for order, many in these operations can parallel, concurrently or together When be performed.In addition, the order of these operations can be rearranged.The process can be terminated when the operation for processing is completed, but at this Reason can also have the additional step being not included in accompanying drawing.Process may correspond to method, function, process, subroutine, subprogram Deng.When a process corresponds to a function, which terminates the return of the function that may correspond to call function or principal function.
Disclosed herein, term " storage medium ", " computer-readable recording medium " or " non-transitory computer-readable Storage medium " can represent the one or more devices for data storage, including read only memory (ROM), random access memory Device (RAM), magnetic ram, core memory, magnetic disk storage medium, optical storage medium, flash memory devices and/or it is used for Other tangible machine-readable medias of storage information.Term " computer-readable medium " may include that (but not limited to) is portable or solid Fixed storage device, optical storage and can store, comprising or carry various other media of instruction and/or data.
Additionally, hardware, software, firmware, middleware, microcode, hardware description language or any combination of them can be passed through To realize at least some part of example embodiment.When being realized with software, firmware, middleware or microcode, must for executing Want task program code or code segment can be stored in such as computer-readable recording medium machine or computer-readable be situated between In matter.When implemented in software, processor, process circuit or processing unit can be programmed to execute necessary task, so as to be turned Become application specific processor or computer.
Code segment can represent process, function, subprogram, program, routine, subroutine, module, software encapsulation, class or refer to Make, any combinations of data structure or program statement.Transmission and/or receive information, data, implicit parameter can be passed through (arguments) code segment is attached to another code segment or hardware circuit by, parameter or memory content.Can by appoint What appropriate means (including Memory Sharing, message transmission, alternative space, network transmission etc.) come transmit, forward or transmission information, Implicit parameter, parameter, data etc..
As discussed here, " end " of transistor is also referred to as " terminal " of transistor.
Fig. 1 is the diagram of the sequence circuit for illustrating the example embodiment according to inventive concept.
With reference to Fig. 1, sequence circuit 100 may include the first order 110, the second level 120, combination logic 130 and latch cicuit 140.In one example, sequence circuit 100 can be trigger.
The first order 110 may include two PMOS transistors P11 and P12 and nmos pass transistor N11.The first of the first order 110 PMOS transistor P11 be attached between power supply terminal VDD and primary nodal point NET1 and may be in response to clock CLK switched on or Cut-off.Second PMOS transistor P12 of the first order 110 is attached between power supply terminal VDD and primary nodal point NET1 and can Voltage in response to secondary nodal point NET2 is switched on or ends.The nmos pass transistor N11 of the first order 110 is attached to the first connection Between node CN1 and primary nodal point NET1 and to may be in response to clock CLK switched on or end.When the first order 110 may be in response to The voltage of clock CLK and secondary nodal point NET2 determines the voltage of the voltage of primary nodal point NET1 and the first connecting node CN1.Here, First connecting node CN1 may be connected to the lead-out terminal of combination logic 130.
Can be complementary with the first order 110 and may include two PMOS transistors P21 and P22 and two NMOS in the second level 120 Transistor N21 and N22.First PMOS transistor P21 of the second level 120 is attached to power supply terminal VDD and secondary nodal point NET2 Between, and it is switched on or end to may be in response to clock CLK.Second PMOS transistor P22 of the second level 120 is attached to power supply Between terminal VDD and secondary nodal point NET2, and it is switched on or end to may be in response to the voltage of primary nodal point NET1.The second level 120 the first nmos pass transistor N21 is attached between secondary nodal point NET2 and the second connecting node CN2, and be may be in response to Logical signal LS is switched on or ends.That is, for example, one end of the first nmos pass transistor N21 is connected with secondary nodal point NET2 Connect and the other end is connected with the second connecting node CN2.Second nmos pass transistor N22 of the second level 120 is attached to the second company Meet between node CN2 and ground terminal GND and may be in response to clock CLK to be switched on or end.That is, for example, second Nmos pass transistor may be in response to the other end that ground terminal GND is connected to clock CLK the first nmos pass transistor N21.
The second level 120 may be in response to clock CLK, the voltage of primary nodal point NET1 and logical signal LS to determine secondary nodal point The voltage of NET2.In at least one example embodiment, in the time period and/or interim for setting (for example, specific lasting In time), the voltage of primary nodal point NET1 can be with the voltage complementary of secondary nodal point NET2.
In FIG for the first nmos pass transistor N21 for being serially connected and the second nmos pass transistor N22 exemplified with sending out The example embodiment of bright design.However, the scope and spirit of inventive concept should not necessarily be limited by this.For example, associate with clock CLK Nmos pass transistor may be connected to secondary nodal point NET2, and the nmos pass transistor associated with logical signal LS may be connected to ground terminal GND.
Combination logic 130 can receive the voltage of primary nodal point NET1, the voltage of secondary nodal point NET2 and data D and can make With the voltage of primary nodal point NET1, the voltage of secondary nodal point NET2 and the execution logic computing internally of data D.Therefore, combination is patrolled Collect 130 to be implemented as generating logical signal LS.Combination logic 130 can be realized with various types of logic circuits.
Latch cicuit 140 can be implemented as the voltage for latching secondary nodal point NET2 in response to clock CLK.Latch cicuit Data Q of 140 exportable latches or/Q.
The conceptual operation of the sequence circuit 100 of example embodiment according to inventive concept is below described.At clock CLK When low level, primary nodal point NET1 and secondary nodal point NET2 can be charged the voltage (for example, VDD) of high level.That is, For example, when clock CLK is in low level, primary nodal point NET1 and secondary nodal point NET2 can be electrically charged, and do not consider (or, Alternatively, independently of) data D.Hereafter, can determine whether to carry out primary nodal point NET1 based on data D and clock CLK Whether electric discharge will discharge to secondary nodal point NET2, and can be latched according to the determination result in latch cicuit 140 Data corresponding with the voltage of secondary nodal point NET2.
In at least one example embodiment, with regard to primary nodal point NET1 discharge operation can with regard to secondary nodal point NET2 Discharge operation complementary.For example, can be by the state based on data D by primary nodal point NET1 and secondary nodal point NET2 Discharge come the output valve (for example, Q or/Q) for determining sequence circuit 100.
In at least one example embodiment, when a node (for example, NET2) is discharged, can suppress, prevent and/or Prevent (for example, preventing completely) with regard to the discharge operation of another node (for example, NET1), vice versa.For example, work as first segment When one in point NET1 and secondary nodal point NET2 is discharged, combination logic 130 can suppress, prevent and/or prevent to wherein another One is discharged, till the node until discharging is recharged.Now, in PMOS transistor P12 and PMOS transistor P22 One can be switched on, and another node can be connected to power supply terminal VDD.
Traditionally, the clock that may be in response to low state based on the sequence circuit of pulse is charged to node, and Can be based on the clock of the pulse, high state generated using clock and data mode, it is determined whether (or maintenance) node will be kept Whether voltage status will discharge to node.Sequence circuit based on pulse relatively quickly can be operated.However, being based on The sequence circuit of pulse can be changed by clock to be affected.
On the other hand, according at least one example embodiment of inventive concept, sequence circuit 100 can be based on according to first segment The state of the voltage and data D of point NET1 and secondary nodal point NET2 and the logical signal LS that determines and clock CLK are determining (example Such as, complementally determine) whether primary nodal point NET1 and secondary nodal point NET2 are discharged.Therefore, compared to traditional sequential Circuit, the sequence circuit 100 according at least one example embodiment of inventive concept can reduce and/or minimize changing due to clock Affect caused by becoming.
Additionally, can be traditional based on pulse with having 3 stack architecture to realize with the nmos pass transistor that discharged node Sequence circuit.On the other hand, according at least one example embodiment, available have 2 stack architecture to enter secondary nodal point NET2 The nmos pass transistor N21 and N22 of row electric discharge is realizing sequence circuit 100.Therefore, compared to traditional sequence circuit, according to send out The sequence circuit 100 of at least one example embodiment of bright design can execute high speed latch operation by improving the velocity of discharge.
Traditionally, sequence circuit can be due to setup time and the clock for exporting (CQ) clock for postponing and affecting system Frequency.Therefore, when the relative high-performance sequence circuit of relatively small (for example, very little) is postponed using setup time and CQ, carry High clock frequency can be relatively easy.Sequence circuit 100 according at least one example embodiment of inventive concept can reduce foundation Time and/or CQ postpone, so as to improve clock frequency.
Fig. 2 is the circuit diagram of the example embodiment for illustrating the combination logic 130 illustrated in Fig. 1.
With reference to Fig. 2, combination logic 130 may include phase inverter 131 and AOI (AOI) door 132.
Phase inverter 131 can receive the voltage of primary nodal point NET1 and which is anti-phase.AOI doors 132 can be implemented as passing through The output valve of voltage, data D and phase inverter 131 for secondary nodal point NET2 executes the computing of AOI doors to generate logical signal LS. As shown in Figure 2, the lead-out terminal of AOI doors 132 may be connected to the first connecting node CN1.
The primary nodal point that to be formed according to the logical signal LS exported from combination logic 130 for Fig. 3 and Fig. 4 descriptions and the The discharge path and discharge operation of two nodes.
Fig. 3 is the circuit diagram of the example discharge path for illustrating the primary nodal point NET1 illustrated in Fig. 1.Describe for convenience, AOI doors 132 may include the discharge path for being connected to the first connecting node CN1.In at least one example embodiment, series connection can be used The nmos pass transistor N12 and N13 of connection realizes discharge path.Nmos pass transistor N12 may be in response to data D and be switched on, and NMOS is brilliant Body pipe N13 may be in response to the voltage of secondary nodal point NET2 and be switched on.Here, the nmos pass transistor being connected in series as shown in Figure 3 The order of N12 and N13 is example.However, the scope and spirit of inventive concept should not necessarily be limited by this.For example, it is connected section with second The nmos pass transistor of the voltage association of point CN2 may be connected to the first connecting node CN1, and the nmos pass transistor associated with data D can It is connected to ground terminal GND.Meanwhile, the discharge path of the primary nodal point NET1 illustrated in Fig. 3 is example.However, inventive concept Scope and spirit should not necessarily be limited by this.
Referring to figs. 1 to Fig. 3, the discharge operation with regard to primary nodal point NET1 is below described.When data D have high level and When the voltage of secondary nodal point NET2 has high level, the voltage of primary nodal point NET1 may be in response to the clock CLK with high level It is discharged.Now, the combination logic 130 for illustrating in Fig. 2 can be generated with low level logical signal LS.Because the first connection section The voltage of point CN1 is low level, so while the voltage of primary nodal point NET1 is discharged, logical signal LS can maintain low Level.Therefore, the voltage of secondary nodal point NET2 substantially can not be discharged.
Fig. 4 is the circuit diagram of the example discharge path for illustrating the secondary nodal point NET2 illustrated in Fig. 1.
With reference to Fig. 4, the available nmos pass transistor N21 and N22 being connected in series realizes the discharge path of secondary nodal point NET2.
Referring to figs. 1 to Fig. 4, the example discharge operation with regard to secondary nodal point NET2 is below described.When primary nodal point NET1's When voltage is high level, the voltage of secondary nodal point NET2 is low level, and data D have low level, combination logic 130 AOI doors 132 can generate the logical signal LS with high level.The voltage of secondary nodal point NET2 may be in response to patrolling with high level Collect the signal LS and clock CLK with high level with reference to the sequence circuit 100 illustrated in Fig. 1 to be discharged.Identical or basic Upper identical time (for example, simultaneously and/or concomitantly), primary nodal point NET1 may be in response to low level secondary nodal point NET2 Voltage by power supply terminal VDD charge and can keep or maintenance voltage be in high level.When secondary nodal point NET2 is discharged, Can suppress, prevent and/or prevent the electric discharge of (for example, preventing completely) primary nodal point NET1.
As with reference to described in Fig. 3 and Fig. 4, one in for primary nodal point NET1 and secondary nodal point NET2 executes electric discharge (for example, preventing completely) during operation, can be suppressed, prevent and/or prevent based on the logical signal LS provided from combination logic 130 Discharge operation with regard to other in which node.
Fig. 5 is the circuit diagram of the example embodiment for illustrating the latch cicuit 140 illustrated in Fig. 1.
Referring to figs. 1 to Fig. 5, latch cicuit 140 may include PMOS transistor P41, nmos pass transistor N41 and N42 and delay Rush device BUF.PMOS transistor P41 may be in response to the voltage of secondary nodal point NET2 and power supply terminal VDD be connected to output node OUT.Nmos pass transistor N41 may be connected to output node OUT and may be in response to clock CLK to operate.Nmos pass transistor N42 can In response to the voltage of secondary nodal point NET2, the drain terminal of nmos pass transistor N41 is connected to ground terminal GND.Buffer BUF can The voltage of Buffer output node OUT.In at least one example embodiment, buffer BUF may be in response to clock CLK be activated or Person may be in response to the anti-phase form of the voltage of secondary nodal point NET2 and be activated.
The order of the nmos pass transistor N41 and N42 that are connected in series as shown in Figure 5 is example.However, the model of inventive concept Enclose this is should not necessarily be limited by with spirit.For example, the position of the nmos pass transistor N41 and N42 that are connected in series is interchangeable.
Sequence circuit according at least one example embodiment of inventive concept can be implemented as receiving scanning signal.Sequential Circuit can be used as a part for the scan chain for being scanned test operation.
Fig. 6 is the diagram of the sequence circuit for illustrating another example embodiment according to inventive concept.
With reference to Fig. 6, sequence circuit 200 may include the first order 210, the second level 220, combination logic 230 and latch cicuit 240.Compared to the first order 110 illustrated in Fig. 1, the first order 210 of sequence circuit 200 may also include：PMOS transistor P13 and P14 and nmos pass transistor N12 and N13, connect to receive the scanning associated with scanning signal input SI and scan enable signal SE；And nmos pass transistor N14, connect to receive the voltage of secondary nodal point NET2.The configuration of the first order 210 is example, invention The scope and spirit of design should not necessarily be limited by this.For example, the first PMOS transistor P11 and the 3rd PMOS transistor P13 and The position of four PMOS transistors P14 is interchangeable.
Additionally, compared to the combination logic 130 illustrated in Fig. 1 and Fig. 2, the combination logic 230 of sequence circuit 200 may include AOI doors 232, the other anti-phase form (for example ,/SE) for receiving scan enable signal SE of AOI doors 232.
The second level 220 can be identical or substantially the same with the second level 120 illustrated in Fig. 1.
Latch cicuit 240 can be similar to the latch cicuit 140 illustrated in Fig. 1, but may also include and be attached to latch 242 The phase inverter 244 of output.Latch 242 can be identical or substantially the same with the latch cicuit 140 in Fig. 1.Phase inverter 244 can Will be anti-phase for the output of latch 242.
At least one example embodiment of inventive concept is illustrated as scanning input SI and scan enable signal SE is transfused to The first order 210 in the sequence circuit 200 illustrated in Fig. 6.However, the scope and spirit of inventive concept should not necessarily be limited by this. For example, scanning input SI and scanning may be implemented such that according to the sequence circuit of at least one example embodiment of inventive concept Enable signal SE and be imported into combination logic.
Fig. 7 is the diagram of the sequence circuit for illustrating another example embodiment according to inventive concept.
With reference to Fig. 7, sequence circuit 300 may include the first order 310, the second level 320, combination logic 330 and latch cicuit 340.
Compared to the sequence circuit 200 illustrated in Fig. 6, sequence circuit 300 may include to be configured to different from sequence circuit 200 scan the combination logic 330 for being input into SI and scan enable signal SE and generating logical signal LS in addition to receive.
Combination logic 330 may include phase inverter 331, AOI doors 332 and multiplexer 333.Multiplexer 333 can quilt It is embodied as selecting an input as AOI doors 332 in data D and scanning input SI in response to scan enable signal SE. The configuration of the combination logic 330 illustrated in Fig. 7 is example, and the scope and spirit of inventive concept should not necessarily be limited by this.
The first order 310 can be identical or substantially the same with the first order 110 and the second level 220 respectively with the second level 320.Latch Circuit 340 may include latch 342 and phase inverter 344.Latch 342 and phase inverter 344 can respectively with latch 242 and anti-phase Device 244 is identical or substantially the same.
With regard to be implemented as data path and scanning pattern with shared structure come describe inventive concept at least some Example embodiment.However, the scope and spirit of inventive concept should not necessarily be limited by this.For example, can use and divide data path and scanning The structure in path is realizing the sequence circuit of the example embodiment according to inventive concept.
Fig. 8 is the diagram of the sequence circuit for illustrating another example embodiment according to inventive concept.
With reference to Fig. 8, sequence circuit 400 may include the first order 410, the second level 420, combination logic 430 and latch cicuit 440.
The first order 410 receives scanning input SI by the different configuration of the sequence circuit 300 from Fig. 7, and combines and patrol Volumes 430 by the different configuration of the sequence circuit 300 from Fig. 7 come receiving data D.
The first order 410 may include：Primary nodal point NET1 is connected in response to clock CLK by the first PMOS transistor P11 The common node of both three PMOS transistors P13 and the 4th PMOS transistor P14；Second PMOS transistor P12, in response to second Primary nodal point NET1 is connected to power supply terminal VDD by the voltage of node NET2；3rd PMOS transistor P13, defeated in response to scanning Enter SI and one end of the first PMOS transistor P11 is connected to power supply terminal VDD；4th PMOS transistor P14, makes in response to scanning Described one end of first PMOS transistor P11 is connected to power supply terminal VDD by energy signal SE；First nmos pass transistor N11, response The first connecting node CN1 is connected to primary nodal point NET1 in clock CLK；Second nmos pass transistor N12, in response to scanning input One end of 3rd nmos pass transistor N13 is connected to primary nodal point NET1 by SI；And the 3rd nmos pass transistor N13, in response to sweeping Retouch the described one end for enabling that the second connecting node CN2 is connected to signal SE the second nmos pass transistor N12.The first order 410 is matched somebody with somebody It is example to put, and the scope and spirit of inventive concept should not necessarily be limited by this.For example, the second nmos pass transistor N12 for being connected in series and The position of the 3rd nmos pass transistor N13 is interchangeable.
Combination logic 430 may include：Phase inverter 431, by the voltage inversion of primary nodal point NET1；PMOS transistor P31, rings The common node of PMOS transistor P31, P32 and P33 should be connected to the first company in the reverse voltage/NET1 of primary nodal point NET1 Meet node CN1；One end of PMOS transistor P31 is connected to power supply terminal VDD in response to data D by PMOS transistor P32； Described one end of PMOS transistor P31 is connected to power end in response to anti-phase scan enable signal/SE by PMOS transistor P33 Sub- VDD；Described one end of PMOS transistor P31 is connected to electricity by PMOS transistor P34, the voltage in response to secondary nodal point NET2 Source terminal VDD；Ground terminal GND is connected to by nmos pass transistor N31, the reverse voltage/NET1 in response to primary nodal point NET1 One connecting node CN1；One end of nmos pass transistor N33 is connected to the first connecting node in response to data by nmos pass transistor N32 CN1；Second connecting node CN2 is connected to nmos pass transistor in response to anti-phase scan enable signal/SE by nmos pass transistor N33 N32；And nmos pass transistor N34, ground terminal GND is connected to the second connecting node by the voltage in response to secondary nodal point NET2 CN2.The configuration of combination logic 430 is example, and the scope and spirit of inventive concept should not necessarily be limited by this.For example, it is connected in series The position of PMOS transistor P31 and PMOS transistor P32, P33 and P34 is interchangeable.Additionally, nmos pass transistor N32, N33 and N34 Position differently can exchange.
The second level 420 can be identical with the second level 120 or substantially the same.Latch cicuit 440 may include latch 442 and anti- Phase device 444.Latch 442 can be identical or substantially the same with latch 242 and phase inverter 244 respectively with phase inverter 444.
The sequence circuit 300 that illustrate in the Fig. 7 with reference to Fig. 8 descriptions is different from, can be used and be divided scanning pattern and data path Structure realizing sequence circuit 400.
Fig. 9 is the diagram in the sample scan path in the sequence circuit 400 for illustrate Fig. 8.
With reference to Fig. 8 and Fig. 9, when scan enable signal SE is in high level, scanning pattern can be formed.Even if working as from Fig. 8 Sequence circuit 400 component among to remove PMOS transistor P14 that is insignificant or not operated and P33 and NMOS brilliant Body pipe N11, N13, N32, N33, the scan enable signal SE formation also dependent on high level are identical with shown in Fig. 8 or basic Upper identical scanning pattern.Scanning pattern according to the example embodiment of inventive concept may include by Fig. 8 transistor P31, The phase inverter 434 of P32, P34 and N31 composition.The phase inverter 434 of scanning pattern is not appeared on data path.Therefore, sequential Circuit 400 may be designed such that the speed of operation of scanning pattern is slower than the speed of operation of data path.
Sequence circuit according at least one example embodiment of inventive concept can be implemented as receiving reset signal.
Figure 10 is the diagram of the sequence circuit for illustrating another example embodiment according to inventive concept.
With reference to Figure 10, sequence circuit 500 may include the first order 510, the second level 520, combination logic 530 and latch cicuit 550.
The first order 510 can be identical or substantially the same with the first order 410 and combination logic 430 respectively with combination logic 530.
The second level 520 is configured to the second level different from the sequence circuit 400 illustrated in Fig. 8, resets letter to receive Number R.
The second level 520 may include：PMOS transistor P23, brilliant in response to reset signal R connection power supply terminal VDD and PMOS The common node of both body pipe P21 and P22；And nmos pass transistor N23, in response to reset signal R by ground terminal GND and second Node NET2 connects.Here, reset signal R can be imported into the replacement port of latch 542.
Latch cicuit 550 may include latch 542 and phase inverter 544.Latch 542 and phase inverter 544 can respectively with lock Storage 242 is identical with phase inverter 244 or substantially the same.
Can various forms of structures be transformed into the AOI doors illustrated in Fig. 2 to Figure 10 to realize according to inventive concept The sequential chart of at least one example embodiment.
Figure 11 is the example embodiment of the sequence circuit for illustrating that the AOI doors of the sequence circuit 400 illustrated in Fig. 8 occur to change Circuit diagram.
With reference to Figure 11, sequence circuit 600 may include that PMOS transistor P34, PMOS transistor P34 have and illustrate in Fig. 8 The different connection of sequence circuit 400.PMOS transistor P34 may be in response to the voltage of secondary nodal point NET2 by power supply terminal VDD It is connected to the first connecting node CN1.
Figure 12 is another example for the sequence circuit for illustrating that the AOI doors of the sequence circuit 400 illustrated in Fig. 8 occur to change The circuit diagram of embodiment.
With reference to Figure 12, sequence circuit 700 may include that nmos pass transistor N31, nmos pass transistor N31 have and illustrate in Fig. 8 The different connection of sequence circuit 400.Nmos pass transistor N31 may be in response to the reverse voltage/NET1 of primary nodal point NET1 by One connecting node CN1 is connected to the second connecting node CN2.
Figure 13 is another example for the sequence circuit for illustrating that the AOI doors of the sequence circuit 400 illustrated in Fig. 8 occur to change The circuit diagram of embodiment.
With reference to Figure 13, sequence circuit 800 may include PMOS transistor P34 and nmos pass transistor 31, PMOS transistor P34 and Nmos pass transistor N31 has the connection different from the sequence circuit 400 illustrated in Fig. 8.PMOS transistor P34 may be in response to second Power supply terminal VDD is connected to the first connecting node CN1 by the voltage of node NET2.Nmos pass transistor N31 may be in response to first segment First connecting node CN1 is connected to the second connecting node CN2 by the reverse voltage/NET1 of point NET1.
Electric discharge road with regard to the first order in the sequence circuit that illustrates in the Fig. 1 to Figure 13 using a part for combination logic Footpath is describing the example embodiment of inventive concept.However, the scope and spirit of inventive concept should not necessarily be limited by this.For example, invent The sequence circuit of at least some example embodiment of design may include the discharge path in the first order, and not consider combination logic.
Figure 14 is the diagram of the sequence circuit for illustrating another example embodiment according to inventive concept.
With reference to Figure 14, sequence circuit 900 may include the first order 910, the second level 920, combination logic 930 and latch cicuit 940.The second level 920, combination logic 930 and latch cicuit 940 can respectively with the second level 120, combination logic 130 and latch cicuit 140 is identical or substantially the same.
The first order 910 of sequence circuit 900 can be similar to the first order 110 in Fig. 1, but may also include and be connected to the first company Connect the discharge circuit 192 between node CN1 and ground terminal GND.Can be by the discharge circuit 192 that do not associate with combination logic 930 To execute the discharge operation of the primary nodal point NET1 with regard to the first order 910.
As shown in Figure 14, discharge circuit 192 may include：Nmos pass transistor N15, in response to data D by nmos pass transistor One end of N17 is connected to the first connecting node CN1；Nmos pass transistor N16, is parallel-connected to nmos pass transistor N15；And NMOS Ground terminal GND is connected to the public affairs of both nmos pass transistor N15 and N16 for transistor N17, the voltage in response to secondary nodal point NET2 Conode.In at least one example embodiment, the gate terminal of nmos pass transistor N16 may be connected to the defeated of combination logic 930 Go out terminal.The discharge circuit illustrated in Figure 14 is example, and the scope and spirit of inventive concept should not necessarily be limited by this.
Figure 15 is the flow chart of the operational approach of the sequence circuit for illustrating the example embodiment according to inventive concept.Hereinafter, The operational approach of sequence circuit will be described referring to figs. 1 to Figure 15.
With reference to Figure 15, clock CLK, data D or logical signal LS supply voltages is may be in response to primary nodal point NET1's The voltage of voltage and/or secondary nodal point NET2 is charged (S110).May be in response to voltages of the clock CLK to primary nodal point NET1 Discharged (S120).May be in response to data D, clock CLK and logical signal LS to discharge the voltage of secondary nodal point NET2. Here, logical signal LS can be generated from the combination logic described referring to figs. 1 to Figure 14.Combination logic can generate logical signal LS so that the voltage of primary nodal point NET1 is not discharged or causes to work as first segment when the voltage of secondary nodal point NET2 is discharged When the voltage of point NET1 is discharged, the voltage of secondary nodal point NET2 is not discharged.
Hereafter, can latch and corresponding data whether are discharged with the voltage of secondary nodal point NET2, and sequence circuit can be by The data of latch are worth (for example, Q or/Q) output as a result.In at least one example embodiment, it is capable of the data of latch Anti-phase.
Additionally, sequence circuit may be in response to reset signal R by the voltage of primary nodal point NET1 or the electricity of secondary nodal point NET2 Ballast is put.
Meanwhile, with reference to the latch operation that Figure 15 describes data.However, at least one example embodiment according to inventive concept Sequence circuit may be in response to scan enable signal SE formed scanning pattern so that latch be input to scanning pattern Scanning input SI.
In the operational approach of the sequence circuit with reference to Figure 15 descriptions, the quantity of the order of explanation or step or operation is not The scope and spirit of inventive concept should be limited.For example, can execution step S120 and S130 sequentially or in parallel.
Figure 16 is the sequential chart of the exemplary operations sequential of the sequence circuit for illustrating the example embodiment according to inventive concept.With Under, the operation of sequence circuit will be described with reference to Figure 15 and Figure 16.
As shown in Figure 16, the electric discharge of the secondary nodal point of the primary nodal point and the second level of the controllable first order of combination logic, So that primary nodal point is discharged in the interim very first time and secondary nodal point is discharged during the second time interval, its In, very first time interval is different underlapped time intervals with the second time interval.
With reference to Figure 15 and Figure 16, during the T1 of interval (in S110), low level clock CLK, low level is may be in response to Data D and the logical signal LS of high level the voltage of secondary nodal point NET2 is charged.In this case, primary nodal point The voltage of NET1 can maintain high level.During the T2 of interval (in S130), may be in response to clock CLK with high level, There is low level data D and the logical signal LS with high level the voltage of secondary nodal point NET2 is discharged.At interval During T3 (in S110), when assuming that data D change, logical signal LS can be transformed into low level from high level.Now, can ring Ying Yu have low level clock CLK, change before low level data D and change before high level logical signal LS The voltage of secondary nodal point NET2 is charged.Additionally, the voltage of primary nodal point NET1 continuously or substantially continuously can be tieed up Hold in high level.During the T4 of interval (in S130), the transformation of data D can be completed.May be in response to the clock with high level CLK, have high level data D and the voltage of primary nodal point NET1 is discharged with low level logical signal LS.This When, the voltage of secondary nodal point NET2 can maintain high level.In this case, lead-out terminal Q exportable with high level with The corresponding voltage of the voltage of secondary nodal point NET2.During the T5 of interval (in S110), may be in response to low level clock CLK, have high level data D and the voltage of primary nodal point NET1 is charged with low level logical signal LS.This When, the voltage of secondary nodal point NET2 can maintain high level, and lead-out terminal Q can maintain high level.The sequential illustrated in Figure 16 It is example, the scope and spirit of inventive concept should not limited to this.
Sequence circuit according at least some example embodiment of inventive concept can be applicable to solid-state drive (SSD) extremely A kind of few configuration.
Figure 17 is the block diagram of the SSD for illustrating the example embodiment according to inventive concept.
With reference to Figure 17, SSD 1000 may include multiple nonvolatile memories 1100 and SSD controller 1200.
Nonvolatile memory 1100 can be implemented as alternatively receiving external high voltage Vppx.Nonvolatile memory 1100 may include that the multiple nonvolatile memories for being connected respectively to multiple channel C H1 to CHi are encapsulated.In this illustration, " i " It is the integer of two or more.
SSD controller 1200 can be connected to nonvolatile memory 1100 by channel C H1 to CHi respectively.SSD controller 1200 may include at least one processor 1210, buffer storage 1220, error correcting code (ECC) circuit 1230, HPI 1240 With non-volatile memory interface 1250.
Processor 1210 can be implemented as the overall operation for processing SSD controller 1200.Processor 1210 may include multiple Sequence circuit FF1 and FF2.Here, can be realized in sequence circuit FF1 and FF2 with the sequence circuit described with reference to Fig. 1 and Figure 16 Each.It is 2 that the example embodiment of inventive concept is illustrated as the quantity of the sequence circuit FF1 and FF2 being connected in series.So And, the scope and spirit of inventive concept should not necessarily be limited by this.
Buffer storage 1220 can be stored temporarily in the data used in the operation of SSD controller 1200.Buffer storage The 1220 a plurality of memory lines that may include data storage or order.Here, a plurality of memory lines can be mapped using various methods Arrive cache line.The buffer storage 1220 that at least some example embodiment of inventive concept is illustrated as in Figure 17 is arranged In SSD controller 1200.However, the scope and spirit of inventive concept can not limited to this.For example, according to the example of inventive concept The buffer storage 1220 of embodiment can be disposed in outside SSD controller 1200.
ECC circuit 1230 can calculate the value of the error correcting code by data are programmed that in write operation, can be based on error correcting code Value is correcting the data read in read operation, and/or the mistake that recoverable is repaired from nonvolatile memory 1100.Invention structure The example embodiment of think of is illustrated as with regard to ECC circuit 1230 by sector detection and correction mistake.However, the scope of inventive concept Can not limited to this with spirit.
ECC circuit 1230 can generate in the data received from nonvolatile memory 1100 invalid bit (fail bit) or For correcting the error correcting code (ECC) of error bit.ECC circuit 1230 can be held for the data for providing nonvolatile memory 1100 Row error correction is encoded and can generate the data of interpolation parity check bit.Parity check bit can be stored in non-volatile memories In device 1100.Additionally, the data that ECC circuit 1230 can be directed to from the output of nonvolatile memory 1100 execute error correction solution Code.ECC circuit 1230 can correct mistake using parity check bit.Although not shown, can also wrap in SSD controller 1200 Code memory is included, code memory stores the code data for the operation of SSD controller 1200.Available non-volatile memory To realize code memory.
HPI 1240 can provide for the interface function being connected with external device interface.HPI 1240 can pass through Parallel Advanced Technology adnexa (PATA) bus, Serial Advanced Technology adnexa (SATA) bus, small computer system interface (SCSI), USB (universal serial bus) (USB), periphery component interconnection quick (PCIe), secure digital (SD), Serial Attached SCSI (SAS) (SAS), generic flash memory (UFS), embedded multi-media card (eMMC), multimedia card (MMC), NAND Interface etc. are connected to External host.Non-volatile memory interface 1250 can be provided between SSD controller 1200 and nonvolatile memory 1100 Interface function.Although not shown, SSD controller 1200 can install radio communication function (for example, WiFi).
As high-speed sequential logic circuits FF1 and FF2 are applied to processor 1210, therefore according at least one of inventive concept The SSD 1000 of example embodiment may include processor 1210.Therefore, SSD 1000 can be operated under relatively high clock frequency.
Figure 18 is the block diagram of the electronic installation 2000 for illustrating the example embodiment according to inventive concept.
With reference to Figure 18, electronic installation 2000 may include at least one processor 2100, the storage of buffer storage 2200, code Device 2300, non-volatile memory interface 2600, non-volatile memory device 2700 and HPI 2800.Electronic installation 2000 can be in following device or two of which or the combination of more：Data storage medium (for example, drive by solid-state Dynamic device (SSD)), memory stick, generic flash memory (UFS) device), storage card (for example, secure digital (SD), multimedia card (MMC), embedded MMC (eMMC) etc.), smart card, mobile device (for example, smart phone and GalaxyTMSeries), intelligence electricity Words, tablet personal computer (PC), mobile phone, visual telephone, E-book reader, Desktop PC, PC on knee, net book meter Calculation machine, personal digital assistant (PDA), portable media player (PMP), MP3 player, portable medical device, electronic hand Bracelet, electronics necklace, electronic application accessory, camera, wearable device, electronic clock, watch, household electrical appliances device (for example, refrigerator, sky Tune, vacuum cleaner, baking box, microwave oven, washing machine, air filter etc.), artificial intelligence robot, TV (TV), numeral regard (for example, magnetic resonance angiography (MRA) camera, magnetic are common for frequency disk (DVD) player, audio system, various types of medical treatment devices Shake imaging (MRI) camera, computed tomography (CT) camera, ultrasonic machine etc.), guider, global positioning system (GPS) connect Receive device, event data recorder (EDR), flight data recorder (FDR), Set Top Box, TV boxes (for example, Samsung HomeSyncTM、Apple TVTMOr Google TVTM), electronic dictionary, automotive infotainment device, ship electronic equipment (example Such as, marine navigator, gyrocompass etc.), avionics system, safety device, electronic clothes, electron key, video camera, trip Play control station, head mounted display (HMD), panel display apparatus, digital photo frame, electron album, the building for including communication function The furniture or a part of thing or structure, electron plate, electronic signature reception device or projector.
Processor 2100 can be implemented as controlling the overall operation with regard to electronic installation 2000.Here, processor 2100 can Being CPU, application processor, graphic process unit etc..In at least one example embodiment, processor 2100 can Including safe processor or safety element (SE) etc..For example, processor 2100 can have anti-tamper function, to protected from usurping Change attack (such as, micro- detection, software attacks, eavesdropping, failure generation etc.).In at least one example embodiment, processor 2100 may include at least two the sequence circuit FF1 and FF2 that are connected in series.Here, the sequential described with reference to Fig. 1 and Figure 15 can be used Circuit is realizing each in sequence circuit FF1 and FF2.In at least one example embodiment, can be with identical or substantially phase With type sequence circuit realizing each in sequence circuit FF1 and FF2.In at least one other example embodiment In, each in sequence circuit FF1 and FF2 can be realized with different types of sequence circuit.
Buffer storage 2200 can be operated according to the control of processor 2100.Buffer storage 220 temporarily can be stored The data or available buffer processed by processor 2100 be sent to the data of non-volatile memory device 2700 or from non-easily The data that the property lost storage arrangement 2700 sends.In at least one example embodiment, buffer storage 2200 can be random Access memorizer (RAM), static RAM (SRAM) and phase change random access memory devices (PRAM).
Code memory 2300 can be implemented as storage to be used for managing or operating the code of electronic installation 2000 and/or answers With.In at least one example embodiment, code memory 2300 can be read only memory (ROM) or PRAM.Can pass through non- Volatile memory interface 2600 is executing the data exchange with non-volatile memory device 2700.HPI 2800 can lead to Cross Parallel Advanced Technology adnexa (PATA) bus, Serial Advanced Technology adnexa (SATA) bus, small computer system interface (SCSI), USB (universal serial bus) (USB), periphery component interconnection quick (PCIe), SD, Serial Attached SCSI (SAS) (SAS), UFS, EMMC, MMC, NAND Interface etc. are connected to external host.
Although not shown, electronic installation 2000 can install radio communication function (for example, WiFi).Meanwhile, electronic installation 2000 may also include the component not shown in Figure 18, or may not include at least one of component for illustrating in Figure 18 (except Outside cryptographic processing circuit).
Figure 19 is the block diagram of the mobile device 3000 for illustrating the example embodiment according to inventive concept.
With reference to Figure 19, mobile device 3000 may include processor (AP/ModAP) 3100, storage arrangement 3200, show/ Touch modules 3300 and buffer storage 3400.
Processor 3100 can be implemented as controlling the overall operation of mobile device 3000 and the wire/wireless with external device (ED) Communication.For example, processor 3100 can be that application processor (AP), integrated modem application processor (hereinafter, are claimed For " ModAP ") etc..Processor 3100 may include at least two sequence circuit FF 1 and FF2 referring to figs. 1 to Figure 14 descriptions.
In at least one example embodiment, processor 3100 can be realized with the sequence circuit described with reference to Fig. 1 and Fig. 6 Sequence circuit FF1 and FF2.In at least one other example embodiment, processor 3100 may include to be connected in series with sound The first sequence circuit FF1 and the second sequence circuit FF2 of sweep test should be executed in scanning signal.Here, can use with reference to Fig. 6 extremely The reception scanning of Figure 13 descriptions is input into the sequence circuit of SI and scan enable signal SE to realize the first sequence circuit FF1 and second Each in sequence circuit FF2.
Buffer storage 3400 can be implemented as the number that temporarily storage needs when mobile device 3000 is executed and processes operation According to.Display/touch modules 3300 can be implemented as showing from the data of the process of processor 3100 or receive number from touch panel According to.Storage device 3200 can be implemented as the data for storing user.Storage device 3200 can be eMMC, SSD, UFS etc..
Basis can be passed through according to the sequence circuit of one or more example embodiments of inventive concept and/or its operational approach Whether the state of the voltage of complementary node and data is put in response to logical signal and clock come the voltage for complementally determining node Electricity changes caused impact to suppress and/or minimize due to clock.
Can be by using 2 according to the sequence circuit of one or more example embodiments of inventive concept and/or its operational approach The nmos pass transistor of stack architecture is realized improving the velocity of discharge.Therefore, it can execute latch operation at a relatively high speed.
Can be made it possible to according to the sequence circuit of one or more example embodiments of inventive concept and/or its operational approach Clock frequency is improved by reducing setup time or CQ delays.
It should therefore be understood that example embodiment discussed here is not restricted, but illustrative.Although Inventive concept is described with reference to example embodiment, but those skilled in the art will be clear that, can be in the essence without departing from inventive concept Make various changes and modifications in the case of god and scope.

Claims (20)

1. a kind of sequence circuit, including：
The first order, is configured to respond to clock and the voltage of primary nodal point is charged, and in response to clock, secondary nodal point Voltage and data the voltage of primary nodal point is discharged；
The second level, is configured to respond to clock and the voltage of secondary nodal point is charged, and believes in response to clock and logic Number the voltage of secondary nodal point is discharged；
Combination logic, is configured with the voltage of primary nodal point, the voltage of secondary nodal point and data to generate logical signal；With And
Latch cicuit, is configured to respond to clock to latch the voltage of secondary nodal point,
Wherein, combination logic generates logical signal so that when the voltage of primary nodal point is discharged, the voltage of secondary nodal point not by Electric discharge, or cause when the voltage of secondary nodal point is discharged, the voltage of primary nodal point is not discharged.
2. sequence circuit according to claim 1, wherein, the first order includes：
First PMOS transistor, is configured to respond to clock and primary nodal point is connected to power supply terminal；
Primary nodal point is connected to power supply terminal by the second PMOS transistor, the voltage for being configured to respond to secondary nodal point；And
First nmos pass transistor, is configured to respond to clock and the first connecting node for providing logical signal is connected to first segment Point.
3. sequence circuit according to claim 2, wherein, the second level includes：
First PMOS transistor, is configured to respond to clock and secondary nodal point is connected to power supply terminal；
Secondary nodal point is connected to power supply terminal by the second PMOS transistor, the voltage for being configured to respond to primary nodal point；
First nmos pass transistor, with the one end for being connected to secondary nodal point in response to logical signal；And
Second nmos pass transistor, is configured to respond to the institute that ground terminal is connected to clock the first nmos pass transistor of the second level State one end,
Wherein, the first connecting node is connected to the gate terminal of the first nmos pass transistor of the second level.
4. sequence circuit according to claim 2, wherein, combination logic includes：
Phase inverter, is configured to the voltage inversion of primary nodal point；And
AOI (AOI) door, is configured to the output valve of the voltage, data and phase inverter of reception secondary nodal point, and generates logic Signal.
5. sequence circuit according to claim 4, wherein, AND OR NOT gate includes：
First nmos pass transistor, with the one end for being connected to the first connecting node in response to data；
Ground terminal is connected to the first of AND OR NOT gate for second nmos pass transistor, the voltage for being configured to respond to secondary nodal point Described one end of nmos pass transistor.
6. sequence circuit according to claim 1, wherein, latch cicuit includes：
Output node is connected to power supply terminal by the first PMOS transistor, the voltage for being configured to respond to secondary nodal point；
First nmos pass transistor, with the one end for being connected to output node in response to clock；
Second nmos pass transistor, is configured to respond to the voltage of secondary nodal point by the institute of the first nmos pass transistor of latch cicuit State one end and be connected to ground terminal；And
Buffer, is configured to the voltage of Buffer output node.
7. sequence circuit according to claim 6, wherein, latch cicuit also includes：
Phase inverter, is configured to the voltage inversion of output node.
8. sequence circuit according to claim 1, wherein, the first order includes：
First PMOS transistor, with the one end for being connected to primary nodal point in response to clock；
Primary nodal point is connected to power supply terminal by the second PMOS transistor, the voltage for being configured to respond to secondary nodal point；
3rd PMOS transistor, is configured to respond to scan input by one end company of the first PMOS transistor of the first order It is connected to power supply terminal；
4th PMOS transistor, is configured to respond to scan enable signal by described the one of the first PMOS transistor of the first order End is connected to power supply terminal；
First nmos pass transistor, is configured to respond to clock and the first connecting node for providing logical signal is connected to first segment Point；
Second nmos pass transistor, with the one end for being connected to primary nodal point in response to scanning input；
3rd nmos pass transistor, described with the second nmos pass transistor for being connected to the first order in response to scan enable signal The one end at end；And
4th nmos pass transistor, is configured to respond to the voltage of secondary nodal point by described in the 3rd nmos pass transistor of the first order One end is connected to ground terminal,
Wherein, combination logic includes：
Phase inverter, is configured to the voltage inversion of primary nodal point；And
AOI doors, are configured to output valve, anti-phase scan enable signal, the voltage of secondary nodal point and the data for receiving phase inverter, And logical signal is generated,
Wherein, the first connecting node is connected to the lead-out terminal of AOI doors.
9. sequence circuit according to claim 1, wherein, the first order includes：
First PMOS transistor, is configured to respond to clock and primary nodal point is connected to power supply terminal；
Primary nodal point is connected to power supply terminal by the second PMOS transistor, the voltage for being configured to respond to secondary nodal point；And
First nmos pass transistor, is configured to respond to clock and the first connecting node for providing logical signal is connected to first segment Point,
Wherein, combination logic includes：
Phase inverter, is configured to the voltage inversion of primary nodal point；
Multiplexer, be configured to respond to during scan enable signal selects data or scanning to be input into；And
AOI doors, are configured to the output valve of the output valve, the voltage of secondary nodal point and phase inverter of reception multiplexer, and raw Into logical signal,
Wherein, the first connecting node is connected to the lead-out terminal of AOI doors.
10. sequence circuit according to claim 1, wherein,
The first order includes：
First PMOS transistor, with the one end for being connected to primary nodal point in response to clock；
Primary nodal point is connected to power supply terminal by the second PMOS transistor, the voltage for being configured to respond to secondary nodal point；
3rd PMOS transistor, is configured to respond to scan input by one end company of the first PMOS transistor of the first order It is connected to power supply terminal；
4th PMOS transistor, is configured to respond to scan enable signal by described the one of the first PMOS transistor of the first order End is connected to power supply terminal；
First nmos pass transistor, is configured to respond to clock and the first connecting node for providing logical signal is connected to first segment Point；
Second nmos pass transistor, with the one end for being connected to primary nodal point in response to scanning input；And
3rd nmos pass transistor, be configured to respond to that the second connecting node is connected to scan enable signal the first order second Described one end of nmos pass transistor, and
Wherein, combination logic includes：
Phase inverter, is configured to the voltage inversion of primary nodal point；
First PMOS transistor, with one end that the output valve in response to phase inverter is connected to the first connecting node；
Second PMOS transistor, is configured to respond to data by one end connection of the first PMOS transistor of combination logic Arrive power supply terminal；
3rd PMOS transistor, is configured to respond to anti-phase scan enable signal by the first PMOS transistor of combination logic Described one end be connected to power supply terminal；
4th PMOS transistor, is configured to respond to the voltage of secondary nodal point by the institute of the first PMOS transistor of combination logic State one end and be connected to power supply terminal；
Ground terminal is connected to the first connecting node by the first nmos pass transistor, the output valve for being configured to respond to phase inverter；
Second nmos pass transistor, with the one end in response to data cube computation to the first connecting node；
3rd nmos pass transistor, is configured to respond to anti-phase scan enable signal by the second nmos pass transistor of combination logic Described one end be connected to the second connecting node；And
Ground terminal is connected to the second connecting node by the 4th nmos pass transistor, the voltage for being configured to respond to secondary nodal point.
A kind of 11. sequence circuits, including：The first order, the second level, combination logic and latch cicuit, wherein,
The first order, including：
First PMOS transistor, with the one end for being connected to primary nodal point in response to clock；
Primary nodal point is connected to power supply terminal by the second PMOS transistor, the voltage for being configured to respond to secondary nodal point；
3rd PMOS transistor, is configured to respond to scanning input and described one end of the first PMOS transistor is connected to power supply Terminal；
4th PMOS transistor, is configured to respond to scan enable signal and is connected to described one end of the first PMOS transistor Power supply terminal；
First nmos pass transistor, is configured to respond to clock and the first connecting node for providing logical signal is connected to first segment Point；
Second nmos pass transistor, with the one end for being connected to primary nodal point in response to scanning input；And
3rd nmos pass transistor, is configured to respond to scan enable signal and the second connecting node is connected to the 2nd NMOS crystal Described one end of pipe,
The second level, including：
First PMOS transistor, is configured to respond to clock and secondary nodal point is connected to power supply terminal；
Secondary nodal point is connected to power supply terminal by the second PMOS transistor, the voltage for being configured to respond to primary nodal point；
First nmos pass transistor, with the one end for being connected to secondary nodal point in response to logical signal；And
Second nmos pass transistor, is configured to respond to the institute that ground terminal is connected to clock the first nmos pass transistor of the second level State one end,
Combination logic, is configured to the voltage of receiving data, the voltage of primary nodal point and secondary nodal point, and generates logical signal, Wherein, the lead-out terminal of the combination logic of output logic signal is connected to the first connecting node,
Latch cicuit, is configured to respond to clock to latch the voltage of secondary nodal point.
12. sequence circuits according to claim 11, wherein, combination logic includes：
Phase inverter, is configured to the voltage inversion of primary nodal point；
First PMOS transistor, with one end that the output valve in response to phase inverter is connected to the first connecting node；
Second PMOS transistor, is configured to respond to data by one end connection of the first PMOS transistor of combination logic Arrive power supply terminal；
3rd PMOS transistor, the inversion signal for being configured to respond to scan enable signal are brilliant by a PMOS of combination logic Described one end of body pipe is connected to power supply terminal；
4th PMOS transistor, is configured to respond to the voltage of secondary nodal point by the institute of the first PMOS transistor of combination logic State one end and be connected to power supply terminal；
Ground terminal is connected to the first connecting node by the first nmos pass transistor, the output valve for being configured to respond to phase inverter；
Second nmos pass transistor, with the one end in response to data cube computation to the first connecting node；
3rd nmos pass transistor, is configured to respond to anti-phase scan enable signal by the second nmos pass transistor of combination logic Described one end be connected to the second connecting node；And
Ground terminal is connected to the second connecting node by the 4th nmos pass transistor, the voltage for being configured to respond to secondary nodal point.
13. sequence circuits according to claim 11, wherein, the second level also includes：
3rd PMOS transistor, is configured to respond to reset signal and is connected to one end of the first PMOS transistor of the second level Power supply terminal, and one end of the second PMOS transistor of the second level is connected to power supply terminal in response to reset signal；And
3rd nmos pass transistor, is configured to respond to reset signal and ground terminal is connected to secondary nodal point.
14. sequence circuits according to claim 11, wherein, combination logic includes：
Phase inverter, is configured to the voltage inversion of primary nodal point；
First PMOS transistor, with one end that the output valve in response to phase inverter is connected to the first connecting node；
Second PMOS transistor, is configured to respond to data by one end connection of the first PMOS transistor of combination logic Arrive power supply terminal；
3rd PMOS transistor, the inversion signal for being configured to respond to scan enable signal are brilliant by a PMOS of combination logic Described one end of body pipe is connected to power supply terminal；
First connecting node is connected to power supply terminal by the 4th PMOS transistor, the voltage for being configured to respond to secondary nodal point；
Ground terminal is connected to the first connecting node by the first nmos pass transistor, the output valve for being configured to respond to phase inverter；
Second nmos pass transistor, with the one end in response to data cube computation to the first connecting node；
3rd nmos pass transistor, is configured to respond to anti-phase scan enable signal by the second nmos pass transistor of combination logic Described one end be connected to the second connecting node；And
Ground terminal is connected to the second connecting node by the 4th nmos pass transistor, the voltage for being configured to respond to secondary nodal point.
15. sequence circuits according to claim 11, wherein, combination logic includes：
Phase inverter, is configured to the voltage inversion of primary nodal point；
First PMOS transistor, with one end that the output valve in response to phase inverter is connected to the first connecting node；
Second PMOS transistor, is configured to respond to data by one end connection of the first PMOS transistor of combination logic Arrive power supply terminal；
3rd PMOS transistor, the inversion signal for being configured to respond to scan enable signal are brilliant by a PMOS of combination logic Described one end of body pipe is connected to power supply terminal；
4th PMOS transistor, is configured to respond to the voltage of secondary nodal point by the institute of the first PMOS transistor of combination logic State one end and be connected to power supply terminal；
Second connecting node is connected to the first connection section by the first nmos pass transistor, the output valve for being configured to respond to phase inverter Point；
Second nmos pass transistor, with the one end in response to data cube computation to the first connecting node；
3rd nmos pass transistor, is configured to respond to anti-phase scan enable signal by the second nmos pass transistor of combination logic Described one end be connected to the second connection terminal；And
Ground terminal is connected to the second connecting node by the 4th nmos pass transistor, the voltage for being configured to respond to secondary nodal point.
16. sequence circuits according to claim 11, wherein, combination logic includes：
Phase inverter, is configured to the voltage inversion of primary nodal point；
First PMOS transistor, with one end that the output valve in response to phase inverter is connected to the first connecting node；
Second PMOS transistor, is configured to respond to data by one end connection of the first PMOS transistor of combination logic Arrive power supply terminal；
3rd PMOS transistor, the inversion signal for being configured to respond to scan enable signal are brilliant by a PMOS of combination logic Described one end of body pipe is connected to power supply terminal；
First connecting node is connected to power supply terminal by the 4th PMOS transistor, the voltage for being configured to respond to secondary nodal point；
Second connecting node is connected to the first connection section by the first nmos pass transistor, the output valve for being configured to respond to phase inverter Point；
Second nmos pass transistor, with the one end in response to data cube computation to the first connecting node；
3rd nmos pass transistor, is configured to respond to anti-phase scan enable signal by the second nmos pass transistor of combination logic Described one end be connected to the second connecting node；And
Ground terminal is connected to the second connecting node by the 4th nmos pass transistor, the voltage for being configured to respond to secondary nodal point.
A kind of 17. sequence circuits, including：
First order circuit；
Second level circuit；And
Combinational logic circuit, in conjunction between the secondary nodal point of the primary nodal point of first order circuit and second level circuit, combination is patrolled Volume circuit be configured to the voltage at the voltage at based on primary nodal point, secondary nodal point and entering data to control primary nodal point and The electric discharge of secondary nodal point so that primary nodal point is discharged in the interim very first time and secondary nodal point is in the second time interval Period is discharged, and wherein, very first time interval and the second time interval are different and nonoverlapping time intervals.
18. sequence circuits according to claim 17, also include：
Latch cicuit, is configured to respond to clock signal and latches the voltage at secondary nodal point.
19. sequence circuits according to claim 17, wherein
Combinational logic circuit is additionally configured to the logical signal for generating the electric discharge for being used for controlling primary nodal point and secondary nodal point, its In, based on the voltage at primary nodal point, the voltage at secondary nodal point and enter data to generate logical signal.
20. sequence circuits according to claim 19, wherein,
First order circuit is configured to be charged primary nodal point based on clock signal；
First order circuit is configured to put primary nodal point based on the voltage at clock signal, secondary nodal point and input data Electricity；
The second level is configured to be charged secondary nodal point based on clock signal；And
The second level is configured to discharge secondary nodal point based on clock signal and logical signal.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109462394A (en) * 2017-09-06 2019-03-12 三星电子株式会社 Sequence circuit
CN110431745A (en) * 2017-03-23 2019-11-08 高通股份有限公司 The device and method for latch data including AND-NOR or OR-NAND He feedback path
CN110932713A (en) * 2019-11-11 2020-03-27 东南大学 Timing elastic circuit for convolutional neural network hardware accelerator

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1929307A (en) * 2005-10-14 2007-03-14 威盛电子股份有限公司 N-domino output latch
US20100315144A1 (en) * 2009-06-16 2010-12-16 Hyoung-Wook Lee Flip-Flop Circuits and System Including the Same
CN102487270A (en) * 2010-12-02 2012-06-06 三星电子株式会社 Flip-flop circuit
CN103308851A (en) * 2012-03-16 2013-09-18 三星电子株式会社 Scan flip-flop, method thereof and devices having the same
CN104049713A (en) * 2013-03-14 2014-09-17 三星电子株式会社 Integrated clock gater (icg) using clock cascode complimentary switch logic
WO2014179944A1 (en) * 2013-05-08 2014-11-13 Qualcomm Incorporated Flip-flop for reducing dynamic power

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2735034B2 (en) * 1995-06-14 1998-04-02 日本電気株式会社 Clock signal distribution circuit
TW505804B (en) * 1998-02-19 2002-10-11 Hitachi Ltd Liquid crystal display device
US20040153926A1 (en) * 2002-10-30 2004-08-05 Abdel-Hafez Khader S. Method and apparatus for testing asynchronous set/reset faults in a scan-based integrated circuit
US7157930B2 (en) 2003-12-22 2007-01-02 Matsushita Electric Industrial Co., Ltd. Scan flip flop, semiconductor device, and production method of semiconductor device
US6972605B1 (en) 2004-03-25 2005-12-06 Sun Microsystems, Inc. High speed semi-dynamic flip-flop circuit
KR101045295B1 (en) 2004-04-29 2011-06-29 삼성전자주식회사 MTCMOS flip-flop, MTCMOS circuit including the same, and method for generating the same
JP2007028532A (en) 2005-07-21 2007-02-01 Matsushita Electric Ind Co Ltd Flip-flop circuit
WO2007046368A1 (en) 2005-10-18 2007-04-26 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit
US7665001B2 (en) * 2006-09-25 2010-02-16 Wisconsin Alumni Research Foundation Progressive random access scan circuitry
US8593194B2 (en) 2010-11-30 2013-11-26 Marvell Israel (M.I.S.L) Ltd. Race free semi-dynamic D-type flip-flop
US8508275B2 (en) 2011-10-11 2013-08-13 Oracle International Corporation Semi-dynamic flip-flop with partially floating evaluation window
TWI508450B (en) 2013-04-10 2015-11-11 Mstar Semiconductor Inc Semi-dynamic flip-flop

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1929307A (en) * 2005-10-14 2007-03-14 威盛电子股份有限公司 N-domino output latch
US20100315144A1 (en) * 2009-06-16 2010-12-16 Hyoung-Wook Lee Flip-Flop Circuits and System Including the Same
CN102487270A (en) * 2010-12-02 2012-06-06 三星电子株式会社 Flip-flop circuit
CN103308851A (en) * 2012-03-16 2013-09-18 三星电子株式会社 Scan flip-flop, method thereof and devices having the same
CN104049713A (en) * 2013-03-14 2014-09-17 三星电子株式会社 Integrated clock gater (icg) using clock cascode complimentary switch logic
WO2014179944A1 (en) * 2013-05-08 2014-11-13 Qualcomm Incorporated Flip-flop for reducing dynamic power

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110431745A (en) * 2017-03-23 2019-11-08 高通股份有限公司 The device and method for latch data including AND-NOR or OR-NAND He feedback path
CN109462394A (en) * 2017-09-06 2019-03-12 三星电子株式会社 Sequence circuit
CN109462394B (en) * 2017-09-06 2023-10-20 三星电子株式会社 sequential circuit
CN110932713A (en) * 2019-11-11 2020-03-27 东南大学 Timing elastic circuit for convolutional neural network hardware accelerator
CN110932713B (en) * 2019-11-11 2023-05-16 东南大学 Time sequence elastic circuit for convolutional neural network hardware accelerator

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