CN106505031A - A kind of manufacture method of copper interconnection structure, copper interconnection structure and electronic installation - Google Patents
A kind of manufacture method of copper interconnection structure, copper interconnection structure and electronic installation Download PDFInfo
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- CN106505031A CN106505031A CN201510563368.3A CN201510563368A CN106505031A CN 106505031 A CN106505031 A CN 106505031A CN 201510563368 A CN201510563368 A CN 201510563368A CN 106505031 A CN106505031 A CN 106505031A
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- interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53233—Copper alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
Abstract
The present invention provides a kind of manufacture method of copper interconnection structure, copper interconnection structure and electronic installation, and the manufacture method includes：Semiconductor substrate is provided, forms the fluted interlayer dielectric layer of tool on the semiconductor substrate；Dielectric barrier layer is formed on the trenched side-wall；Electrically conductive barrier is formed on the dielectric barrier layer；In the remainder filler metal copper of the groove, to form the copper interconnection structure.The manufacture method of copper interconnection structure proposed by the present invention, due to using dielectric barrier layer and electrically conductive barrier two-layer barrier layer, so ensureing certain blocking capability, on the premise of preventing copper to be diffused in dielectric layer, the thickness of electrically conductive barrier can suitably be reduced again, so that the thickness relative increase of the layers of copper for interconnecting, and then reduce interconnection resistance, improve the electric property of device.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor device and its
Manufacture method, electronic installation.
Background technology
With the development of semiconductor technology, integrated circuit is gradually to super large-scale integration
(ULSI) develop, the characteristic size of its internal circuit is less and less, and density is increasing,
Contained number of elements is continuously increased.Copper becomes integrated circuit technique by its excellent electric conductivity
One of solution of interconnection integration technology in field.
In the copper wiring technique of back segment operation (BEOL), with the diminution of device size,
For interconnect copper volume also reduce, and copper volume reduce and dimensional effect can cause mutually
Even resistance increase, device electric property decline problem (that is, RC retardation ratio increase).For reduce by
Reduce in copper volume and dimensional effect can cause interconnection resistance to increase, people attempt various sides
Method, one of most promising method is to reduce the metal barrier between copper and dielectric layer among these
The thickness of (metal liner), but needing in this way to introduce (surpasses to copper and ULK
Low K) oxide there is high stepcoverage (step coverage), high diffusivity resistance (diffusion
Resitance material), and this material is not readily available and/or prepares.
Therefore, it is necessary to a kind of new manufacture method is proposed, to solve the above problems.
Content of the invention
A series of concept of reduced forms is introduced in Summary, and this will be concrete real
Apply in mode part and further describe.The Summary of the present invention is not meant to
Attempt key feature and the essential features for limiting technical scheme required for protection, less
Mean the protection domain for attempting to determine technical scheme required for protection.
In order to overcome the problem that presently, there are, one aspect of the present invention to provide a kind of copper interconnection structure
Manufacture method, the method include：Semiconductor substrate is provided, is formed on the semiconductor substrate
Has fluted interlayer dielectric layer；Dielectric barrier layer is formed on the trenched side-wall；Described
Electrically conductive barrier is formed on dielectric barrier layer；In the remainder filler metal copper of the groove,
To form the copper interconnection structure.
Further, the method also includes：Conductive layer is formed in the channel bottom, with
Layer layer metal interconnection.
Further, the dielectric barrier layer of expectation thickness is formed by ald.
Further, the dielectric barrier layer is formed by following step：In the trenched side-wall
Three silicon substrate N2 adsorption layers of upper formation；The three silicon substrates N2 adsorption layer is processed with nitrogen or ammonia, with
Silicon nitride layer is formed on the trenched side-wall；Repeat the above steps, on the trenched side-wall
The silicon nitride layer of expectation thickness is formed, for use as the dielectric barrier layer.
Further, the conductive layer is formed by following step：Inhale on the channel bottom
Annex III silicon substrate N2 adsorption layer；The three silicon substrates N2 adsorption layer is processed with nitrogen or ammonia, with institute
State formation CuSiN layers on channel bottom；Repeat the above steps, shape on the channel bottom
Into the CuSiN layers of expectation thickness, for use as the conductive layer.
The manufacture method of copper interconnection structure proposed by the present invention, due to using dielectric barrier layer and leading
Electrical barrier two-layer barrier layer, is so ensureing certain blocking capability, is preventing copper to be diffused into dielectric
On the premise of in layer, can suitably reduce the thickness of electrically conductive barrier again, so that being used for interconnecting
Layers of copper thickness relative increase, and then reduce interconnection resistance, improve device electric property.
Another aspect of the present invention provides a kind of copper interconnection structure for semiconductor device, including：
Semiconductor substrate, the fluted interlayer dielectric layer of the tool for being formed on the semiconductor substrate,
The dielectric barrier layer sequentially formed on the trenched side-wall and electrically conductive barrier, and filling is described
The layers of copper of groove remainder.
Further, the copper interconnection structure also includes the conductive layer positioned at the channel bottom, uses
In interconnecting with lower metal layer.
Further, the dielectric barrier layer is nitride.
Further, the conductive layer is CuSiN.
Copper interconnection structure proposed by the present invention, due to using dielectric barrier layer and electrically conductive barrier two
Layer barrier layer, is so ensureing certain blocking capability, is preventing copper to be diffused into the premise in dielectric layer
Under, can suitably reduce the thickness of electrically conductive barrier again, so that the thickness of the layers of copper for interconnecting
Degree relative increase, and then reduce interconnection resistance, improve the electric property of device.
Further aspect of the present invention provides a kind of electronic installation, and which includes above-mentioned the half of present invention offer
Conductor device.
Electronic installation proposed by the present invention, due to above-mentioned copper interconnection structure, thus has class
As advantage.
Description of the drawings
The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention.Attached
Embodiments of the invention and its description is shown in figure, for explaining the principle of the present invention.
In accompanying drawing：
Fig. 1 shows the step of the manufacture method of copper interconnection structure according to an embodiment of the present invention
Rapid flow chart；
Fig. 2A～Fig. 2 F show the making side of copper interconnection structure according to an embodiment of the present invention
Method implements the generalized section of the obtained device of each step successively；
Fig. 3 shows the copper-connection for semiconductor device according to an embodiment of the present invention
The schematic diagram of structure.
Specific embodiment
In the following description, a large amount of concrete details are given to provide to the present invention more
Thoroughly understand.It is, however, obvious to a person skilled in the art that of the invention
Can be carried out without the need for one or more of these details.In other examples, in order to keep away
Exempt to obscure with the present invention, for some technical characteristics well known in the art are not described.
It should be appreciated that the present invention can be implemented in different forms, and it is not construed as office
It is limited to embodiments presented herein.Disclosure will be made thoroughly and complete on the contrary, providing these embodiments
Entirely, and those skilled in the art will fully convey the scope of the invention to.In the accompanying drawings,
In order to clear, the size and relative size in Ceng He areas may be exaggerated.Identical attached from start to finish
Icon note represents identical element.
It should be understood that be referred to as when element or layer " ... on ", " with ... adjacent ", " being connected to "
Or when " being coupled to " other elements or layer, its can directly on other elements or layer and
Adjacent, be connected or coupled to other elements or layer, or there may be element between two parties or layer.
Conversely, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " being directly connected to "
Or when " being directly coupled to " other elements or layer, then there is no element between two parties or layer.Should
Understand, although can using term first, second, third, etc. describe various elements, part,
Area, floor and/or part, these elements, part, area, floor and/or part should be by these
Term is limited.These terms be used merely to distinguish an element, part, area, floor or part with
Another element, part, area, floor or part.Therefore, without departing from present invention teach that under,
First element discussed below, part, area, floor or part be represented by the second element, part,
Area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... it
Under ", " ... on ", " above " etc., can describe for convenience here and used from
And an element shown in figure or feature are described with other elements or the relation of feature.Should be bright
In vain, in addition to the orientation shown in figure, spatial relationship term is intended to also include using and operate
In device different orientation.For example, if the device upset in accompanying drawing, then, is described as
" below other elements " or " under it " or " under which " element or feature will be orientated
Be other elements or feature " on ".Therefore, exemplary term " ... below " and " ...
Under " may include upper and lower two orientations.Device can additionally be orientated and (be rotated by 90 ° or other
Orientation) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as this
Bright restriction.When here is used, " one " of singulative, " one " and " described/should "
It is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that art
Language " composition " and/or " including ", when in this specification use when, determine the feature,
The presence of integer, step, operation, element and/or part, but be not excluded for one or more its
The presence or interpolation of its feature, integer, step, operation, element, part and/or group.
When here is used, term "and/or" includes any and all combination of related Listed Items.
The present invention proposes a kind of manufacture method of copper interconnection structure, for forming copper interconnection structure,
The method includes：Semiconductor substrate is provided, forms tool on the semiconductor substrate fluted
Interlayer dielectric layer；Dielectric barrier layer is formed on the trenched side-wall；In the dielectric barrier
Upper formation electrically conductive barrier；In the remainder filler metal copper of the groove, described in being formed
Copper interconnection structure.
The manufacture method of copper interconnection structure proposed by the present invention, due to using dielectric barrier layer and leading
Electrical barrier two-layer barrier layer, is so ensureing certain blocking capability, is preventing copper to be diffused into dielectric
On the premise of in layer, can suitably reduce the thickness of electrically conductive barrier again, so that being used for interconnecting
Layers of copper thickness relative increase, and then reduce interconnection resistance, improve device electric property.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description
Suddenly, to explain technical scheme proposed by the present invention.Presently preferred embodiments of the present invention is described in detail
As follows, but in addition to these detailed descriptions, the present invention can also have other embodiment.
Embodiment one
Below with reference to the copper-connection of Fig. 1 and Fig. 2A～Fig. 2 F to an embodiment of the present invention
The manufacture method of structure is described in detail.
First, execution step S101, there is provided Semiconductor substrate, on the semiconductor substrate
Form the fluted interlayer dielectric layer of tool.
As shown in Figure 2 A, there is provided Semiconductor substrate 200, formed on the semiconductor substrate
There is the interlayer dielectric layer 202 of groove 203.
Semiconductor substrate 200 can be at least one in the following material being previously mentioned：Si、Ge、
SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V compound semiconductors,
Also include multiple structure that these quasiconductors are constituted etc. or be silicon-on-insulator (SOI), insulate
It is laminated on body on silicon (SSOI), insulator and is laminated SiGe (S-SiGeOI), germanium on insulator
SiClx (SiGeOI) and germanium on insulator (GeOI) etc..Can be with shape in Semiconductor substrate
Into having device, such as NMOS and/or PMOS etc..Equally, may be used also in the semiconductor substrate
To be formed with isolation structure, the isolation structure is that shallow trench isolates (STI) structure or office
Portion's silicon oxide (LOCOS) isolation structure.Additionally, can also be formed with Semiconductor substrate
Conductive member, conductive member can be grid, source electrode or the drain electrode of transistor, or with
The metal interconnection structure of transistor electrical connection, etc..Additionally, can be with shape in Semiconductor substrate
Into other functions structure sheaf, etching stopping layer etc. can be such as formed.As an example, in this reality
Apply in example, the constituent material of Semiconductor substrate 200 selects monocrystal silicon, in Semiconductor substrate 200
On be formed with conductive member, which is the metal copper layer 201 electrically connected with transistor.
In order to improve the interaction or crosstalk that may occur between copper interconnection structure, and reduce copper
The resistance capacitance (RC) of interconnection structure postpones, and interlayer dielectric layer 202 can be using such as
SiOH or the low K or ultra low-K material of porous SiOH, to reduce interconnection capacitance, reduce
RC retardation ratio, improves electric property.Interlayer dielectric layer 202 can adopt such as PECVD,
The methods such as Spin-On are formed, thickness can be arranged as required to for
The groove 203 formed in interlayer dielectric layer 202 is mainly used in filling out in which through subsequent technique
Fill copper product and form copper interconnection structure.Those skilled in the art can adopt in the art normal
Method forms above-mentioned groove in interlayer dielectric layer, for example, can adopt photoetching work
Skill forms groove 203 in interlayer dielectric layer.As an example, in the present embodiment, groove 203
For dual damascene trench, its bottom is connected with lower metal layers of copper 201.
Then, execution step 102, adsorb one layer of three silicon on the side wall of the groove and bottom
Base nitrogen.
As shown in Figure 2 B, adsorb one layer of three silicon substrate nitrogen on the side wall of groove 203 and bottom
(TSA, (SiH3)3N), specifically, three appropriate silicon substrate nitrogen are passed through into reaction chamber, are flowed
Amount and it is passed through the time and can be determined according to three silicon substrate nitrogen layer thickness to be adsorbed, such as can be with
50sccm～500sccm, pressure are 1Torr～10Torr, are passed through the time for 10～60 seconds, wherein,
Sccm represents cc/min, and Torr represents millimetres of mercury.
Then, execution step 103, process the three silicon substrates nitrogen layer with N2 or NH3, with
The trenched side-wall forms dielectric barrier layer, forms conductive layer in the channel bottom.
As shown in Figure 2 C, the three silicon substrates nitrogen layer 204 is processed with N2 or NH3, with ditch
203 side wall of groove forms dielectric barrier layer 205, forms conductive layer 206 in the channel bottom.
Specifically, specifically, be passed through appropriate N2 or NH3 gases into reaction chamber, flow and
The time of being passed through can be determined according to the thickness of dielectric barrier layer to be formed and conductive layer, such as can be with
100sccm～300sccm, pressure are 1Torr～10Torr, are passed through the time for 30～120 seconds, its
In, sccm represents cc/min, and Torr represents millimetres of mercury.In this embodiment, use
After N2 or NH3 process the three silicon substrates nitrogen layer 204, the two reaction in 203 side wall of groove and
On bottom formed silicon nitride, and bottom formed silicon nitride further with lower-lying metal layers of copper 201
Reaction forms CuSiN, and wherein silicon nitride is used as dielectric barrier layer, and on the one hand which can be used as layer
Between dielectric medium, on the other hand can be used as preventing the metallic copper of follow-up filling to interlayer dielectric layer
The barrier layer of 202 diffusions.The CuSiN formed in 203 bottom of groove has electric conductivity, thus
Metallic copper and the lower metal layers of copper 201 of follow-up filling can be connected, open circuit is prevented.Using this
The silicon nitride that the method for kind is formed has high Step Coverage and diffusion barrier capability, is suitable as being situated between
Electrical barrier.
Then, execution step 104, repeat step 102 and 103 is forming Jie of expectation thickness
Electrical barrier and conductive layer.
As shown in Figure 2 D, repeat step 102 and 103 expects thickness to be formed on trenched side-wall
The dielectric barrier layer 205 of degree, in the conductive layer 206 that channel bottom forms expectation thickness.Wherein
Dielectric barrier layer 205 is silicon nitride, and conductive layer 206 is CuSiN.
Then, execution step 105, form electrically conductive barrier and metal in the remainder of groove
Layers of copper.As shown in Figure 2 E, the remainder in groove 203 forms electrically conductive barrier and metal
Layers of copper 207, wherein electrically conductive barrier can be Ti, TiN, CuMn and CuAl in extremely
Few one kind, to prevent copper metal to interlayer dielectric layer internal diffusion, its can pass through such as PVD,
The conventional process such as CVD, ALD are formed.It is conventional that metal copper layer can pass through electrochemical plating etc.
Method is formed.
Finally, execution step 106, execute planarization, remove the conduction of more than interlayer dielectric layer
Barrier layer and metal copper layer, to form copper interconnection structure in the trench.
As shown in Figure 2 F, planarization is executed, the conductive resistance of interlayer dielectric layer more than 202 is removed
Barrier and metal copper layer 207, to form copper interconnection structure 208 in groove 203.
So far, the processing step that method according to embodiments of the present invention is implemented, Ke Yili are completed
Solution, the present embodiment manufacturing method of semiconductor device not only includes above-mentioned steps, in above-mentioned step
Before rapid, among or may also include other desired step afterwards, such as form coating step,
Which is included in the range of this enforcement manufacture method.
Embodiment two
The present invention also provides a kind of partly leading for method making using described in embodiment one or two
Body device, which includes：Semiconductor substrate 300, forms in the Semiconductor substrate 300
Has fluted interlayer dielectric layer 301, the dielectric resistance sequentially formed on the side wall of the groove
Barrier 302, electrically conductive barrier 303, and fill the layers of copper 304 of the groove remainder.
Wherein, Semiconductor substrate 300 can be at least one in the following material being previously mentioned：
Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V chemical combination
Thing quasiconductor, also includes multiple structure that these quasiconductors are constituted etc. or for silicon-on-insulator
(SOI), stacking silicon (SSOI) on insulator, be laminated on insulator SiGe (S-SiGeOI),
Germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..Quasiconductor is served as a contrast
Device, such as NMOS and/or PMOS etc. is could be formed with bottom.Equally, quasiconductor lining
Can also be formed with conductive member in bottom, conductive member can be the grid of transistor, source electrode or
Drain electrode, or the metal interconnection structure electrically connected with transistor, etc..Additionally, partly
Isolation structure can also be formed with conductor substrate, the isolation structure is isolated for shallow trench
(STI) structure or selective oxidation silicon (LOCOS) isolation structure.As an example.At this
In embodiment, the constituent material of Semiconductor substrate 300 selects monocrystal silicon.
Have fluted interlayer dielectric layer 301 to be formed by method commonly used in the art, such as
The techniques such as CVD, photoetching, dielectric layer barrier layer 301 can select suitable material, for example may be used
Think the nitride of such as silicon nitride, electrically conductive barrier can adopt Ti, TiN, CuMn and
At least one in CuAl.Dielectric barrier layer 302, electrically conductive barrier 303, and layers of copper
304 are formed by a kind of method for illustrating of similar embodiment or method commonly used in the art, and here is not
Repeat again.
Copper interconnection structure for semiconductor device proposed by the present invention, by adopting dielectric barrier
Layer and electrically conductive barrier constitute the composite barrier for preventing copper from spreading, and are so ensureing certain stop
Ability, on the premise of preventing copper to be diffused in dielectric layer, can suitably reduce electrically conductive barrier again
Thickness so that for interconnect layers of copper thickness relative increase, and then reduce interconnection resistance,
Improve the electric property of device.
Embodiment three
In addition the present invention also provides a kind of electronic installation, and which includes aforesaid semiconductor device.
There is semiconductor device due to including higher performance, the electronic installation equally to have upper
State advantage.
The electronic installation, can be mobile phone, panel computer, notebook computer, net book, trip
Gaming machine, television set, VCD, DVD, navigator, photographing unit, video camera, recording pen,
Any electronic product such as MP3, MP4, PSP or equipment, or there is above-mentioned quasiconductor
The intermediate products of device, for example：There is cell phone mainboard of the integrated circuit etc..
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-mentioned
Embodiment is only intended to citing and descriptive purpose, and is not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that the present invention not office
It is limited to above-described embodiment, more kinds of modifications can also be made according to the teachings of the present invention and repaiied
Change, within these variants and modifications all fall within scope of the present invention.The present invention's
Protection domain is defined by the appended claims and its equivalent scope.
Claims (10)
1. a kind of manufacture method of copper interconnection structure, it is characterised in that include：
Semiconductor substrate is provided, forms the fluted interlayer dielectric of tool on the semiconductor substrate
Layer；
Dielectric barrier layer is formed on the trenched side-wall；
Electrically conductive barrier is formed on the dielectric barrier layer；
In the remainder filler metal copper of the groove, to form the copper interconnection structure.
2. manufacture method according to claim 1, it is characterised in that also include：
Conductive layer is formed in the channel bottom, to interconnect with lower metal layer.
3. manufacture method according to claim 1 and 2, it is characterised in that by original
Sublayer deposition process forms the dielectric barrier layer of expectation thickness.
4. manufacture method according to claim 3, it is characterised in that the dielectric resistance
Barrier is formed by following step：
Three silicon substrate N2 adsorption layers are formed on the trenched side-wall；
The three silicon substrates N2 adsorption layer is processed with nitrogen or ammonia, with shape on the trenched side-wall
Into silicon nitride layer；
Repeat the above steps, form the silicon nitride layer of expectation thickness on the trenched side-wall, with
It is used as the dielectric barrier layer.
5. manufacture method according to claim 2, it is characterised in that the conductive layer
Formed by following step：
Adsorb three silicon substrate N2 adsorption layers on the channel bottom；
The three silicon substrates N2 adsorption layer is processed with nitrogen or ammonia, with shape on the channel bottom
Into CuSiN layers；
Repeat the above steps, form the CuSiN layers of expectation thickness on the channel bottom,
For use as the conductive layer.
6. a kind of copper interconnection structure for semiconductor device, it is characterised in that include：Partly lead
Body substrate, the fluted interlayer dielectric layer of the tool for being formed on the semiconductor substrate, described
The dielectric barrier layer sequentially formed on trenched side-wall and electrically conductive barrier, and fill the groove
The layers of copper of remainder.
7. copper interconnection structure according to claim 6, it is characterised in that also include position
In the conductive layer of the channel bottom, for interconnecting with lower metal layer.
8. the copper interconnection structure according to claim 6 or 7, it is characterised in that described
Dielectric barrier layer is nitride.
9. copper interconnection structure according to claim 7, it is characterised in that the conduction
Layer is CuSiN.
10. a kind of electronic installation, it is characterised in that include as described in one of claim 6-9
Copper interconnection structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201510563368.3A CN106505031B (en) | 2015-09-07 | 2015-09-07 | Manufacturing method of copper interconnection structure, copper interconnection structure and electronic device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510563368.3A CN106505031B (en) | 2015-09-07 | 2015-09-07 | Manufacturing method of copper interconnection structure, copper interconnection structure and electronic device |
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| Publication Number | Publication Date |
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| CN106505031A true CN106505031A (en) | 2017-03-15 |
| CN106505031B CN106505031B (en) | 2019-12-31 |
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