CN105489556B

CN105489556B - Semiconductor device, manufacturing method thereof and electronic device

Info

Publication number: CN105489556B
Application number: CN201410537884.4A
Authority: CN
Inventors: 徐建华
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2014-10-13
Filing date: 2014-10-13
Publication date: 2020-03-10
Anticipated expiration: 2034-10-13
Also published as: CN105489556A

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and an electronic device, wherein the method comprises the following steps: providing a semiconductor substrate, wherein a grid groove is formed on the semiconductor substrate, and an etching stop layer is formed in the grid groove; and sequentially forming a bonding layer, a work function layer, a diffusion barrier layer and a conductive layer on the etching stop layer. According to the manufacturing method of the semiconductor device provided by the invention, the adhesive layer is formed between the etching stop layer and the work function layer of the metal gate. The adhesive layer can enhance the adhesion between the etch stop layer and the work function layer, avoid the peeling problem at the interface between the two layers, and thus can improve the performance of the semiconductor device.

Description

Semiconductor device, manufacturing method thereof and electronic device

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof and an electronic device.

Background

As the integration density of semiconductor integrated circuits is continuously increased, the feature size of CMOS devices is smaller and smaller. As gate dimensions shrink to tens of nanometers, high-k/metal gate processes are increasingly replacing the polysilicon/SiO 2 process and becoming mainstream in the industry. The metal gate typically includes a work function layer. Currently, in an NMOS device, TiAl is generally selected as a material of a work function layer thereof. Processes prior to the 28nm technology node typically employ a Physical Vapor Deposition (PVD) process to form the TiAl film. But as technology nodes evolve to 20nm and below, the aspect ratio of the gate trench is getting larger and larger. To achieve better gap fill, processes at 20nm and below technology nodes employ Atomic Layer Deposition (ALD) processes to form TiAl films. The process of forming TiAl by adopting ALD is a low-temperature process, and the process temperature is 80-150 ℃. The quality of the TiAl film formed in this way is not as good as that of the TiAl film formed by PVD, so that the problem of peeling (peeling) exists on TiN/TiAl interfaces and TaN/TiAl interfaces. Some approaches use high temperature NMOS work function metals instead of low temperature TiAl, but high temperature NMOS work function metals also have some side effects, such as having higher resistance, higher threshold voltage (Vt), and the like.

Disclosure of Invention

In view of the shortcomings of the prior art, the invention provides a method for manufacturing a semiconductor device, which comprises the following steps: providing a semiconductor substrate, wherein a grid groove is formed on the semiconductor substrate, and an etching stop layer is formed in the grid groove; and sequentially forming a bonding layer, a work function layer, a diffusion barrier layer and a conductive layer on the etching stop layer.

Optionally, the material of the work function layer is TiAl.

Optionally, the material of the adhesion layer is Ti.

Optionally, the material of the etch stop layer is TiN or TaN.

Optionally, the work function layer is formed using an ALD process.

Optionally, the adhesion layer is formed using a Chemical Vapor Deposition (CVD) process at a temperature of 450-550 ℃.

Optionally, the adhesive layer has a thickness of about 10 angstroms.

Optionally, a high-k dielectric layer is formed below the etch stop layer.

Optionally, an interfacial layer is formed below the high-k dielectric layer.

According to another aspect of the present invention, there is provided a semiconductor device manufactured according to the above method.

According to a further aspect of the present invention, there is provided an electronic device comprising the semiconductor device manufactured according to the above method.

According to the manufacturing method of the semiconductor device provided by the invention, the adhesive layer is formed between the etching stop layer and the work function layer of the metal gate. The adhesive layer can enhance the adhesion between the etch stop layer and the work function layer, avoid the peeling problem at the interface between the two layers, and thus can improve the performance of the semiconductor device.

In order to make the objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:

fig. 1a and 1b show schematic cross-sectional views of a semiconductor device obtained in key steps of a method of manufacturing a semiconductor device according to an embodiment of the invention; and

fig. 2 shows a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

In order to thoroughly understand the present invention, detailed steps will be set forth in the following description in order to explain a method of manufacturing a semiconductor device according to the present invention. It will be apparent that the invention may be practiced without limitation to specific details that are within the skill of one of ordinary skill in the semiconductor arts. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present.

Example one

Next, the detailed steps of the method for manufacturing a semiconductor device proposed by the present invention are described with reference to fig. 1a and 1b and fig. 2. Fig. 1a and 1b show schematic cross-sectional views of a semiconductor device obtained in key steps of a method of manufacturing a semiconductor device according to an embodiment of the invention.

First, referring to fig. 1a, a semiconductor substrate 101 is provided, a gate trench 102 is formed on the semiconductor substrate 101, and an etch stop layer 103 is formed in the gate trench 102. The constituent material of the semiconductor substrate 101 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. Alternatively, an isolation trench, a buried layer, and various well structures may be formed in the semiconductor substrate 101, and are omitted in the drawings for simplicity.

The gate trench 102 is formed by etching a dummy gate layer. The dummy gate layer includes, but is not limited to, silicon, polysilicon, doped polysilicon and polysilicon-germanium alloy materials (i.e., having a doping concentration of from about 1 x 1018 to about 1 x 1022 dopant atoms per cubic centimeter) and polysilicon metal silicide (polycide) materials (doped polysilicon/metal silicide stack materials). The formation and etching processes of the dummy gate layer are known in the art and will not be described herein.

Optionally, sidewalls 104 are formed on two sides of the gate trench 102. The material of the sidewall spacers 104 is, for example, an insulating material such as silicon nitride, silicon oxide, or silicon oxynitride. The sidewall spacers 104 are formed by a process such as CVD, ALD, etc. On both sides of the sidewall spacers 104 are interlayer dielectric layers 105. The interlayer dielectric layer 105 may be a silicon oxide layer, including a doped or undoped silicon oxide layer formed by a thermal chemical vapor deposition (thermal CVD) process or a High Density Plasma (HDP) process, such as Undoped Silicate Glass (USG), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric layer 105 may also be spin-on-glass (SOG) doped with boron or phosphorus, tetraethoxysilane (PTEOS) doped with phosphorus, or tetraethoxysilane (BTEOS) doped with boron.

In one embodiment, a high-k dielectric layer 107 is formed below the etch stop layer 103. The material of high-K dielectric layer 107 includes hafnium oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, and the like. Particularly preferred are hafnium oxide, zirconium oxide and aluminum oxide. Optionally, an interface layer 106 may also be formed below the high-k dielectric layer 107. The interface layer 106 is, for example, an oxide layer.

Optionally, a capping layer 108 may also be formed between the etch stop layer 103 and the high-K dielectric layer 107 to cover the high-K dielectric layer 107. In one embodiment, the capping layer 108 is a TiN layer. The capping layer 108 may be deposited by CVD, such as Low Temperature CVD (LTCVD), Low Pressure CVD (LPCVD), rapid thermal CVD (LTCVD), plasma CVD (PECVD), and the like.

The etch stop layer 103 may comprise any of several etch stop materials including, but not limited to, TiN, TaN, and the like.

Next, referring to fig. 1b, an adhesion layer 109, a work function layer 110, a diffusion barrier layer 111, and a conductive layer 112 are sequentially formed on the etch stop layer 103.

In one embodiment, the semiconductor device is an NMOS transistor. The material of the work function layer 110 may be TiAl. The material of the adhesion layer 109 may be Ti metal. The Ti metal adhesion layer may greatly enhance the adhesion between the TiAl work function layer formed using the ALD process and the etch stop layer 103. Therefore, the problem of falling off can be avoided.

In one embodiment, the adhesion layer 109 may be formed using a CVD process. The CVD process may be high temperature CVD, with process temperatures of, for example, 450 ℃ to 550 ℃. The formation of the Ti metal adhesion layer using a CVD process is a conformal deposition process with good step coverage. The adhesion layer 109 is relatively thin, for example, in one embodiment, about 10 angstroms thick. The thickness of the adhesive layer 109 may be adjusted as necessary.

In one embodiment, the work function layer 110 may be formed using an ALD process. For example, the TiAl work function layer is formed using an ALD process. The ratio between the Ti metal and the Al metal can be adjusted by adjusting the flow ratio of the precursor during deposition. Mixing Al: the Ti ratio is adjusted to be relatively high so that the Al content is more than the Ti content, thereby being able to compensate the effect of the Ti metal adhesion layer on the work function and Vt of the whole. Thereby ensuring that the double-layer stacked structure consisting of the bonding layer and the work function layer has the work function and Vt performance which are equivalent to that of a single ALD TiAl film as a whole. Bilayer stack structures (e.g., CVD Ti + ALD TiAl) have better gap fill capability than PVD TiAl films alone, and better adhesion performance than ALD TiAl alone.

Alternatively, the diffusion barrier layer 111 may be a silicon-containing layer, a carbon-containing layer, a nitrogen-containing layer, a hydrogen-containing layer, or a metal or metal compound layer. The material of the metal or metal compound layer is, for example, tantalum nitride, titanium nitride, zirconium nitride, titanium zirconium nitride, tungsten nitride, an alloy thereof, or a composition thereof. In one embodiment, the diffusion barrier 111 is TiN. The diffusion barrier layer 111 is formed by a process such as PVD, ALD, spin-on deposition or other suitable methods. The diffusion barrier layer 111 may be formed at a temperature between-40 ℃ and 400 ℃ and a pressure between about 0.1 mTorr and 100 mTorr. In addition, the diffusion barrier layer 111 may also include a plurality of layers.

The material of the conductive layer 112 is not particularly limited, and a conductive material and a metal compound having one or more selected from Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W, and Al may be used. In one embodiment, W metal is used as the conductive material of the conductive layer 112, and the W metal can be deposited by CVD or PVD.

Fig. 2 shows a flow chart of a method 200 of manufacturing a semiconductor device according to an embodiment of the invention. The method 200 comprises the following steps:

step S201: providing a semiconductor substrate, forming a gate trench on the semiconductor substrate, and forming an etching stop layer in the gate trench.

Step S202: and sequentially forming a bonding layer, a work function layer, a diffusion barrier layer and a conductive layer on the etching stop layer.

Example two

The invention also provides a semiconductor device which is manufactured by adopting the method of the embodiment. According to the semiconductor device provided by the invention, the bonding layer is formed between the etching stop layer and the work function layer of the metal gate. The adhesive layer can enhance the adhesion between the etch stop layer and the work function layer, avoid the peeling problem at the interface between the two layers, and thus can improve the performance of the semiconductor device.

EXAMPLE III

The invention also provides an electronic device comprising the semiconductor device. The semiconductor device is the semiconductor device described in the second embodiment, or the semiconductor device obtained by the manufacturing method described in the first embodiment.

The electronic device of this embodiment may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a voice pen, an MP3, an MP4, and a PSP, and may also be any intermediate product including the semiconductor device. The electronic device of the embodiment of the invention has better performance due to the use of the semiconductor device.

The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor substrate, wherein a grid groove is formed on the semiconductor substrate, and an etching stop layer is formed in the grid groove; and

forming a bonding layer, a work function layer, a diffusion barrier layer and a conductive layer on the etching stop layer in sequence;

wherein the adhesion layer is formed using a chemical vapor deposition process to enhance adhesion between the work function layer and the etch stop layer.

2. The method of claim 1, wherein the material of the work function layer is TiAl.

3. The method of claim 2, wherein the material of the adhesion layer is Ti.

4. The method of claim 1, wherein the material of the etch stop layer is TiN or TaN.

5. The method of claim 1, wherein the work function layer is formed using an atomic layer deposition process.

6. The method of claim 1, wherein the chemical vapor deposition process temperature is 450 ℃ to 550 ℃.

7. The method of claim 1, wherein the adhesion layer has a thickness of about 10 angstroms.

8. The method of claim 1, wherein a high-k dielectric layer is formed below the etch stop layer.

9. The method of claim 8, wherein an interfacial layer is formed below the high-k dielectric layer.

10. A semiconductor device manufactured by the method of any one of claims 1 to 9.

11. An electronic device comprising the semiconductor device according to claim 10.