CN106487500A - The method that aes algorithm process is realized using streamline - Google Patents
The method that aes algorithm process is realized using streamline Download PDFInfo
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- CN106487500A CN106487500A CN201710004761.8A CN201710004761A CN106487500A CN 106487500 A CN106487500 A CN 106487500A CN 201710004761 A CN201710004761 A CN 201710004761A CN 106487500 A CN106487500 A CN 106487500A
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- key
- streamline
- deciphering
- delay logic
- aes algorithm
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
- H04L9/0631—Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
Abstract
The invention discloses a kind of realize the method that aes algorithm is processed using streamline, its hardware handles framework includes encryption part, decryption processing part and cipher key spreading part, wherein：Encryption part and decryption processing part shared key widening parts；Increase by a delay logic before the first deciphering turn operation in described decryption processing part；In described cipher key spreading part, cipher key spreading streamline generates Nr+1 encryption round key and uses for cryptographic operation, and increasing Nr+1 deciphering round key of a delay logic generation for decryption oprerations use in cipher key spreading streamlines at different levels, Nr is the conversion wheel number generating needed for round key.Using the present invention, can achieve encryption and the blocked operation of deciphering, do not need during realization to use memorizer, simplify control logic, and can according to chip back end design need the pipeline series of delay logic are flexibly reduced.
Description
Technical field
The present invention relates to the information security treatment technology of chip is and in particular to one kind is realized at aes algorithm using streamline
The method of reason.
Background technology
Aes algorithm is a kind of symmetric block ciphers algorithm, is widely used in information security process field.Realize in prior art
The hardware configuration of aes algorithm is general as shown in figure 1, wherein cipher key spreading part, encryption part and deciphering processing component be all
Using the pipeline design, to ensure that each clock cycle can processing data.Key inputs cipher key spreading part, and input in plain text adds
Close processing component, ciphertext inputs decryption processing part.Encryption components interior pipelined architecture is as shown in Fig. 2 every grade of flowing water
Line is made up of cryptographic operation logical sum trigger, and the wheel state of each wheel operation is stored in trigger, uses for next round.Key
Widening parts are similar with encryption part with deciphering processing component internal pipeline framework.Fig. 4 is aes algorithm flow chart, by
Fig. 4 understands, the round key that decryption oprerations first time InvAddRoundKey is used is exactly last 4 of round key used by cryptographic operation
Word, and the round key that last InvAddRoundKey is used is exactly initial 4 words of round key used by cryptographic operation.Therefore,
For decryption oprerations, need to generate in advance all of word of round key, be stored in key storage component.Then input close again
Literary composition, sequential reads out round key by the order contrary with storing process more simultaneously and delivers to decryption processing part for deciphering use.
In order to avoid the round key of next packet covers the key of current group, the write address of memorizer in prior art
Need to stagger with reading address, which adds the complexity of Read-write Catrol.Due to needing to generate round key needed for deciphering in advance,
Before execution deciphering, ciphertext and key can not be processed in same time input.It is thus impossible to support the friendship of Encrypt and Decrypt operation
For operation.Further, since employing memorizer, needing to insert BIST logic when chip is realized, causing extra face
Long-pending expense.
Content of the invention
For the deficiencies in the prior art, present invention is primarily targeted at：Propose one kind and aes algorithm is realized using streamline
The method processing, can meet encryption and the blocked operation of deciphering simultaneously, and avoid using memorizer, simplify control logic, and
Reduce chip area.
For realizing object defined above, the invention discloses a kind of method that aes algorithm process is realized using streamline, its hardware
Processing framework includes encryption part, decryption processing part and cipher key spreading part, each part all using the pipeline design, often
Level production line is made up of corresponding operating logical sum trigger, specifically：
Encryption part and decryption processing part shared key widening parts；
Increase by a delay logic before the first deciphering turn operation in described decryption processing part；
In described cipher key spreading part, cipher key spreading streamline generates Nr+ 1 encryption round key uses for cryptographic operation, and
Increase by a delay logic in cipher key spreading streamlines at different levels and generate Nr+ 1 deciphering round key uses for decryption oprerations, NrFor generating
Conversion wheel number needed for round key；Wherein, generating first required round key of deciphering does not need to increase delay logic, directly by
Cipher key spreading streamline end obtains.
Preferably, described delay logic comprises multi-stage pipeline.
Preferably, the delay logic of described decryption processing part comprises NrLevel production line.
Preferably, comprise the trigger of corresponding series in the delay logic in each level production line of described cipher key spreading, be used for
The corresponding round key deciphered needed for round of storage.
Preferably, described corresponding series is 2* (Nr- N) -1, N extends round for current key, and 0≤N≤Nr-1.
Preferably, described key with input clear packets or ciphertext block corresponding when, described clear packets with described
Ciphertext block can alternately input, and described encryption part and described decryption processing part export ciphertext block respectively and divide in plain text
Group.
Preferably, the pipeline series of described delay logic can accordingly be reduced as needed.
Compared with prior art, it is an advantage of the current invention that：One kind disclosed by the invention realizes aes algorithm using streamline
The method processing, meets encryption and the blocked operation of deciphering using pipelining delay round key, does not need to use during realization
Memorizer, simplifies control logic, and the pipeline series to delay logic can be needed flexible according to chip back end design
Reduced.
Brief description
Fig. 1 is the hardware handles Organization Chart realizing aes algorithm process in prior art；
Fig. 2 is encryption components interior streamline in the hardware handles framework realize in prior art aes algorithm process
Organization Chart；
Fig. 3 is wheel number and cipher key relation figure；
Fig. 4 is the process chart of aes algorithm；
Fig. 5 is wheel view；
Fig. 6 is byte substitution table；
Fig. 7 is row displacement schematic diagram；
Fig. 8 is that row obscure operating principle figure；
Fig. 9 is reverse row displacement schematic diagram；
Figure 10 is reverse byte substitution table；
Figure 11 is that reverse row obscure operating principle figure；
Figure 12 is a kind of hardware handles framework realizing aes algorithm process using streamline that one embodiment of the invention proposes
Figure；
Figure 13 is decryption processing part Organization Chart in the hardware handles framework that one embodiment of the invention proposes；
Figure 14 is delay logic Organization Chart in the hardware handles framework that one embodiment of the invention proposes；
Figure 15 is cipher key spreading part Organization Chart in the hardware handles framework that one embodiment of the invention proposes.
Specific embodiment
In view of deficiency of the prior art, inventor, through studying for a long period of time and putting into practice in a large number, is proposed the present invention's
Technical scheme.This technical scheme, its implementation process and principle etc. will be further explained as follows.
In order to more clearly illustrate the technical scheme that the embodiment of the present invention is proposed, the realization first to aes algorithm below
Process is introduced and the parameter that Examples hereinafter is related to is defined.
Aes algorithm is a kind of symmetric block ciphers algorithm, and information is considered as this algorithm binary number " 0 " and " 1 " forms
Sequence, information is grouped with 128 (16 bytes), and its key length is 128,192 or 256.We will be grouped and be wrapped
Number containing 32 words is designated as Nb, the number of the word that key is comprised is designated as Nk.For aes algorithm, Nb=4, Nk=4,6 or 8.
Input key generates multiple round key through after excessive round transformation.Each clear packets becomes ciphertext through after excessive round transformation,
Each ciphertext block becomes in plain text through after excessive wheel inverse transformation.The wheel number N of conversionrRelated to key length, its relation such as Fig. 3
Shown.
Fig. 4 is the handling process of aes algorithm, as illustrated, no matter encrypt or decryption oprerations the 1st arrive Nr- 1 round transformation is all
Comprise 4 kinds of operations.The conversion that cryptographic operation comprises is followed successively by：Byte is replaced, row displacement, and row are obscured and InvAddRoundKey.Deciphering behaviour
The conversion making to comprise is followed successively by：Reversely row displacement, reverse byte is replaced, InvAddRoundKey and reverse row are obscured.Last round transformation
(i.e. NrRound transformation) all only have 3 kinds of operations, encryption does not have row to obscure operation, and deciphering does not reversely arrange obscures operation.Conversion life
The intermediate result becoming referred to as takes turns state, can be expressed as array of bytes S of as shown in Figure 54 × 4i,j(0<i<4,0<j<4), take turns
State can also regard the sequence of 4 words as.
The ciphertext of the plaintext of cryptographic operation input and decryption oprerations input, before entering line translation, is required for carrying out round key
Add operation.Additionally, wheel state is required for carrying out InvAddRoundKey operation with round key in every round transformation.The round key altogether needing is
4*(Nr+ 1) individual word.Required round key converts generation by inputting key through cipher key spreading, because the length of information block is 4
Word, therefore InvAddRoundKey needs the key of 4 words every time, is designated as array w [0,4*n+3] by word composition, and n is current round,
I.e. n=0,1 ... ..., Nr-1, Nr.
Byte replacement operation is replaced by byte to the wheel state of encryption, replaces according to the word for form as shown in Figure 6
Section substitution table.Row shifting function carries out byte shift to wheel state by row, as shown in fig. 7, not converting from upper number the 1st is capable.2nd
1 byte of row ring shift left, the 3rd row ring shift left 2 byte, the 4th row ring shift left 3 byte.
Row are obscured operation and are carried out finite field gf (2 to wheel state by row8) on matrix multiplication, as shown in figure 8, symbol
Represent the addition on finite field, the addition of two bytes is equivalent to two byte step-by-steps and carries out logic XOR, and symbol " " represents
Multiplication on finite field.One byte can be expressed as：{ b7, b6, b5, b4, b3, b2, b1, b0 }, wherein bi(0≤i≤7) are
The value of each.Byte and multiplication { 02 } S of constant " 02 "0,cCan be equivalent to S0,cMove to left 1, if b7 is equal to 1, will
Value after moving to left executes step-by-step logic xor operation with { 00011011 }.The multiplication of byte and constant " 03 " can decompose such as
Under：
The operation of other bytes is by that analogy.
Reversely row displacement carries out byte shift operation to the wheel state of deciphering by row, is the inverse operation of row displacement.As Fig. 9 institute
Show, do not convert from upper number the 1st is capable.2nd row ring shift right 1 byte, the 3rd row ring shift right 2 byte, the 4th row circulation is right
Move 3 bytes.The wheel state that reversely byte is replaced to deciphering is reversely replaced in units of byte, is the inverse behaviour that byte is replaced
Make, the replacement sheet form of its byte is as shown in Figure 10.
Reversely arrange to obscure and wheel state operated by row, its principle is as shown in figure 11, wherein, byte and constant " 0e "
Multiplication decomposable asymmetric choice net is as follows：
Other multiplication can make similar decomposition.
It is the processing procedure realizing aes algorithm above, for the performance of information processing, and reduce the wind of chip back-end realization
Danger, the method realizing typically adopting streamline of aes algorithm in information security process chip.According to the needs of back end design, often
One level production line realizes the operation of several round transformations.For sake of convenience, the embodiment of the present invention realizes a wheel change with each level production line
It is changed to example to illustrate, those skilled in the art should draw the overall technical architecture of the embodiment of the present invention based on this.
In order that the objects, technical solutions and advantages of the present invention become more apparent, below in conjunction with drawings and Examples, right
The present invention is further elaborated.It should be appreciated that specific embodiment described herein is only in order to explain the present invention, not
For limiting the present invention.
Figure 12 is a kind of hardware handles framework realizing aes algorithm process using streamline that one embodiment of the invention proposes
Figure, as shown in figure 12, described framework includes encryption part, decryption processing part and cipher key spreading part, and each part is still
All using the pipeline design, every level production line is made up of corresponding operating logical sum trigger, encryption part and decryption processing
Part shared key widening parts.Wherein：
Encryption part is identical with the encryption part in Fig. 1, and every level production line is triggered by cryptographic operation logical sum
Device forms, and the wheel state of each wheel operation is stored in trigger, uses for next round, inside structure is as shown in Figure 2；
Decryption processing part framework is as shown in figure 13, in order to ensure ciphertext and deciphering round key 0 in the same clock cycle
Effectively, increased delay logic before execution decryption oprerations round 0, for being postponed ciphertext.Comprise in delay logic
NrLevel production line, its framework is as shown in figure 14.
Cipher key spreading part is respectively encryption part and deciphering processing component provides key, its framework such as Figure 15 institute
Show, the N altogether that cipher key spreading streamline generatesr+ 1 round key uses for cryptographic operation, and such as in figure is marked as encryption key.
The feature of round key used by decryption oprerations according to Fig. 4, the wheel that decryption oprerations first time InvAddRoundKey is used
Key is exactly last 4 word w [4*N of round key used by cryptographic operationr,4*Nr+ 3] InvAddRoundKey is used, and for the last time
Round key be exactly round key used by cryptographic operation initial 4 word w [0,3].Therefore, in embodiments of the present invention, key
Widening parts increased delay logic to provide Nr+ 1 deciphering round key, is designated as w [0,4*N by wordr+ 3], as in figure is labeled
For decruption key.
The framework of the delay logic in cipher key spreading part is similar with the delay logic in decryption processing part.Deciphering is required
The 0th round key need not postpone, directly by cipher key spreading streamline end obtain.Principle according to Fig. 4, in Figure 15, key expands
1 grade of trigger is comprised, for storing round key w [4* (N in the delay logic 1501 of exhibition round Nr-1r-1),4*Nr- 1], provide
Decipher key needed for the 1st wheel；Cipher key spreading round Nr3 grades of triggers are comprised in -2 delay logic 1502, close for storage wheel
Key w [4* (Nr-2),4*Nr- 5], key needed for deciphering the 2nd wheel is provided；By that analogy, the delay logic in cipher key spreading round n
Comprise 2 (Nr- n) -1 grade of trigger, for storing round key w [4*n, 4*n+3], 0≤n≤Nr- 1, that is,：Delay logic 1503 wraps
Containing 2*Nr- 3 grades of triggers, for storing round key w [4,7], provide deciphering NrKey needed for -1 wheel；Delay logic 1504 wraps
Containing 2*Nr- 1 grade of trigger, for storing round key w [0,3], provides deciphering NrKey needed for wheel.
Using the hardware handles framework described in the embodiment of the present invention, clear packets and key are simultaneously entered, through NrWhen individual
After the clock cycle, ciphertext block exports from encryption part；Ciphertext block and key are simultaneously entered, through 2*NrIndividual clock week
After phase, clear packets export from decryption processing part.As long as key is corresponding with input clear packets or ciphertext block, bright
Literary composition packet and ciphertext block can alternately input, through different delays, can be respectively in encryption part and decryption processing
Part obtains ciphertext block and clear packets.
Further, the needs according to chip back end design, the pipeline series of each delay logic can also accordingly be cut out
Subtract, for example, adjacent several rounds are merged into 1 level production line, thus reducing the quantity of trigger, to save area.
Can become apparent from learning by above-described embodiment, one kind that the embodiment of the present invention proposes realizes AES using streamline
The method of algorithm process, by pipelining delay round key, can achieve encryption and the blocked operation of deciphering；Avoid in processing framework
Using memorizer, thus simplifying control logic, reduce chip area simultaneously；And, the pipeline series of delay logic can
Flexibly to be reduced according to the needs of chip back end design.
It should be appreciated that above-described embodiment technology design only to illustrate the invention and feature, its object is to allow and be familiar with this
The personage of item technology will appreciate that present disclosure and implements according to this, can not be limited the scope of the invention with this.All
The equivalence changes made according to spirit of the invention or modification, all should be included within the scope of the present invention.
Claims (7)
1. a kind of method realizing aes algorithm process using streamline, its hardware handles framework includes encryption part, deciphering
Processing component and cipher key spreading part, all using the pipeline design, every level production line is triggered each part by corresponding operating logical sum
Device composition it is characterised in that：
Encryption part and decryption processing part shared key widening parts；
Increase by a delay logic before the first deciphering turn operation in described decryption processing part；
In described cipher key spreading part, cipher key spreading streamline generates Nr+ 1 encryption round key uses for cryptographic operation, and each
Level cipher key spreading streamline increases by a delay logic and generates Nr+ 1 deciphering round key uses for decryption oprerations, NrClose for generating wheel
Conversion wheel number needed for key；Wherein, generating first required round key of deciphering does not need to increase delay logic, directly by key
Extension streamline end obtains.
2. according to claim 1 using streamline realize aes algorithm process method it is characterised in that：Described delay
Logic comprises multi-stage pipeline.
3. according to claim 2 using streamline realize aes algorithm process method it is characterised in that：Described deciphering
The delay logic of processing component comprises NrLevel production line.
4. according to claim 2 using streamline realize aes algorithm process method it is characterised in that：Described key
Extend the trigger comprising corresponding series in the delay logic in each level production line, for storing the wheel needed for corresponding deciphering round
Key.
5. according to claim 4 using streamline realize aes algorithm process method it is characterised in that：Described corresponding
Series is 2* (Nr- N) -1, N extends round for current key, and 0≤N≤Nr-1.
6. the method realizing aes algorithm process using streamline according to Claims 1 to 5 any one, its feature exists
In：When described key is corresponding with input clear packets or ciphertext block, described clear packets can be handed over described ciphertext block
For input, described encryption part and described decryption processing part export ciphertext block and clear packets respectively.
7. the method realizing aes algorithm process using streamline according to Claims 1 to 5 any one, its feature exists
In：The pipeline series of described delay logic can accordingly be reduced as needed.
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| CN110311771A (en) * | 2018-03-20 | 2019-10-08 | 北京松果电子有限公司 | SM4 encipher-decipher method and circuit |
| CN110336658A (en) * | 2019-07-01 | 2019-10-15 | 武汉能钠智能装备技术股份有限公司 | Encryption method, user equipment, storage medium and device based on aes algorithm |
| CN113078996A (en) * | 2021-02-25 | 2021-07-06 | 西安电子科技大学 | FPGA (field programmable Gate array) optimization realization method, system and application of SM4 cryptographic algorithm |
| CN113193950A (en) * | 2021-07-01 | 2021-07-30 | 广东省新一代通信与网络创新研究院 | Data encryption method, data decryption method and storage medium |
| CN114553538A (en) * | 2022-02-22 | 2022-05-27 | 国网山东省电力公司电力科学研究院 | Active protection method and system for power grid information safety |
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| CN110311771A (en) * | 2018-03-20 | 2019-10-08 | 北京松果电子有限公司 | SM4 encipher-decipher method and circuit |
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| CN114553538A (en) * | 2022-02-22 | 2022-05-27 | 国网山东省电力公司电力科学研究院 | Active protection method and system for power grid information safety |
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Application publication date: 20170308 |