CN106487467B - Time synchronization deviation detection method and device - Google Patents
Time synchronization deviation detection method and device Download PDFInfo
- Publication number
- CN106487467B CN106487467B CN201510532505.7A CN201510532505A CN106487467B CN 106487467 B CN106487467 B CN 106487467B CN 201510532505 A CN201510532505 A CN 201510532505A CN 106487467 B CN106487467 B CN 106487467B
- Authority
- CN
- China
- Prior art keywords
- time
- deviation
- timestamp data
- nodes
- frequency deviation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Electric Clocks (AREA)
Abstract
The invention discloses a time synchronization deviation detection method, which comprises the following steps: receiving a detection instruction of frequency deviation and time deviation; according to the detection instruction, timestamp data of detection messages between nodes is acquired within preset time; and calculating the frequency deviation and the time deviation between the nodes through a preset algorithm according to the timestamp data. The invention also discloses a time synchronization deviation detection device. The invention realizes that the frequency deviation and the time deviation between the nodes can be effectively detected under the condition that the input reference frequency is larger or the crystal oscillator is aged and the clock source can not be locked.
Description
Technical Field
The present invention relates to the field of network management, and in particular, to a method and an apparatus for detecting a time synchronization deviation.
Background
In recent years, as mobile communication technology is continuously developed, a 1588V 2-based time synchronization network has been widely applied to global mobile operators. 1588V2 is a synchronization technology standard based on packet transmission, which uses a timestamp mechanism and a master-slave clock (master-slave) scheme to encode and transmit time, and uses the symmetry and delay measurement technology of network links to synchronize the frequency and time of the master-slave clocks.
The real-time detection of the time synchronization condition of the whole network of the packet network and the internal clock time performance of each node has become an urgent need of operators. The frequency deviation performance and the time deviation performance of the slave clock node relative to the master clock node are one of the most important detection indexes for the whole network time synchronization condition of the packet network. At present, most of methods for recovering 1588V2 frequency or estimating frequency deviation adopt a least square method estimation model, and frequency or frequency deviation is obtained after least square regression fitting. This method is common, but complex to implement. And under the condition that the input reference frequency is large or the crystal oscillator is aged and the clock source cannot be locked, the least square method estimation model can be failed in detection.
The above is only for the purpose of assisting understanding of the technical aspects of the present invention, and does not represent an admission that the above is prior art.
Disclosure of Invention
The invention mainly aims to provide a time synchronization deviation detection method and a time synchronization deviation detection device, and aims to solve the technical problem that the frequency deviation and the time deviation between nodes are failed to detect under the condition that the input reference frequency is too large or a crystal oscillator is aged and a clock source cannot be locked.
In order to achieve the above object, the present invention provides a method for detecting a time synchronization deviation, comprising:
receiving a detection instruction of frequency deviation and time deviation;
according to the detection instruction, timestamp data of detection messages between nodes is acquired within preset time;
and calculating the frequency deviation and the time deviation between the nodes through a preset algorithm according to the timestamp data.
Preferably, before the step of receiving the detection instruction of the frequency deviation and the time deviation, the method further includes:
setting a maximum threshold value and a minimum threshold value corresponding to the frequency deviation and the time deviation;
after the step of calculating the frequency deviation and the time deviation between the nodes by a preset algorithm according to the timestamp data, the method further comprises the following steps:
and when the frequency deviation and/or the time deviation are larger than the corresponding maximum threshold value or smaller than the corresponding minimum threshold value, outputting alarm information.
Preferably, after the step of obtaining timestamp data of the detection packet between the nodes within a preset time according to the detection instruction, the method further includes:
storing the timestamp data;
after the step of calculating the frequency deviation and the time deviation between the nodes by a preset algorithm according to the timestamp data, the method further comprises the following steps:
deleting the timestamp data and storing new timestamp data;
and calculating the frequency deviation and the time deviation between the nodes by a preset algorithm according to the new timestamp data.
Preferably, the step of deleting the time stamp data and storing new time stamp data comprises:
acquiring a current time T1 and a time T2 at which the timestamp data is stored;
when the difference of the current time T1 minus the time T2 is greater than the preset time, the time stamp data is deleted and new time stamp data is stored.
Preferably, the step of calculating the frequency deviation and the time deviation between the nodes by a preset algorithm according to the timestamp data includes:
calculating to obtain a phase sum corresponding to the timestamp data according to the timestamp data;
calculating to obtain the frequency deviation between the nodes through a frequency deviation formula according to the phase sum;
calculating to obtain a first time deviation according to the timestamp data;
and correcting the clock of the detection message according to the first time deviation, and comparing the clock with the clock of the non-detection message to obtain a second time deviation, wherein the second time deviation is the time deviation between the nodes.
In order to achieve the above object, the present invention also provides a time synchronization deviation detecting device, including:
the receiving module is used for receiving a detection instruction of the frequency deviation and the time deviation;
the acquisition module is used for acquiring timestamp data of detection messages between nodes within preset time according to the detection instruction;
and the calculation module is used for calculating the frequency deviation and the time deviation between the nodes through a preset algorithm according to the timestamp data.
Preferably, the time synchronization deviation detecting device further includes:
a setting module, configured to set a maximum threshold value and a minimum threshold value corresponding to the frequency deviation and the time deviation;
and the output module is used for outputting alarm information when the frequency deviation and/or the time deviation is greater than a corresponding maximum threshold value or less than a corresponding minimum threshold value.
Preferably, the time synchronization deviation detecting device further includes:
the storage module is used for storing the timestamp data;
the deleting module is used for deleting the timestamp data and storing new timestamp data;
and the calculating module is also used for calculating the frequency deviation and the time deviation between the nodes through a preset algorithm according to the new timestamp data.
Preferably, the deletion module includes:
an acquisition unit for acquiring a current time T1 and a time T2 at which the time stamp data is stored;
and the deleting unit is used for deleting the timestamp data and storing new timestamp data when the difference of the current time T1 minus the time T2 is greater than the preset time.
Preferably, the calculation module comprises:
the first calculation unit is used for calculating a phase sum corresponding to the timestamp data according to the timestamp data;
the second calculation unit is used for calculating and obtaining the frequency deviation between the nodes through a frequency deviation formula according to the phase sum;
the third calculating unit is used for calculating to obtain a first time deviation according to the timestamp data;
and the correcting unit is used for correcting the clock of the detection message according to the first time deviation and comparing the clock with the clock of the non-detection message to obtain a second time deviation, wherein the second time deviation is the time deviation between the nodes.
According to the invention, when a detection instruction of frequency deviation and time deviation is received, timestamp data of a detection message is obtained, and the frequency deviation and the time deviation between nodes are calculated through a preset algorithm according to the timestamp data. The method and the device can effectively detect the frequency deviation and the time deviation between the nodes under the condition that the input reference frequency is larger or the crystal oscillator is aged and the clock source cannot be locked.
Drawings
FIG. 1 is a schematic flow chart illustrating a method for detecting a time synchronization deviation according to a first embodiment of the present invention;
FIG. 2 is a flowchart illustrating a time synchronization deviation detecting method according to a second embodiment of the present invention;
FIG. 3 is a flowchart illustrating a method for detecting a time synchronization deviation according to a third embodiment of the present invention;
FIG. 4 is a functional block diagram of a time synchronization deviation detecting apparatus according to a first embodiment of the present invention;
FIG. 5 is a functional block diagram of a time synchronization deviation detecting apparatus according to a second embodiment of the present invention;
fig. 6 is a functional block diagram of a time synchronization deviation detecting apparatus according to a third embodiment of the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The invention provides a time synchronization deviation detection method.
Referring to fig. 1, fig. 1 is a flowchart illustrating a method for detecting a time synchronization deviation according to a first embodiment of the present invention.
In this embodiment, the method for detecting the time synchronization deviation includes:
step S10, receiving a detection instruction of frequency deviation and time deviation;
step S20, according to the detection instruction, obtaining the timestamp data of the detection message between the nodes in the preset time;
the device where the slave clock node is located communicates with the device where the master clock node is located through an IEEE (institute of Electrical and Electronics Engineers) 1588V2 protocol. Namely, the slave clock node device and the master clock node device communicate through an IEEE 1588V2 protocol. The IEEE 1588V2 is used as a master-slave Synchronization system, in the Synchronization process of the system, a master clock (master clock) periodically issues a Precision Time Synchronization Protocol (PTP) and Time information, a slave clock port (slave clock node) receives timestamp data sent by the master clock port (master clock node), the system calculates master-slave line Time delay and master-slave Time difference according to the timestamp data, and adjusts local Time by using the Time difference, so that the Time of a slave device (slave clock node device) maintains the frequency and phase consistent with the Time of the master device (master clock node device).
And the slave clock node equipment sends a detection message and a 1588V2 message to the master clock node equipment through the slave clock node. The detection message and the 1588V2 message process corresponding timestamp data through different time counters, preferably, the different time counters use the same clock, the detection message is also a 1588V2 message, and the detection message and the 1588V2 message are transmitted between the sample clock node device and the master clock node device through different communication channels. The message of the 1588V2 message may be divided into an event message and a common message, where the event message includes a Sync message, a Delay _ Req message, a Pdelay _ Req message, and a Pdelay _ Resp message; the normal messages include announce message, Follow _ Up message, Delay _ Resp message, Pdelay _ Resp _ Follow _ Up message, Management message, Signaling message.
When the slave clock node equipment receives a detection instruction of starting frequency deviation and time deviation sent by a server, starting a first timer and a second timer, and acquiring timestamp data of a detection message between the slave clock node and the master clock node within preset time. The detection instruction comprises an enabling identification of the detection message, the reporting period of the frequency deviation and the time deviation and the like. Preferably, the unit of the preset time is seconds, for example, set to 60 seconds, the slave clock node device acquires a first group of timestamp data and a last group of timestamp data within 60 seconds, records the first group of timestamp data as T1, T2, T3 and T4, and records the last group of timestamp data as T1', T2', T3', and T4'. If a set of timestamp data includes the time T1 when the master clock node device sends the Sync message, the time T2 when the slave clock node device receives the Sync message, the time T3 when the slave clock node device sends the Delay _ Req message to the master clock node device after receiving the Sync message, and the time T4 when the master clock node device receives the Delay _ Req message.
And step S30, calculating the frequency deviation and the time deviation between the nodes through a preset algorithm according to the timestamp data.
And the slave clock node equipment calculates the frequency deviation and the time deviation of the slave clock node relative to the master clock node through a preset algorithm according to the timestamp data. Preferably, the slave clock node device calculates, by using a first timer, a phase sum corresponding to the timestamp data according to the timestamp data, and calculates, by using a frequency deviation formula, a frequency deviation of the slave clock node relative to the master clock node according to the phase sum. The specific process of calculating the frequency deviation of the slave clock node relative to the master clock node by the slave clock node device is as follows: the slave clock node device obtains offset1 ═ [ (T1-T2) + (T3-T4) ]/2 from the first set of timestamp data, obtains offset2 [ (T1'-T2') + (T3'-T4') ]/2 from the second set of timestamp data, adds the offset1 and the offset2 to obtain a phase sum Theta, that is, the phase sum Time 1+ offset2, and obtains a calculation formula F ═ according to a frequency deviation ((T2'-T1') -Theta- (T2-T1))/Theta after obtaining the phase sum Theta; and calculating the Time (T1' -T1) to obtain the frequency deviation of the slave clock node relative to the master clock node device. The specific process that the slave clock node device calculates the time deviation of the slave clock node relative to the master clock node through the first timer is as follows: the slave clock node device calculates a first time deviation according to the timestamp data through a first timer, wherein the first time deviation is offset1 or offset2, corrects the time counter of the detection packet according to the calculated offset1 and/or offset2, compares the time counter of the detection packet with the time counter of the non-detection packet, namely corrects the clock of the detection packet, compares the clock of the time counter of the detection packet with the clock of the time counter of the 1588V2 packet, calculates a difference value, and obtains the time deviation of the slave clock node relative to the master clock node.
In the embodiment, when a detection instruction of frequency deviation and time deviation is received, timestamp data of a detection message is acquired, and according to the timestamp data, the frequency deviation and the time deviation between nodes are calculated through a preset algorithm. The method and the device can effectively detect the frequency deviation and the time deviation between two nodes under the condition that the input reference frequency is larger or the crystal oscillator is aged and the clock source cannot be locked. In addition, in the process of calculating the frequency deviation and the time deviation between the two nodes, the physical characteristics of equipment where the two nodes are located do not need to be changed, and the calculation cost is reduced.
Referring to fig. 2, fig. 2 is a flowchart illustrating a time synchronization deviation detecting method according to a second embodiment of the present invention, and the time synchronization deviation detecting method according to the second embodiment of the present invention is proposed based on the first embodiment.
In this embodiment, before step S10, the method further includes:
step S40, setting a maximum threshold value and a minimum threshold value corresponding to the frequency deviation and the time deviation;
the slave clock node equipment sets a maximum threshold value and a minimum threshold value of frequency deviation of the slave clock node relative to a master clock node in the master clock node equipment, sets a maximum threshold value and a minimum threshold value of time deviation of the slave clock node relative to the master clock node, port information and the like, and stores the information.
Further, after the step S30, the method further includes:
and step S50, when the frequency deviation and/or the time deviation is larger than the corresponding maximum threshold value or smaller than the corresponding minimum threshold value, outputting alarm information.
And the slave clock node equipment detects whether the frequency deviation and/or the time deviation are greater than a corresponding maximum threshold value or less than a corresponding minimum threshold value at regular intervals through a second timer. When the slave clock node device detects that the frequency deviation of the detection message is greater than the set maximum threshold value or less than the set minimum threshold value through the second timer, or detects that the time deviation of the detection message is greater than the set maximum threshold value or less than the set minimum threshold value, alarm information is output to prompt a user that the frequency deviation and/or the time deviation of the slave clock node relative to the master clock node are/is in an abnormal range. And when the slave clock node equipment detects that the frequency deviation of the detection message is between the set minimum threshold value and the set maximum threshold value through the second timer, and the time deviation of the detection message is also between the set minimum threshold value and the set maximum threshold value, not outputting alarm information.
Preferably, the slave clock node device detects, by the second timer, whether the frequency deviation and/or the time deviation are greater than a corresponding maximum threshold value or less than a corresponding minimum threshold value every 15 minutes. Within the 15 minutes, the slave clock node device calculates frequency deviations and time deviations of 15 slave clock nodes relative to the master clock node through the first timer, and in the 15 frequency deviations and time deviations, the second timer selects the maximum frequency deviation and the minimum time deviation, and simultaneously selects the frequency deviation and the time deviation calculated at the current time to be compared with the corresponding minimum threshold value and the maximum threshold value set by the frequency deviation and the time deviation. And when the slave clock node equipment detects that the selected frequency deviation and/or time deviation is not between the set corresponding minimum threshold value and the set corresponding maximum threshold value through the second timer, outputting alarm information. The alarm information corresponding to the frequency deviation and the time deviation may be the same or different, for example, when the frequency deviation is not between the minimum threshold and the maximum threshold, a first alarm prompt tone is output; and when the time deviation is not between the minimum threshold value and the maximum threshold value, outputting a second alarm prompt tone. The alarm information includes, but is not limited to, an alarm prompt tone, or flashing of an LED or the like.
In this embodiment, when the frequency deviation and/or the time deviation is greater than the corresponding maximum threshold value or less than the corresponding minimum threshold value, an alarm message is output to prompt a user of a detection result of the frequency deviation and the time deviation between two current nodes, so that the efficiency of fault location between the two nodes is improved, and a decision basis is improved for switching of a clock synchronization path.
Referring to fig. 3, fig. 3 is a flowchart illustrating a time synchronization deviation detecting method according to a third embodiment of the present invention, and the time synchronization deviation detecting method according to the third embodiment of the present invention is proposed based on the first embodiment.
In this embodiment, after step S20, the method further includes:
step S60, storing the time stamp data;
and after the slave clock node equipment acquires the timestamp data of the detection message of the slave clock node relative to the master clock node within the preset time, storing the timestamp data.
Further, after the step S30, the method further includes:
step S70, deleting the time stamp data and storing new time stamp data;
and step S80, calculating the frequency deviation and the time deviation between the nodes through a preset algorithm according to the new timestamp data.
And after the slave clock node equipment obtains the frequency deviation and the time deviation of the slave clock node relative to the master clock node through calculation of a preset algorithm according to the timestamp data, calculating the time for storing the timestamp data through a first timer. The specific algorithm is as follows: the slave clock node equipment acquires the current time T1 and the time T2 for storing the timestamp data through a first timer, subtracts the time T2 from the current time T1, and deletes the timestamp data and stores new timestamp data when the difference between the subtraction of the current time T1 and the subtraction of the time T2 is greater than the preset time. If the difference between the current time T1 minus the time T2 is greater than 60 seconds, the time stamp data is deleted and new time stamp data is stored. After the slave clock node equipment stores new timestamp data, the slave clock node equipment calculates the frequency deviation and the time deviation of the slave clock node relative to the master clock node through a first timer according to the new timestamp data and a preset algorithm.
The present embodiment improves the accuracy of detection of the frequency deviation and the time deviation between two nodes by calculating the frequency deviation and the time deviation between the two nodes a plurality of times based on different time stamp data.
The invention further provides a time synchronization deviation detection device.
Referring to fig. 4, fig. 4 is a functional block diagram of a time synchronization deviation detecting apparatus according to a first embodiment of the present invention.
In this embodiment, the time synchronization deviation detecting apparatus includes:
a receiving module 10, configured to receive a detection instruction of a frequency deviation and a time deviation;
an obtaining module 20, configured to obtain timestamp data of a detection packet between nodes within a preset time according to the detection instruction;
the device where the slave clock node is located communicates with the device where the master clock node is located through an IEEE (institute of Electrical and Electronics Engineers) 1588V2 protocol. Namely, the slave clock node device and the master clock node device communicate through an IEEE 1588V2 protocol. The IEEE 1588V2 is used as a master-slave Synchronization system, in the Synchronization process of the system, a master clock (master clock) periodically issues a Precision Time Synchronization Protocol (PTP) and Time information, a slave clock port (slave clock node) receives timestamp data sent by the master clock port (master clock node), the system calculates master-slave line Time delay and master-slave Time difference according to the timestamp data, and adjusts local Time by using the Time difference, so that the Time of a slave device (slave clock node device) maintains the frequency and phase consistent with the Time of the master device (master clock node device).
And the slave clock node equipment sends a detection message and a 1588V2 message to the master clock node equipment through the slave clock node. The detection message and the 1588V2 message process corresponding timestamp data through different time counters, preferably, the different time counters use the same clock, the detection message is also a 1588V2 message, and the detection message and the 1588V2 message are transmitted between the sample clock node device and the master clock node device through different communication channels. The message of the 1588V2 message may be divided into an event message and a common message, where the event message includes a Sync message, a Delay _ Req message, a Pdelay _ Req message, and a Pdelay _ Resp message; the normal messages include announce message, Follow _ Up message, Delay _ Resp message, Pdelay _ Resp _ Follow _ Up message, Management message, Signaling message.
When the slave clock node equipment receives a detection instruction of starting frequency deviation and time deviation sent by a server, starting a first timer and a second timer, and acquiring timestamp data of a detection message between the slave clock node and the master clock node within preset time. The detection instruction comprises an enabling identification of the detection message, the reporting period of the frequency deviation and the time deviation and the like. Preferably, the unit of the preset time is seconds, for example, set to 60 seconds, the slave clock node device acquires a first group of timestamp data and a last group of timestamp data within 60 seconds, records the first group of timestamp data as T1, T2, T3 and T4, and records the last group of timestamp data as T1', T2', T3', and T4'. If a set of timestamp data includes the time T1 when the master clock node device sends the Sync message, the time T2 when the slave clock node device receives the Sync message, the time T3 when the slave clock node device sends the Delay _ Req message to the master clock node device after receiving the Sync message, and the time T4 when the master clock node device receives the Delay _ Req message.
And the calculating module 30 is configured to calculate, according to the timestamp data, a frequency deviation and a time deviation between the nodes through a preset algorithm.
And the slave clock node equipment calculates the frequency deviation and the time deviation of the slave clock node relative to the master clock node through a preset algorithm according to the timestamp data. Preferably, the slave clock node device calculates, by using a first timer, a phase sum corresponding to the timestamp data according to the timestamp data, and calculates, by using a frequency deviation formula, a frequency deviation of the slave clock node relative to the master clock node according to the phase sum. The specific process of calculating the frequency deviation of the slave clock node relative to the master clock node by the slave clock node device is as follows: the slave clock node device obtains offset1 ═ [ (T1-T2) + (T3-T4) ]/2 from the first set of timestamp data, obtains offset2 [ (T1'-T2') + (T3'-T4') ]/2 from the second set of timestamp data, adds the offset1 and the offset2 to obtain a phase sum Theta, that is, the phase sum Time 1+ offset2, and obtains a calculation formula F ═ according to a frequency deviation ((T2'-T1') -Theta- (T2-T1))/Theta after obtaining the phase sum Theta; and calculating the Time (T1' -T1) to obtain the frequency deviation of the slave clock node relative to the master clock node device. The specific process that the slave clock node device calculates the time deviation of the slave clock node relative to the master clock node through the first timer is as follows: the slave clock node device calculates a first time deviation according to the timestamp data through a first timer, wherein the first time deviation is offset1 or offset2, corrects the time counter of the detection packet according to the calculated offset1 and/or offset2, compares the time counter of the detection packet with the time counter of the non-detection packet, namely corrects the clock of the detection packet, compares the clock of the time counter of the detection packet with the clock of the time counter of the 1588V2 packet, calculates a difference value, and obtains the time deviation of the slave clock node relative to the master clock node device.
In the embodiment, when a detection instruction of frequency deviation and time deviation is received, timestamp data of a detection message is acquired, and according to the timestamp data, the frequency deviation and the time deviation between nodes are calculated through a preset algorithm. The method and the device can effectively detect the frequency deviation and the time deviation between two nodes under the condition that the input reference frequency is larger or the crystal oscillator is aged and the clock source cannot be locked. In addition, in the process of calculating the frequency deviation and the time deviation between the two nodes, the physical characteristics of equipment where the two nodes are located do not need to be changed, and the calculation cost is reduced.
Referring to fig. 5, fig. 5 is a functional block diagram of a time synchronization deviation detecting apparatus according to a second embodiment of the present invention, and the second embodiment of the time synchronization deviation detecting apparatus according to the present invention is proposed based on the first embodiment.
In this embodiment, the time synchronization deviation detecting apparatus further includes:
a setting module 40, configured to set a maximum threshold and a minimum threshold corresponding to the frequency deviation and the time deviation;
the slave clock node equipment sets a maximum threshold value and a minimum threshold value of frequency deviation of the slave clock node relative to a master clock node in the master clock node equipment, sets a maximum threshold value and a minimum threshold value of time deviation of the slave clock node relative to the master clock node, port information and the like, and stores the information.
An output module 50, configured to output alarm information when the frequency deviation and/or the time deviation is greater than a corresponding maximum threshold value or smaller than a corresponding minimum threshold value.
And the slave clock node equipment detects whether the frequency deviation and/or the time deviation are greater than a corresponding maximum threshold value or less than a corresponding minimum threshold value at regular intervals through a second timer. When the slave clock node device detects that the frequency deviation of the detection message is greater than the set maximum threshold value or less than the set minimum threshold value through the second timer, or detects that the time deviation of the detection message is greater than the set maximum threshold value or less than the set minimum threshold value, alarm information is output to prompt a user that the frequency deviation and/or the time deviation of the slave clock node relative to the master clock node are/is in an abnormal range. And when the slave clock node equipment detects that the frequency deviation of the detection message is between the set minimum threshold value and the set maximum threshold value through the second timer, and the time deviation of the detection message is also between the set minimum threshold value and the set maximum threshold value, not outputting alarm information.
Preferably, the slave clock node device detects, by the second timer, whether the frequency deviation and/or the time deviation are greater than a corresponding maximum threshold value or less than a corresponding minimum threshold value every 15 minutes. Within the 15 minutes, the slave clock node device calculates frequency deviations and time deviations of 15 slave clock nodes relative to the master clock node through the first timer, and in the 15 frequency deviations and time deviations, the second timer selects the maximum frequency deviation and the minimum time deviation, and simultaneously selects the frequency deviation and the time deviation calculated at the current time to be compared with the corresponding minimum threshold value and the maximum threshold value set by the frequency deviation and the time deviation. And when the slave clock node equipment detects that the selected frequency deviation and/or time deviation is not between the set corresponding minimum threshold value and the set corresponding maximum threshold value through the second timer, outputting alarm information. The alarm information corresponding to the frequency deviation and the time deviation may be the same or different, for example, when the frequency deviation is not between the minimum threshold and the maximum threshold, a first alarm prompt tone is output; and when the time deviation is not between the minimum threshold value and the maximum threshold value, outputting a second alarm prompt tone. The alarm information includes, but is not limited to, an alarm prompt tone, or flashing of an LED or the like.
In this embodiment, when the frequency deviation and/or the time deviation is greater than the corresponding maximum threshold value or less than the corresponding minimum threshold value, an alarm message is output to prompt a user of a detection result of the frequency deviation and the time deviation between two current nodes, so that the efficiency of fault location between the two nodes is improved, and a decision basis is improved for switching of a clock synchronization path.
Referring to fig. 6, fig. 6 is a functional block diagram of a time synchronization deviation detecting apparatus according to a third embodiment of the present invention, and the third embodiment of the time synchronization deviation detecting apparatus according to the present invention is provided based on the first embodiment.
In this embodiment, the time synchronization deviation detecting apparatus further includes:
a storage module 60 for storing the timestamp data;
and after the slave clock node equipment acquires the timestamp data of the detection message of the slave clock node relative to the master clock node within the preset time, storing the timestamp data.
A deleting module 70, configured to delete the timestamp data and store new timestamp data;
the calculating module 30 is further configured to calculate, according to the new timestamp data, a frequency deviation and a time deviation between the nodes through a preset algorithm.
And after the slave clock node equipment obtains the frequency deviation and the time deviation of the slave clock node relative to the master clock node through calculation of a preset algorithm according to the timestamp data, calculating the time for storing the timestamp data through a first timer. The specific algorithm is as follows: the slave clock node equipment acquires the current time T1 and the time T2 for storing the timestamp data through a first timer, subtracts the time T2 from the current time T1, and deletes the timestamp data and stores new timestamp data when the difference between the subtraction of the current time T1 and the subtraction of the time T2 is greater than the preset time. If the difference between the current time T1 minus the time T2 is greater than 60 seconds, the time stamp data is deleted and new time stamp data is stored. After the slave clock node equipment stores new timestamp data, the slave clock node equipment calculates the frequency deviation and the time deviation of the slave clock node relative to the master clock node through a first timer according to the new timestamp data and a preset algorithm.
The present embodiment improves the accuracy of detection of the frequency deviation and the time deviation between two nodes by calculating the frequency deviation and the time deviation between the two nodes a plurality of times based on different time stamp data.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (such as a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present invention.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (8)
1. A time synchronization deviation detection method is characterized by comprising the following steps:
receiving a detection instruction of frequency deviation and time deviation, wherein the detection instruction at least comprises an enabling identifier of a detection message, and a reporting period of the frequency deviation and the time deviation;
according to the detection instruction, timestamp data of detection messages between nodes is acquired within preset time;
calculating to obtain frequency deviation and time deviation between the nodes through a preset algorithm according to the timestamp data;
the step of calculating the frequency deviation and the time deviation between the nodes by a preset algorithm according to the timestamp data comprises the following steps:
calculating to obtain a phase sum corresponding to the timestamp data according to the timestamp data;
calculating to obtain the frequency deviation between the nodes through a frequency deviation formula according to the phase sum;
calculating to obtain a first time deviation according to the timestamp data;
and correcting the clock of the detection message according to the first time deviation, and comparing the clock with the clock of the non-detection message to obtain a second time deviation, wherein the second time deviation is the time deviation between the nodes.
2. The method for detecting a time synchronization deviation according to claim 1, wherein the step of receiving the detection command of the frequency deviation and the time deviation further comprises, before the step of:
setting a maximum threshold value and a minimum threshold value corresponding to the frequency deviation and the time deviation;
after the step of calculating the frequency deviation and the time deviation between the nodes by a preset algorithm according to the timestamp data, the method further comprises the following steps:
and when the frequency deviation and/or the time deviation are larger than the corresponding maximum threshold value or smaller than the corresponding minimum threshold value, outputting alarm information.
3. The method according to claim 1, wherein after the step of obtaining the timestamp data of the detection packet between the nodes within a preset time according to the detection instruction, the method further comprises:
storing the timestamp data;
after the step of calculating the frequency deviation and the time deviation between the nodes by a preset algorithm according to the timestamp data, the method further comprises the following steps:
deleting the timestamp data and storing new timestamp data;
and calculating the frequency deviation and the time deviation between the nodes by a preset algorithm according to the new timestamp data.
4. The time synchronization deviation detecting method of claim 3, wherein the step of deleting the time stamp data and storing new time stamp data comprises:
acquiring a current time T1 and a time T2 at which the timestamp data is stored;
when the difference of the current time T1 minus the time T2 is greater than the preset time, the time stamp data is deleted and new time stamp data is stored.
5. A time synchronization deviation detecting apparatus, characterized by comprising:
a receiving module, configured to receive a detection instruction of a frequency deviation and a time deviation, where the detection instruction at least includes an enable identifier of a detection packet, and a reporting period of the frequency deviation and the time deviation;
the acquisition module is used for acquiring timestamp data of detection messages between nodes within preset time according to the detection instruction;
the calculation module is used for calculating and obtaining the frequency deviation and the time deviation between the nodes through a preset algorithm according to the timestamp data;
wherein the calculation module comprises:
the first calculation unit is used for calculating a phase sum corresponding to the timestamp data according to the timestamp data;
the second calculation unit is used for calculating and obtaining the frequency deviation between the nodes through a frequency deviation formula according to the phase sum;
the third calculating unit is used for calculating to obtain a first time deviation according to the timestamp data;
and the correcting unit is used for correcting the clock of the detection message according to the first time deviation and comparing the clock with the clock of the non-detection message to obtain a second time deviation, wherein the second time deviation is the time deviation between the nodes.
6. The time synchronization deviation detecting device according to claim 5, further comprising:
a setting module, configured to set a maximum threshold value and a minimum threshold value corresponding to the frequency deviation and the time deviation;
and the output module is used for outputting alarm information when the frequency deviation and/or the time deviation is greater than a corresponding maximum threshold value or less than a corresponding minimum threshold value.
7. The time synchronization deviation detecting device according to claim 5, further comprising:
the storage module is used for storing the timestamp data;
the deleting module is used for deleting the timestamp data and storing new timestamp data;
and the calculating module is also used for calculating the frequency deviation and the time deviation between the nodes through a preset algorithm according to the new timestamp data.
8. The time synchronization deviation detecting device according to claim 7, wherein the deleting module includes:
an acquisition unit for acquiring a current time T1 and a time T2 at which the time stamp data is stored;
and the deleting unit is used for deleting the timestamp data and storing new timestamp data when the difference of the current time T1 minus the time T2 is greater than the preset time.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510532505.7A CN106487467B (en) | 2015-08-26 | 2015-08-26 | Time synchronization deviation detection method and device |
| PCT/CN2016/083671 WO2017032113A1 (en) | 2015-08-26 | 2016-05-27 | Method and apparatus for measuring time synchronization deviation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510532505.7A CN106487467B (en) | 2015-08-26 | 2015-08-26 | Time synchronization deviation detection method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106487467A CN106487467A (en) | 2017-03-08 |
| CN106487467B true CN106487467B (en) | 2020-10-13 |
Family
ID=58099498
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510532505.7A Active CN106487467B (en) | 2015-08-26 | 2015-08-26 | Time synchronization deviation detection method and device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN106487467B (en) |
| WO (1) | WO2017032113A1 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106027193B (en) * | 2016-07-07 | 2019-06-18 | 广州市国飞信息科技有限公司 | For the clock synchronizing method of time calibration in network system, module, equipment and system |
| CN113138623A (en) * | 2020-01-20 | 2021-07-20 | 南京深视光点科技有限公司 | Global clock synchronous transmission method |
| CN112689963B (en) * | 2020-03-30 | 2022-01-11 | 华为技术有限公司 | Data processing method and device |
| CN111447674A (en) * | 2020-04-03 | 2020-07-24 | 南京大鱼半导体有限公司 | Node synchronization method, device, storage medium and node |
| CN111708302A (en) * | 2020-06-23 | 2020-09-25 | 吴松林 | System for synchronously acquiring biomechanical data by using mouse |
| CN114765586A (en) * | 2021-01-13 | 2022-07-19 | 华为技术有限公司 | Method, device and system for detecting time synchronization performance |
| CN113259038B (en) * | 2021-04-29 | 2022-06-21 | 北京邮电大学 | Time synchronization method, node, device and storage medium |
| CN114217104A (en) * | 2021-11-24 | 2022-03-22 | 深圳市道通智能汽车有限公司 | Indoor analog signal generation method and device and analog signal generator |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102237941A (en) * | 2010-04-28 | 2011-11-09 | 中兴通讯股份有限公司 | Time synchronization system and method |
| CN103139002A (en) * | 2011-11-30 | 2013-06-05 | 中兴通讯股份有限公司 | Detection method and device of 1588 time error between network elements |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8473638B2 (en) * | 2008-05-02 | 2013-06-25 | James Aweya | Method and apparatus for time and frequency transfer in communication networks |
| CN101895384A (en) * | 2010-07-07 | 2010-11-24 | 中兴通讯股份有限公司 | Method and device for implementing boundary clock |
| CN102148652B (en) * | 2011-02-17 | 2014-12-03 | 上海奇微通讯技术有限公司 | System and method for measuring network clock synchronization |
| CN104660359B (en) * | 2013-11-21 | 2019-01-11 | 中兴通讯股份有限公司 | A kind of method, apparatus and equipment of clock frequency deviation detection |
-
2015
- 2015-08-26 CN CN201510532505.7A patent/CN106487467B/en active Active
-
2016
- 2016-05-27 WO PCT/CN2016/083671 patent/WO2017032113A1/en active Application Filing
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102237941A (en) * | 2010-04-28 | 2011-11-09 | 中兴通讯股份有限公司 | Time synchronization system and method |
| CN103139002A (en) * | 2011-11-30 | 2013-06-05 | 中兴通讯股份有限公司 | Detection method and device of 1588 time error between network elements |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2017032113A1 (en) | 2017-03-02 |
| CN106487467A (en) | 2017-03-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106487467B (en) | Time synchronization deviation detection method and device | |
| EP2342850B1 (en) | A method for synchronizing clocks in a communication network | |
| WO2016054884A1 (en) | Frequency deviation monitoring method, device and computer storage medium | |
| CN107360060B (en) | Time delay measuring method and device | |
| JP6192995B2 (en) | COMMUNICATION DEVICE, COMMUNICATION SYSTEM, COMMUNICATION METHOD, AND COMPUTER PROGRAM | |
| WO2009043299A1 (en) | A determining method and device for the synchronization port of a transparent clock equipment | |
| CN109548135B (en) | Optimized wireless network time synchronization method | |
| CN104092740B (en) | Application data synchronous method and device | |
| EP4407900A1 (en) | Time synchronization apparatus, system, and method | |
| JP2014096853A (en) | Time synchronization device | |
| CN113098646A (en) | Time synchronization method and device, electronic equipment and storage medium | |
| CN101808167B (en) | Method for procedure tracking, device and system | |
| US20190239173A1 (en) | Determine abnormal clock | |
| JP2011511362A5 (en) | ||
| CN102833027B (en) | A kind of synchronous regime monitoring method based on time migration | |
| CN112199447A (en) | Database synchronization method, device and system and electronic equipment | |
| WO2014101668A1 (en) | Time synchronization processing method and apparatus | |
| CN108243396B (en) | Time synchronization processing method and device | |
| WO2018076651A1 (en) | Time synchronization method, device and computer storage medium | |
| EP2106052A2 (en) | Communication system, transmitting apparatus, receiving apparatus, communication method and record medium for transferring a clock in a packet network | |
| WO2015172398A1 (en) | Method and apparatus for acquiring packet transmission delay | |
| CN116781202A (en) | Method for adjusting synchronization period of TSN clock | |
| JP2018088644A (en) | Time synchronization method and time synchronization system between wirelessly-connected terminals | |
| CN110601786A (en) | Time synchronization method, relay equipment and device | |
| WO2016177240A1 (en) | Frequency synchronization method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20200617 Address after: 518057 Zhongxing building, A3-01, A3-02, Nanshan District hi tech Industrial Park, Shenzhen, Guangdong Applicant after: Shenzhen ZTE Technical Service Co.,Ltd. Address before: 518057 Nanshan District Guangdong high tech Industrial Park, South Road, science and technology, ZTE building, Ministry of Justice Applicant before: ZTE Corp. |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |