CN106486143A

CN106486143A - Sense amplifier

Info

Publication number: CN106486143A
Application number: CN201510531697.XA
Authority: CN
Inventors: 李智
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2015-08-26
Filing date: 2015-08-26
Publication date: 2017-03-08
Anticipated expiration: 2035-08-26
Also published as: CN106486143B

Abstract

A kind of sense amplifier, by arranging on-off circuit between described amplification reading circuit input and outfan, controls the described conducting amplified between reading circuit input and outfan and blocks.Before reading data, by turning on described amplification reading circuit input and outfan, make described amplification reading circuit input voltage and output voltage equal, so that the described reading circuit that amplifies is operated in the maximum state of voltage transmission gain, the i.e. small change of input voltage, you can cause the change that output voltage is larger.Therefore when on described bit line, voltage occurs minor variations, the described amplifying circuit that reads is the exportable data signal making described trigger output represent different pieces of information, thus improve the described amplifying circuit that reads to perceive the speed that institute's bitline voltage changes, improve the speed that described sense amplifier reads data in storage unit, improve the performance of memorizer.

Description

Sense amplifier

Technical field

The present invention relates to field of semiconductor manufacture, particularly to a kind of sense amplifier.

Background technology

Digital signal processor (Digital Signal Processor, DSP) and video coding algorithm memorizer The use of (Video Algorithm Coding Store), the requirement more and more higher to memorizer reading speed.

Sense amplifier (Sense Amplifier, SA) is an important component part of memorizer, directly The reading speed of impact memorizer.

With reference to Fig. 1, show a kind of structural representation of memorizer in prior art.Herein, apply only Illustrate as a example reading the circuit structure in memorizer (Read-Only Memory, ROM).

Multiple memory element 10 are connected to sense amplifier 20 by bit line bl.Voltage Vb on bit line bl is pre- Charge (Precharge) to high potential Vh.When the data of storage in memory cell is " 1 ", bit line Bl upper voltage Vb is constant；When the data of storage in memory element is " 0 ", the voltage Vb meeting on bit line bl It is reduced to electronegative potential Vl.Sense amplifier senses the change of voltage Vb on bit line bl, and by amplifying bit line The change of bl upper voltage Vb, the data of output memory cell storage is " 1 " or " 0 ".

However, with the raising of technique, memorizer memory storage element number increases, and sense amplifier loads Increase, but the operating current of sense amplifier is less and less.The reduction of sense amplifier operating current, Sense amplifier is made the reading speed of memory cell data voltage to be affected and reduce, thus have impact on The performance of memorizer.

Content of the invention

The problem that the present invention solves is to provide a kind of sense amplifier, to improve memorizer reading speed.

For solving the above problems, the present invention provides a kind of sense amplifier, for reading in read only memory Data storage in memory element, described sense amplifier is connected with described memory element by bit line, bag Include：

Pull-up circuit, in order to produce pull-up current；

Amplify reading circuit, be connected with described memory element by bit line, according to described pull-up current and The change of electric current on bit line, the change of voltage on sensing bit line, and by amplifying the change of voltage on bit line Export the output voltage related to institute's data storage in memory element；

On-off circuit, is connected between the described input amplifying reading circuit and outfan, for controlling The described conducting amplified between reading circuit input and outfan and blocking；

Trigger, according to the described output voltage related to institute data storage amplifying reading circuit output, Output stores up the corresponding data signal of data with described memory cell.

Optionally, described pull-up circuit includes：Analog module, is depositing of " 0 " for analog storage data Storage unit；Current mirror module, is connected with described analog module, for obtaining simulation from described analog module Read electric current, and electric current output pull-up current is read according to described simulation.

Optionally, described analog module includes：At least one is effectively stored with described memory element identical Unit, is the memory element of " 0 " for analog storage data；Described effective storage unit passes through mimotope Line is connected with described current mirror module all the time.

Optionally, described analog module also includes：Multiple with memory element identical invalid storage unit, Described invalid storage cell distribution is around described effective storage unit.

Optionally, described current mirror module includes：At least one input metal-oxide-semiconductor and at least one output mos Pipe；Described input metal-oxide-semiconductor includes first end, the second end and control end, the control of described input metal-oxide-semiconductor End processed is used for controlling leading between the first end of described input metal-oxide-semiconductor and the second end of described input metal-oxide-semiconductor Lead to and block；Described output mos pipe includes first end, the second end and control end, described output mos The control end of pipe controls between first end and second end of described output mos pipe of described output mos pipe Turn on and block；The described first end of input metal-oxide-semiconductor and the first end of described output mos pipe are used for receiving Supply voltage；The control end phase of described input the second end of metal-oxide-semiconductor and control end and described output mos pipe Even, and it is connected with described analog module；Second end of described output mos pipe and described amplification reading circuit It is connected, to export described pull-up current；The size of described input metal-oxide-semiconductor and the chi of described output mos pipe Very little one-tenth integral multiple relation.

Optionally, described current mirror module also includes：At least one input controls metal-oxide-semiconductor, described input Control the quantity of metal-oxide-semiconductor equal with the quantity of described input metal-oxide-semiconductor, control metal-oxide-semiconductor in described input When quantity is multiple, the plurality of input controls the size of metal-oxide-semiconductor all equal；Described input controls MOS Pipe include first end, the second end and and control end, described input controls the control end of metal-oxide-semiconductor to control institute State the conducting between the first end of input control metal-oxide-semiconductor and the second end of described input control metal-oxide-semiconductor and cut Disconnected；Described input controls the first end of metal-oxide-semiconductor to receive supply voltage；Described input controls the of metal-oxide-semiconductor Two ends are connected one to one with the first end of described input metal-oxide-semiconductor；Described input controls the control of metal-oxide-semiconductor End receives input control signal, described input control signal controls at least one input described to control metal-oxide-semiconductor Conducting or block, with control access input metal-oxide-semiconductor quantity.

Optionally, described current mirror module also includes：At least one output control metal-oxide-semiconductor, described output Control the quantity of metal-oxide-semiconductor equal with the quantity of described output mos pipe, in described output control metal-oxide-semiconductor When quantity is multiple, the size of the plurality of output control metal-oxide-semiconductor is all equal；Described output control MOS Pipe include first end, the second end and and control end, the control end of described output control metal-oxide-semiconductor controls institute State the conducting between the first end of output control metal-oxide-semiconductor and the second end of described output control metal-oxide-semiconductor and cut Disconnected；The first end of described output control metal-oxide-semiconductor receives supply voltage；The of described output control metal-oxide-semiconductor Two ends are connected one to one with the first end of described output mos pipe；The control of described output control metal-oxide-semiconductor End receives output control signal, and described output control signal controls at least one output control metal-oxide-semiconductor described Conducting or block, to control the quantity of the output mos pipe of access.

Optionally, described current mirror module also includes：At least one input controls metal-oxide-semiconductor；Described input The size controlling metal-oxide-semiconductor becomes integral multiple relation with the size of described output control metal-oxide-semiconductor.

Optionally, described amplification reading circuit includes：Read phase inverter, the input of described reading phase inverter End is connected with described memory element by bit line, and outfan is coupled with described trigger, according to described pull-up The change of electric current on electric current and bit line, the change of voltage on sensing bit line, and by amplifying electricity on bit line The change of pressure exports the output voltage related to institute's data storage in memory element.

Optionally, described on-off circuit includes：First switch, is connected to the defeated of described amplification reading circuit Enter between end and outfan, for controlling leading between the described input amplifying reading circuit and outfan Lead to and block.

Optionally, when reading data, described bit line is precharged to high potential；Described first switch is used Close after being pre-charged in bit line.

Optionally, described on-off circuit also includes：Second switch, in parallel with described first switch, connect Between the described input amplifying reading circuit and outfan, with the cooperation of described first switch, control institute State the conducting amplified between reading circuit input and outfan and block；The size of described second switch is little Size in described first switch.

Optionally, when reading data, described bit line is precharged to high potential；Described first switch is used After being pre-charged in bit line, the first moment closed；Described second switch is used for second after bit line precharge Moment closes, and described second moment is later than described first moment.

Optionally, described first switch includes at least one first switch metal-oxide-semiconductor；Described first switch MOS Pipe includes first end, the second end and control end, and the control end of described first switch metal-oxide-semiconductor controls described the Conducting between the one switch first end of metal-oxide-semiconductor and the second end of described first switch metal-oxide-semiconductor and blocking； The first end of described first switch metal-oxide-semiconductor is connected with the described input amplifying reading circuit；Described first Second end of switch metal-oxide-semiconductor is connected with the described outfan amplifying reading circuit；Described first switch MOS The control end of pipe receives first switch control signal, realizes described first according to first switch control signal and opens Close the conducting of metal-oxide-semiconductor or block, to control leading between described amplification reading circuit input and outfan Lead to and block.

Optionally, described second switch includes at least one second switch metal-oxide-semiconductor；Described second switch MOS Pipe includes first end, the second end and control end, and the control end of described second switch metal-oxide-semiconductor controls described the Conducting between the two switch first ends of metal-oxide-semiconductors and the second end of described first switch metal-oxide-semiconductor and blocking； The first end of described second switch metal-oxide-semiconductor is connected with the described input amplifying reading circuit；Described second Second end of switch metal-oxide-semiconductor is connected with the described outfan amplifying reading circuit；Described second switch MOS The control end of pipe receives second switch control signal, realizes described second according to second switch control signal and opens Close the conducting of metal-oxide-semiconductor and block, to control leading between described amplification reading circuit input and outfan Lead to and block.

Optionally, described sense amplifier also includes：Drive amplification circuit, reads for amplifying described amplification The output voltage related to institute's data storage in memory element of sense circuit output.

Optionally, described drive amplification circuit includes：At least one drives phase inverter, and described driving is anti-phase Device is connected between described amplification reading circuit and trigger.

Optionally, described sense amplifier also includes：Control circuit, for producing control signal to control The conducting of described on-off circuit and blocking.

Optionally, described sense amplifier also includes：Control circuit, described control circuit include with described The first control circuit that first switch is connected, for producing first switch control signal, to control described the One switch conducting or block.

Optionally, described sense amplifier also includes：Control circuit, described control circuit includes：With institute State the first control circuit that first switch is connected, for producing first switch control signal, described to control The conducting of first switch or block；The second control circuit being connected with described second switch, for producing the Two switch controlling signals, to control the conducting of described second switch or to block.

Compared with prior art, technical scheme has advantages below：

The present invention passes through to arrange on-off circuit, control between described amplification reading circuit input and outfan Make the described conducting amplified between reading circuit input and outfan and block.Before reading data, lead to Cross and turn on described amplification reading circuit input and outfan, make described amplification reading circuit input voltage and Output voltage is equal, so that the described reading circuit that amplifies is operated in the maximum state of voltage transmission gain, The i.e. small change of input voltage, you can cause the change that output voltage is larger.Therefore when on described bit line When voltage occurs minor variations, described reading amplifying circuit is exportable so that the output of described trigger is represented not With the data signal of data, thus improve the described amplifying circuit that reads to perceive institute's bitline voltage change Speed, improves the speed that described sense amplifier reads data in storage unit, improves memorizer Performance.

Optionally, in the alternative of this case, opened by arranging second in parallel with described first switch Close, and after first switch blocks described amplification reading circuit input and outfan, remain on conducting State, amplify the input voltage of reading circuit and output voltage keeps equal so that described, it is to avoid the When one switch blocks described amplification reading circuit input and outfan, parasitic capacitance reads to described amplification The impact of circuit input voltage it is ensured that when reading the data, the described electricity amplifying reading circuit input Pressure is equal with the voltage of described outfan, thus improve the speed that described sense amplifier reads data, Improve the performance of memorizer.

Brief description

Fig. 1 is a kind of structural representation of memorizer in prior art；

Fig. 2 is a kind of voltage-transfer characteristic curve of sense amplifier in prior art；

Fig. 3 to Figure 10 is the structural representation of sense amplifier one embodiment of the present invention.

Specific embodiment

By background technology it will be seen that existing memorizer has the slow problem of reading speed, deposit in conjunction with existing The performance profile reason of sense amplifier in reservoir：

Amplify the data voltage Vb on bit line frequently with phase inverter (Inverter) in sense amplifier.

The performance of phase inverter can be with representing the voltage-transfer characteristic curve of input-output voltage relationship (Voltage Transfer Characteristic, VTC) is measuring.With reference to Fig. 2, show in prior art A kind of voltage-transfer characteristic curve of sense amplifier.In figure transverse axis is input voltage vin, and the longitudinal axis is output Voltage Vout.Figure line 31 represents the Utopian voltage-transfer characteristic curve of phase inverter, and figure line 32 represents phase inverter Actual voltage-transfer characteristic curve.

The Utopian voltage-transfer characteristic curve of phase inverter is unit-step function (with reference to figure line 31 in Fig. 2), I.e. phase inverter can no postpone accurately to invert between high potential and electronegative potential.But in real device, The voltage-transfer characteristic curve of phase inverter is that there is transition region (with reference to figure line 32 in Fig. 2), if showing defeated Entering voltage is electronegative potential, then output voltage is high potential；Or input voltage is high potential, then export electricity Press as electronegative potential, the region that input voltage is located between v1 and v2 is transition region.The input voltage of phase inverter When in transition region, when input voltage changes, there is large change in its output voltage, that is, instead The performance of phase device transition region is so as to can use as power amplifier in analog circuit, and transition region Slope is bigger, and phase inverter gain is bigger.

When the data of storage in the memory element chosen is " 0 ", described bit line passes through memory element and connects Ground power supply Vss is connected, and therefore on bit line, voltage declines.So inverter input passes through bit line discharges, instead Phase device input voltage vin is gradually lowered by high potential, and therefore output voltage Vout is then gradually risen by electronegative potential High.Now, the trigger being connected with sense amplifier receives the inverter output voltage Vout of high potential. When trigger exports, trigger represents data according to the inverter output voltage Vout of high potential, output The data signal of " 0 ".

When the data of storage in the memory element chosen is " 1 ", described bit line does not have and memory element phase Even, therefore on bit line, voltage is constant.So the input voltage vin of phase inverter maintains high potential, so instead Phase device exports the output voltage Vout of electronegative potential.Now, trigger receives the phase inverter output of electronegative potential Voltage Vout.When trigger exports, trigger is according to the inverter output voltage Vout of electronegative potential, defeated Go out to represent the data signal of data " 1 ".With the raising of technique, memorizer memory storage element number increases, Sense amplifier load increases, but memory operation electric current is less and less.According to electricity relation： C × Δ V=I × Δ t, in the case that voltage V variable quantity is constant, electric capacity C increases, and electric current I reduces, and the time, Δ t can increase Greatly.That is, with the increase of load, the curent change on bit line reduces, selected when reading During data storage in memory element, the electric current producing with change in voltage on bit line becomes less and less, Inverter input charges, the electric current of electric discharge diminishes, and that is, inverter input voltage pace of change diminishes, from And phase inverter perceives the slowing of change in voltage on bit line, i.e. sense amplifier perception bit-line voltage change Slow, therefore memorizer reading speed reduce, have impact on the performance of memorizer.

For solving described technical problem, the present invention provides a kind of sense amplifier, including：

Pull-up circuit, in order to produce pull-up current；Amplify reading circuit, single with described storage by bit line Unit is connected, and according to the change of electric current on described pull-up current and bit line, senses the change of voltage on bit line, And the output electricity related to institute's data storage in memory element by amplifying the change output of voltage on bit line Pressure；On-off circuit, is connected between the described input amplifying reading circuit and outfan, for controlling The described conducting amplified between reading circuit input and outfan and blocking；Trigger, puts according to described Output voltage, output and the described memory cell related to institute data storage of big reading circuit output The corresponding data signal of storage data.

Understandable for enabling the above objects, features and advantages of the present invention to become apparent from, below in conjunction with the accompanying drawings The specific embodiment of the present invention is described in detail.

With reference to Fig. 3, show the functional block diagram of sense amplifier one embodiment provided by the present invention.

It should be noted that sense amplifier provided by the present invention is used for reading read only memory memory storage Data storage in unit 1100, described sense amplifier passes through bit line BL and described memory element 1100 It is connected.Described memory element 1100 is by CE signal (Chip Enable, CE) in read only memory Storage array 1000 in select.

Described sense amplifier includes：

Pull-up circuit 100, in order to produce pull-up current I_up.

In conjunction with reference to Fig. 4, show the functional block diagram of pull-up circuit 100 in Fig. 3.

Described pull-up circuit 100 includes：It is the analog module of " 0 " memory element for analog storage data 110 and be used for exporting pull-up current I_upCurrent mirror module 120.

Specifically, described analog module 110 includes at least one and described storage array 1000 memory storage list First 1100 identical effective storage units 111, are the memory element of " 0 " for analog storage data.Institute State effective storage unit 111 and be connected with described current mirror module 120 all the time by simulating bit line BL.ref.

It should be noted that because performance of semiconductor device can change with the change of local environment, being Make the performance of described effective storage unit 111 with the performance of described memory element 1100 close.This enforcement In example, described analog module 110 also includes：Multiple with described memory element 1100 identical invalid storage Unit 112, described invalid storage unit 112 is distributed in around described effective storage unit 111.

In conjunction with reference to Fig. 5, show the electricity of invalid storage unit 112 and effective memory module 111 in Fig. 4 Line structure figure.

It should be noted that because memory element 1100 described in the present embodiment is to be made up of NMOS tube, Correspondingly, described effective storage unit 111 and invalid storage unit 112 are all to be made up of NMOS tube. But the present invention is to described memory element 1000, effective storage unit 111 and invalid storage unit 112 Concrete structure do not do any restriction.

Described effective storage unit 111 includes NMOS tube df.The grid dfG of described NMOS tube df Receive supply voltage Vdd；The source electrode dfS of described NMOS tube df is connected with described simulation bit line BL.ref, Produce simulation and read electric current I_sim.read；The drain electrode dfD of described NMOS tube df connects earthing power supply Vss. Grid dfG due to described NMOS tube df accepts supply voltage Vdd, therefore described NMOS tube df Remain conducting state.That is, described effective storage unit 111 and data storage are " 0 " Memory element 1100 is identical, and electric current I is read in therefore produced simulation_sim.readAlso with reading data storage it is Reading electric current I during the memory element of " 0 ", on bit line BL_readEqual.

Described invalid storage unit 112 includes NMOS tube dm1.The grid of described NMOS tube dm1 Dm1G also connects supply voltage Vdd；But the source electrode dm1S of described NMOS tube dm1 and drain electrode dm1D Be connected short circuit.Because described invalid storage unit 112 is not connected with external circuit, therefore in described spirit When quick amplifier carries out digital independent, described invalid storage unit 112 in described sense amplifier not Any electricity effect is provided.

It should be noted that the source electrode dm1S of NMOS tube dm1 described in the present embodiment and drain electrode dm1D It is connected and constitute a way only example of invalid storage unit 112.In other embodiments of the present invention, institute State invalid storage unit to can also be as shown in fig. 6, described invalid storage unit 112 ' includes NMOS tube Dm2, the grid dm2G of described NMOS tube dm2 receives supply voltage Vdd；Described NMOS tube The drain electrode dm2D of dm2 connects earthing power supply Vss；But the source electrode of described NMOS tube dm2 is not connected to Any device.Similar, described invalid storage unit 112 ' is not also connected with external circuit, in described spirit Any electricity effect is not provided in quick amplifier.Additionally, the present invention is to described invalid storage unit 112 Concrete connected mode be not limited, identical with described memory element 1100 structure, but described sensitive The connected mode not providing electricity effect in amplifier all may make up invalid storage unit 112.

With continued reference to Fig. 4, described pull-up circuit 100 also includes current mirror module 120, with described simulation mould Block 110 is connected, and reads electric current I for obtaining simulation from described analog module 110_sim.read, according to described mould Intend reading electric current I_sim.readOutput pull-up current I_up.

Specifically, described current mirror module 120 is passed through to simulate bit line BL.ref and described analog module 110 In effective storage unit 111 be connected, with obtain described simulation read electric current I_sim.read, and by described Electric current I is read in simulation_sim.readCarry out mirror image, output reads electric current I with described simulation_sim.readRelated pull-up electricity Road I_up.

It should be noted that because described effective storage unit 111 and data storage are the storage list of " 0 " Unit 1100 is identical, and electric current I is read in therefore described simulation_sim.readIt is the storage list of " 0 " with reading data storage During unit 1100, the reading electric current I on bit line BL_readEqual that is to say, that pull-up current I_upAll the time with When reading the memory element 1100 that data storage is " 0 ", the reading electric current I on bit line BL_readRelated.

Described current mirror module 120 includes：

At least one input metal-oxide-semiconductor and at least one output mos pipe.

Described input metal-oxide-semiconductor includes first end, the second end and control end, the control of described input metal-oxide-semiconductor End processed is used for controlling leading between the first end of described input metal-oxide-semiconductor and the second end of described input metal-oxide-semiconductor Lead to and block.

Described output mos pipe includes first end, the second end and control end, the control of described output mos pipe End processed control conducting between the first end of described output mos pipe and the second end of described output mos pipe and Block.

The described first end of input metal-oxide-semiconductor and the first end of described output mos pipe all receive supply voltage Vdd；Second end of described input metal-oxide-semiconductor is connected with the control end of described output mos pipe with control end, And be connected with described analog module 110 to export described simulation reading electric current I_sim.read；Described output mos pipe Second end export described pull-up current I_up.

It should be noted that described current mirror module 120 is passed through to input metal-oxide-semiconductor and output mos pipe chi Very little difference, realizes the image feature of electric current, therefore, the size of described output mos pipe and described output The size of metal-oxide-semiconductor becomes integral multiple related.In the present embodiment, described input metal-oxide-semiconductor size with described Output mos pipe equal sized, can be by adjusting the quantity of input metal-oxide-semiconductor and output mos pipe It is adjusted pull-up current I_upSize, control difficulty and technology difficulty to reduce.

Because, in the present embodiment, described input metal-oxide-semiconductor is equal with output mos pipe size, by changing The input metal-oxide-semiconductor quantity of circuit is accessed, to obtain different size of described pull-up in current mirror module 120 Electric current I_up.So, in the present embodiment, described current lens unit 120 also includes at least one input and controls Metal-oxide-semiconductor, described input controls the quantity of metal-oxide-semiconductor equal with the quantity of described input metal-oxide-semiconductor, and When the quantity of described input control metal-oxide-semiconductor is multiple, the plurality of input controls the size of metal-oxide-semiconductor equal Equal.

Specifically, described input control metal-oxide-semiconductor include first end, the second end and and control end, described Input controls the control end of metal-oxide-semiconductor to control described input to control the first end of metal-oxide-semiconductor and described input to control Conducting between second end of metal-oxide-semiconductor and blocking.

Described input controls the first end of metal-oxide-semiconductor to receive supply voltage Vdd；Described input controls metal-oxide-semiconductor The second end with described input metal-oxide-semiconductor first end connect one to one；Described input controls metal-oxide-semiconductor Control end receives input control signal, described input control signal controls at least one input described to control The conducting of metal-oxide-semiconductor or block, to control the quantity of the input metal-oxide-semiconductor of access, thus adjust pull-up electricity Stream I_upSize.

In order to strengthen described current mirror module 120 to pull-up current I_upRegulating power, in the present embodiment, institute State current mirror module 120 also to include：At least one output control metal-oxide-semiconductor, described output control metal-oxide-semiconductor Quantity is equal with the quantity of described output mos pipe, and described output control metal-oxide-semiconductor quantity be multiple When, the size of the plurality of output control metal-oxide-semiconductor is all equal.

Specifically, described output control metal-oxide-semiconductor include first end, the second end and and control end, described The control end of output control metal-oxide-semiconductor controls the first end of described output control metal-oxide-semiconductor and described output control Conducting between second end of metal-oxide-semiconductor and blocking.

The first end of described output control metal-oxide-semiconductor receives supply voltage；The of described output control metal-oxide-semiconductor Two ends are connected one to one with the first end of described output mos pipe；The control of described output control metal-oxide-semiconductor End receives output control signal, and described output control signal controls at least one output control metal-oxide-semiconductor described Conducting or block, to control the quantity of the output mos pipe of access.

It should be noted that in order that adjusting easy, making input metal-oxide-semiconductor and output mos pipe size equal, Pull-up current I is realized by the quantity changing input metal-oxide-semiconductor and output mos pipe_upThe regulation of size.By Controlling metal-oxide-semiconductor and output control metal-oxide-semiconductor in input is string with described input metal-oxide-semiconductor and output mos pipe Connection connects, and is therefore carrying out pull-up current I_upRegulation during, described input controls metal-oxide-semiconductor and defeated Go out to control the size of metal-oxide-semiconductor also can count in the regulatory function of current mirror module 120.So, in order to Reduce and adjust difficulty, in the present embodiment, described input controls the size of metal-oxide-semiconductor and described output control MOS The size of pipe becomes integral multiple relation.

Specifically, in conjunction with reference to Fig. 7, show the particular circuit configurations figure of current mirror module 120 in Fig. 4.

In the present embodiment, described current mirror module 120 input includes：First input controls PMOS Mci1 and first input PMOS mi1, and the second input controls PMOS mci2 and second defeated Enter PMOS mi2.

Described first input controls the source electrode mci1S of PMOS mci1 to receive supply voltage Vdd；Grid Mci1G receives input control signal；The source electrode that drain electrode mci1D inputs PMOS mi1 with described first Mi1S is connected.

Described second input controls the source electrode mci2S of PMOS mci2 also to receive supply voltage Vdd；Grid Pole mci2G receives input control signal；The source that drain electrode mci2D inputs PMOS mi2 with described second Pole mi2S is connected.

The grid mi1G of the first input PMOS mi1, drain electrode miD are connected, described second input PMOS The grid mi2G of pipe mi2, drain electrode mi2D are connected, and are connected with simulation bit line BL.ref, to export mould Intend reading electric current I_sim.read.

It should be noted that described first input controls the grid mci1G of PMOS mci1 and described Second input controls the input control signal that PMOS mci2 grid mci2G receives, by controlling institute State first input control PMOS mci1 and described second input control PMOS mci2 conducting or Block, control the quantity of the input PMOS accessing circuit, to adjust current mirror module 120 output Described pull-up current I_upSize.

Described current mirror module 120 outfan includes：Output pmos mo and output control PMOS Pipe moc.

Specifically, the source electrode moS of described output pmos mo receives supply voltage Vdd；Grid moG Grid mi1G, drain electrode miD and described second input with the described first input PMOS mi1 The grid mi2G of PMOS mi2, drain electrode mi2D are connected；Drain electrode and described output control PMOS The source electrode mocS of moc is connected.The source electrode mocS of described output control PMOS moc is defeated with described The drain electrode moD going out PMOS mo is connected；Grid mocG receives output control signal；Drain electrode mocD Output pull-up current I_up.

It should be noted that in the present embodiment, the grid mocG of described output control PMOS moc Receive output control signal, by controlling the conducting of described output control PMOS or blocking, control institute State pull-up current I_upOutput.

To sum up, in the present embodiment, in current mirror module 120, input is provided with 2 input PMOS And correspond, with described 2 input PMOS, 2 output control PMOS being connected, defeated Go out end and be provided with 1 output pmos and 1 output control PMOS being attached thereto.And 2 Individual described input PMOS is equivalently-sized with 1 described output pmos, and 2 described inputs control PMOS and 1 described output control PMOS are equivalently-sized.

Therefore when the first input controls PMOS mci1 and the second input to control PMOS mci2 all to lead When logical, that is, described first input PMOS mi1 and the second input PMOS mi2 all access circuit, When described output control PMOS moc is also switched on, according to current mirror image theory, described current mirror mould The pull-up current I of block 120 output_upIt is that electric current I is read in described simulation_sim.readHalf, that is,：I_up=1/2I_sim.read.

When reading data in described memory element 1100, described bit line BL is precharged (Precharge) To high potential, described simulation bit line BL.ref is also precharged to high potential simultaneously.Due to described mimotope Line BL.ref is connected with described effective storage unit 111, and described effective storage unit 111 and storage number Identical according to the memory element 1100 for " 0 ".Therefore, no matter the number of described memory element 1100 memory storage According to being " 0 " or " 1 ", electric current I is read in the simulation on described simulation bit line BL.ref_sim.readAll the time with reading When to take data storage be " 0 ", electric current I on bit line BL_read.0Equal in magnitude, i.e. I_sim.read=I_read.0. And pull-up current I_upIt is that electric current I is read in simulation_sim.readHalf, so pull-up current I_upNamely read and deposit When storage data is " 0 ", electric current I on bit line BL_read.0General, that is,：I_up=1/2I_read.0.

It should be noted that in the present embodiment, reading storage array 1000 internal memory storage unit 1100 During data, the way that described bit line BL is precharged to high potential is only an example, and in the present invention, other are real Apply in example, the way of earthing power supply Vss can also be pulled down to using bit line BL, the present invention does not do to this Limit.

With continued reference to Fig. 4, because described effective storage unit 111 and data storage are the storage list of " 0 " Unit 1100 is identical, and that is, NMOS tube df is passed through to simulate bit line BL.ref and current mirror module 120 phase all the time Even.In addition the grid of NMOS tube df connects supply voltage Vdd, and therefore NMOS tube df also keeps leading Logical state, so by described effective storage unit 111, simulation bit line BL.ref and current mirror module, Described supply voltage Vdd is connected with earthing power supply Vss all the time.So existing at described analog module 110 Larger leaky.In order to reduce the electric leakage of described analog module 110, in described analog module 110 It is provided with and described current mirror module 120 between with reference to read switch 130, for when being read out, leading Lead to described current mirror module 120 and described analog module 110.

Specifically, described reference read switch 130 is made up of metal-oxide-semiconductor.In the present embodiment, described reference Read switch 130 includes NMOS tube mc.The source electrode mcS of described NMOS tube mc connects current mirror Module 120, the drain electrode mcD of described NMOS tube mc connects analog module 110, described NMOS tube The grid of mc receives CE signal (Chip Enable, CE) that is to say, that working as the choosing of CE signal When selecting memory element and being read out, described just turn on reference to read switch 130, effectively reduce pull-up The electric leakage of circuit 100.But in the present embodiment, described reference read switch 130 is constituted using NMOS tube Way be only an example, the present invention does not limit to the described composition structure with reference to read switch 130.

With continued reference to Fig. 3, described sense amplifier also includes：Amplify reading circuit 200 and on-off control electricity Road 300.

Described amplification reading circuit 200, is connected with described memory element 1100 by bit line BL, according to described Pull-up current I_upAnd electric current I is read on bit line BL_readChange, sensing bit line BL on voltage change, And by amplify the change of the upper voltage of bit line BL export related to institute's data storage in memory element 1100 defeated Go out voltage V_OUT.

Specifically, described amplification reading circuit 200 includes：Read phase inverter 210, described reading phase inverter 210 input IN is connected with described memory element 1100 by bit line BL, and outfan OUT exports The output voltage V related to institute's data storage in memory element_OUT.Described reading phase inverter 210 is according to institute State pull-up current I_upAnd electric current I is read on bit line BL_readChange, sensing bit line BL on voltage change Change, and by amplifying the change of voltage on bit line BL, obtain and institute's data storage in memory element 1100 Related output voltage V_OUT.

It should be noted that described read phase inverter 210 input IN also with described pull-up circuit 100 Outfan be connected, for receiving the pull-up current I of described pull-up circuit 100 output_up.

Therefore, described amplification reading circuit 200 reads during data in memory element 1100 it may appear that as follows Situation：

When the data of described memory element 1100 memory storage is " 0 ", described memory element 1100 and institute Rheme line BL is connected, and the stored unit 1100 of described bit line BL is connected with described earthing power supply Vss, On described bit line BL, voltage declines.Reading electric current I on described bit line BL_readMake described reading phase inverter 210 input IN electric discharges, to reduce the described input voltage V reading phase inverter 210_IN.

Additionally, the outfan also with described pull-up circuit 100 for the input IN of described reading phase inverter 210 It is connected, receive the pull-up current I of described pull-up circuit 100 output_up, described pull-up current I_upCan make described Read phase inverter 210 input IN to charge, raise the described input voltage V reading phase inverter 210_IN. But pull-up current Iup is only and now reads electric current I_readHalf (I_up=1/2I_read.0).Therefore, institute State and read phase inverter 210 input IN eventually in the pull-down current I reading electric current half size_down (I_down=I_read-I_up=I_read.0-1/2I_read.0=1/2I_read.0) the lower electric discharge of effect, described reading phase inverter 210 Input voltage V_INCan reduce, output voltage V_OUTIncrease, read phase inverter 210 and export high electricity The output voltage V of position_OUT.

When described memory element 1100 memory storage data be " 1 " when, described memory element 1100 not with Described bit line BL is connected, and therefore bit line BL is not connected with described earthing power supply Vss, described bit line BL Keep the high potential after precharge constant.

The input IN phase also with described pull-up circuit 100 for the input IN of described reading phase inverter 210 Even, receive the pull-up current I of described pull-up circuit 100 output_up, described pull-up current I_upDescribed reading can be made Take phase inverter 210 input IN to charge, raise the described input voltage reading phase inverter 210 further V_IN.Therefore, in pull-up current I_upIn the presence of, the described input voltage V reading phase inverter 210_INMeeting Raise further, output voltage V_OUTDecrease, the described phase inverter 210 that reads exports the defeated of electronegative potential Go out voltage V_OUT.

Described on-off circuit 300, is connected to the described input IN amplifying reading circuit 200 and outfan Between OUT, for controlling the conducting between described amplification reading circuit 200 input IN and outfan OUT With block.

It should be noted that described sense amplifier can also include control circuit 305 for produce control The conducting of described on-off circuit 300 and the control signal blocked.

When described ON-OFF control circuit 300 receives control signal, make described reading phase inverter 210 Input IN and outfan OUT turns on, and described input IN is joined directly together with described outfan OUT, Therefore described input voltage V_INWith output voltage V_OUTEqual.Now, at described reading phase inverter 210 In the state that voltage transmission gain is maximum, i.e. input voltage V_INSmall change, you can cause output voltage V_OUTLarger change.

Specifically, described ON-OFF control circuit 300 includes first switch 310, is connected to described amplification and reads Between circuit 200 input IN and outfan OUT, for controlling described input IN and outfan Conducting between OUT and blocking.

When reading data in described memory element 1100, when line precharge is entered to described bit line BL, Described first switch 310 is opened, and turns on described amplification reading circuit 200 input IN and outfan OUT, Make described input IN and outfan OUT current potential equal；After described bit line BL is precharged to high potential, Described first switch 310 is closed, to block described amplification reading circuit 200 input IN and outfan OUT, makes described input IN and outfan OUT maintain isoelectric level state.

It should be noted that described control circuit 305 can also include being connected with described first switch 310 First control circuit 315, for produce control described first switch 310 turn on and block first control Signal.After described bit line BL is precharged to high potential, described first control circuit 315 produces the first control Signal processed, described first switch 310 is switched to block by conducting under the control of the first control signal, so that Institute input IN and outfan OUT maintains isoelectric level state.

It should be noted that in order to avoid ON-OFF control circuit 300 described in effect of parasitic capacitance is to described amplification Blocking between reading circuit 200 input IN and outfan OUT.In the present embodiment, described on-off control Circuit 300 also includes：Second switch 320, in parallel with described first switch 310, it is connected to described amplification and read Between sense circuit 200 input IN and outfan OUT, coordinate with described first switch 310, control described Amplify the conducting between reading circuit 200 input IN and outfan OUT and block.

Therefore, data in reading memory element 1100, when line precharge is entered to described bit line BL, institute State first switch 310 and described second switch 320 is all opened, conducting described amplification reading circuit 200 is defeated Enter to hold IN and outfan OUT, so that described input IN and outfan OUT current potential are equal；Work as institute After rheme line BL is precharged to high potential, described first switch 310 was closed in the first moment, to block Described input IN and outfan OUT.

Afterwards, described second switch 320 was closed in the second moment, and described second moment is later than described first Moment.When first switch 310 is when closing in the first moment, due to the impact of parasitic capacitance, described input Voltage V_INCan raise.Now, the second switch 320 of conducting state is still maintained can to make described input IN With outfan OUT conducting.So, the described input voltage V amplifying reading circuit 200_INCan be further It is reduced to and described output voltage V_OUTEqual.When second switch 320 after second the moment close, When described input IN and outfan OUT is completely cut off, the input electricity of described amplification reading circuit 200 Pressure V_INWith output voltage V_OUTEqual.

Additionally, in the present embodiment, described second switch 320 be smaller in size than described first switch 310, with When reducing described second switch 320 closing, parasitic capacitance inputs to described amplification reading circuit 200 as far as possible Voltage V_INImpact.

It should be noted that in the present embodiment, described control circuit 305 includes producing and first switch 310 Connected first control circuit 315 and the second control circuit 325 being connected with second switch 320.Reading Take data in memory element 1100, when line precharge is entered to described bit line BL, described first control circuit 315 produce the first control signal in the first moment, and described first switch 310 is receiving the first control signal Block the connection between described input IN and outfan OUT afterwards；After first switch 310 is blocked, Described second control circuit 325 produces the second control signal in the second moment, and described second switch 320 exists Block after receiving the second control signal, so that electrically connecting between described input IN and outfan OUT Block, so that described amplification is blocked between reading circuit 200 input IN and outfan, and input electricity Pressure V_INWith output voltage V_OUTEqual.

When reading data in memory element 1100, due to after bit line BL is precharged to high potential, institute State ON-OFF control circuit 300 to switch to block by conducting.Therefore, the described input amplifying reading circuit 300 Voltage V_INWith output voltage V_OUTReading bit line BL is equal during voltage that is to say, that institute State the input voltage V reading phase inverter 210_INWith output voltage V_OUTIt is equal when reading data, So the described phase inverter 210 that reads is operated in the maximum state of voltage transmission gain, i.e. input voltage V_IN Small change, you can cause output voltage V_OUTLarger change.Therefore when electricity on described bit line BL During the raw minor variations of pressure, the output voltage V of described reading phase inverter 210_OUTLarger change can occur Changing, thus improve the speed that described reading amplifying circuit 200 perceives described bit line BL change in voltage, carrying High described sense amplifier reads the speed of data in memory element 1100, improves the performance of memorizer.

Specifically, in the present embodiment, described first switch 310 includes at least one first switch metal-oxide-semiconductor；

Described first switch metal-oxide-semiconductor includes first end, the second end and control end, described first switch MOS The control end of pipe controls the of the first end of described first switch metal-oxide-semiconductor and described first switch metal-oxide-semiconductor Conducting between two ends and blocking.

The first end of described first switch metal-oxide-semiconductor is connected with the described input IN amplifying reading circuit 200； Second end of described first switch metal-oxide-semiconductor is connected with the described outfan OUT amplifying reading circuit 200；Institute The control end stating first switch metal-oxide-semiconductor receives first switch control signal, according to first switch control signal Realize the conducting of described first switch metal-oxide-semiconductor or block, to control described amplification reading circuit input IN Conducting and outfan OUT between and blocking.

Described second switch 320 includes at least one second switch metal-oxide-semiconductor：

Described second switch metal-oxide-semiconductor includes first end, the second end and control end, described second switch MOS The control end of pipe controls the first end of described second switch metal-oxide-semiconductor and the second of described first switch metal-oxide-semiconductor Conducting between end and blocking.

The first end of described second switch metal-oxide-semiconductor is connected with the described input IN amplifying reading circuit 200； Second end of described second switch metal-oxide-semiconductor is connected with the described outfan OUT amplifying reading circuit 200；Institute The control end stating second switch metal-oxide-semiconductor receives second switch control signal, according to second switch control signal Realize the conducting of described second switch metal-oxide-semiconductor and block, to control described amplification reading circuit 200 input Conducting between IN and outfan OUT and blocking.

In conjunction with reference to Fig. 8, showing that Fig. 3 amplifies the concrete of reading circuit 200 and ON-OFF control circuit 300 Circuit diagram.

In the present embodiment, described reading phase inverter 210 is CMOS inverter, including a reading PMOS Pipe mu and reading NMOS tube md.

The described source electrode muS reading PMOS mu receives supply voltage Vdd；Described reading PMOS The drain electrode muD of pipe mu with described read NMOS tube md source electrode mdS be connected, and with described reading The outfan OUT of phase inverter 210 is connected；The described drain electrode mdD reading NMOS tube md connects Ground power supply Vss；The described reading grid muG of PMOS mu and the grid of described reading NMOS tube MdG is connected in the described input IN reading phase inverter 210, and is connected with bit line BL.

In described ON-OFF control circuit 300, in order to improve to described amplification reading circuit 200 input and The performance blocked between outfan, described first switch 310 includes：First switch PMOS sp1 and First switch NMOS tube sn1.

The source electrode sp1S of described first switch PMOS sp1 and the source of described first switch NMOS tube Pole sn1S is connected with the input IN amplifying reading circuit 200；Described first switch PMOS sp1 Drain electrode sp1D and described first switch NMOS tube drain electrode sn1D with amplify reading circuit 200 defeated Go out to hold OUT to be connected；The grid sp1G of described first switch PMOS sp1 and described first switch The grid sn1G of NMOS tube sn1 receives first switch control signal, in order to control described first switch 310 Conducting or block.

Described second switch 320 includes：Second switch PMOS sp2 and second switch NMOS tube sn2.

The source electrode sp2S of described second switch PMOS sp2 and described second switch NMOS tube sn2 Source electrode sn2S with amplify reading circuit 200 input IN be connected；Described second switch PMOS The source electrode sn2D of the drain electrode sp2D of sp2 and described second switch NMOS tube sn2 and amplification reading circuit 200 outfan OUT is connected；The grid sp2G of described second switch PMOS sp2 and described The grid sn2G of two switch NMOS tube sn2 receives second switch control signal, in order to control described second Switch 320 conducting with block.

With continued reference to Fig. 3, described sense amplifier also includes trigger 400, reads electricity according to described amplification The output voltage V related to institute data storage of road 400 output_OUT, export and described memory element 1100 The corresponding data signal of store data inside.

Specifically, amplify, when described, the output voltage V that reading circuit 200 exports high potential_OUTWhen, described Trigger 400 receives the output voltage V of high potential_OUT.Therefore, when trigger 400 exports, root Output voltage V according to high potential_OUT, the data signal of output expression data " 0 ".When described amplification is read Circuit 200 exports the output voltage V of electronegative potential_OUTWhen, described trigger 400 receives the defeated of electronegative potential Go out voltage V_OUT.Therefore, when trigger 400 exports, according to the output voltage V of electronegative potential_OUT, defeated Go out to represent the data signal of data " 1 ".

Phase inverter 210 voltage-transfer characteristic curve is read in conjunction with reference to Fig. 9, showing shown in Fig. 3.

Specifically, in figure, abscissa represents described reading phase inverter 210 input voltage V_IN, vertical coordinate table Show described reading phase inverter 210 output voltage V_OUT, figure line 90 represent described read phase inverter 210 electricity Pressure transmission characteristic, figure line 91 represents described reading phase inverter 210 input voltage V_INWith output voltage V_OUT Equal, V_IN=V_OUT.In the present embodiment, the intersection point 92 of described figure line 91 and described figure line 90, represent As described reading phase inverter 210 input voltage V_INWith output voltage V_OUTEqual state.

When reading data in storage array 1000, when described bit line BL is precharged, described first Switch 310 and described second switch 320 turn on the described input amplifying reading circuit 200 and outfan, Make described reading phase inverter 210 input IN and outfan OUT voltage equal.Therefore described reading is anti- The input voltage V of phase device 210_INWith output voltage V_OUTEqual.

Before described sense amplifier starts to read data in storage array 1000, control letter in first switch Number and under second switch control signal controls, described first switch 310 and described second switch 320 are first Block the described input IN and outfan OUT reading phase inverter 210 afterwards.Now, described reading is anti-phase The input voltage V of device 210_INMaintain and described output voltage V_OUTEqual, i.e. described reading phase inverter 210 State near described intersection point 92.

When described sense amplifier starts to read data, on bit line BL, voltage can be with the storage list reading The difference of first 1100 store data inside and lift：

When described memory element 1100 store data inside be " 0 " when, described reading phase inverter 210 defeated Enter voltage V_INCan reduce, output voltage V_OUTCan increase；When described storage power supply 1100 memory storage When data is " 1 ", the input voltage V of described reading phase inverter 210_INCan raise, output voltage V_OUT Can decrease.It is known that as input voltage V according to phase inverter voltage-transfer characteristic_INAnd output voltage V_OUTWhen equal, when being that phase inverter voltage transmission gain is maximum, i.e. input voltage V_INLess change Change, you can cause output voltage V_OUTLarger change.

Specifically, when the data of described memory element 1100 memory storage is " 0 ", described reading is anti-phase The input voltage V of device 210_INIn pull-down current I_downEffect is lower to be reduced.Due to described reading phase inverter 210 State near intersection point 92, therefore, as described input voltage V_INIn a slight decrease, described reading is anti- Phase device 210 output voltage V_OUTRise very rapidly up to high potential, described trigger 400 receive high potential Output voltage V_OUT.When trigger 400 exports, according to the output voltage V of high potential_OUT, output Represent the data signal of data " 0 ".

When described memory element 1100 store data inside be " 1 " when, described reading phase inverter 210 defeated Enter voltage V_INRise in the presence of pull-up current Iup.Similar, due to described reading phase inverter 210 State near intersection point 92, therefore, as described input voltage V_INSlightly raise, described reading is anti- Phase device 210 output voltage V_OUTIt is dropped rapidly to electronegative potential, described trigger 400 receives electronegative potential Output voltage V_OUT.When trigger 400 exports, according to the output voltage V of electronegative potential_OUT, export table Registration is according to the data signal of " 1 ".

Because the described phase inverter 210 that reads is operated in the maximum state of voltage transmission gain.Therefore when described When on bit line BL, voltage occurs minor variations, described reading phase inverter 210 is exportable to make described trigger 400 outputs represent the data signals of different pieces of informations, thus improve described reading phase inverter 210 perceive described The speed of bit line BL change in voltage, improves described sense amplifier and reads data in memory element 1100 Speed, improve the performance of memorizer.

With continued reference to Fig. 3, it should be noted that touching to described to improve described amplification reading circuit 200 Send out the driving force of device 400, in the present embodiment, described sense amplifier also includes：Drive amplification circuit 500, for amplify described amplify reading circuit 400 output with institute's data storage in memory element 1100 Related output voltage.

Specifically, described drive amplification circuit 500 includes at least one driving phase inverter, and described driving is anti- Phase device is connected between described amplification reading circuit 200 and trigger 400.In the present embodiment, described drive Dynamic amplifying circuit 500 includes the first driving phase inverter 510 and drives phase inverter 510 phase with described first Second driving phase inverter 520 of series connection, to improve the described driving force amplifying reading circuit 400.

Specifically, the input of described first driving phase inverter 510 and described reading amplifying circuit 200 Outfan OUT is connected, and receives the described output voltage V reading amplifying circuit 200_OUT；Described first drive The outfan of dynamic phase inverter 510 is connected with the input of the described second driving phase inverter 520, will be through one The voltage signal of secondary anti-phase amplification sends to the described second driving phase inverter 520；Described second driving phase inverter 520 outfan is connected with described trigger 400, for passing through the voltage signal of second anti-phase amplification V_OUT.ampSend to described trigger 400, described trigger 400 is according to the voltage amplifying through second Signal V_OUT.amp, export corresponding data signal.

In conjunction with reference to Figure 10, show the physical circuit figure of drive amplification circuit 500 in Fig. 3.

In the present embodiment, described first driving phase inverter 510 and described second driving phase inverter 520 are CMOS inverter.

Specifically, described first driving phase inverter 510 includes the first driving PMOS ap1 and the first drive Dynamic NMOS tube an1.

The grid ap1G of described first driving PMOS ap1 and described first driving NMOS tube an1 Grid an1G be connected, and with described amplify reading circuit 200 outfan OUT be connected, be used for connecing Receive the described voltage signal amplifying reading circuit 200 output；The drain electrode of described first driving PMOS Ap1D is connected with the source electrode an1S of the described first driving NMOS tube an1, and puts with the described second driving Big device 520 is connected, for sending the voltage signal through once anti-phase amplification；Described first driving PMOS The source electrode ap1S of pipe ap1 connects supply voltage Vdd；The drain electrode of described first driving NMOS tube an1 An1D connects earthing power supply Vss；.

Described second driving phase inverter 520 includes the second driving PMOS ap2 and the second driving NMOS Pipe an2.

The grid ap2G of described second driving PMOS ap1 and described second driving NMOS tube an2 Grid an2G be connected, and with described first driving phase inverter 510 be connected, for reception through once anti- The voltage signal mutually amplifying；The drain electrode ap2D of described second driving PMOS and described second driving The source electrode an2S of NMOS tube an2 is connected, and is connected with described trigger 400, for trigger 400 Send the voltage signal amplifying second；The source electrode ap2S of described second driving PMOS ap2 connects electricity Source voltage Vdd；The drain electrode an2D of described second driving NMOS tube an2 connects earthing power supply Vss.

In the present embodiment, described reading phase inverter 210 output voltage V_OUTThrough the described first driving phase inverter After 510 and described second drive phase inverter 520 to amplify, formed and amplify signal V_OUT.amp, it is sent to triggering Device 400, described trigger 400 is according to described amplification signal V_OUT.ampExport corresponding data signal.

To sum up, the present invention passes through setting switch control between described amplification reading circuit input and outfan Circuit processed, controls the described conducting amplified between reading circuit input and outfan and blocks.Reading Before data, by turning on described amplification reading circuit input and outfan, make described amplification reading circuit Input voltage and output voltage are equal, so that described amplification reading circuit is operated in voltage transmission gain Big state, i.e. the small change of input voltage, you can cause the change that output voltage is larger.Therefore when When institute bitline voltage occurs minor variations, described reading amplifying circuit is exportable to make described trigger defeated Go out to represent the data signal of different pieces of information, thus improve the described bit line electricity of described reading amplifying circuit perception The speed of buckling, improves the speed that described sense amplifier reads data in storage unit, improves The performance of memorizer.In the alternative of this case, by arranging second in parallel with described first switch Switch, and after first switch blocks described amplification reading circuit input and outfan, remain on and lead Logical state, so that the described input voltage amplifying reading circuit and output voltage keep equal, it is to avoid When first switch blocks described amplification reading circuit input and outfan, parasitic capacitance is read to described amplification The impact of sense circuit input voltage it is ensured that when reading the data, the described reading circuit input that amplifies Voltage is equal with the voltage of described outfan, thus further increasing described sense amplifier to read data Speed, improve the performance of memory block.

Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention Shield scope should be defined by claim limited range.

Claims

1. a kind of sense amplifier, for reading the data storage in read only memory internal memory storage unit, described spirit Quick amplifier is connected it is characterised in that including with described memory element by bit line：

Pull-up circuit, in order to produce pull-up current；

2. sense amplifier as claimed in claim 1 is it is characterised in that described pull-up circuit includes：

Analog module, is the memory element of " 0 " for analog storage data；

Current mirror module, is connected with described analog module, reads for obtaining simulation from described analog module Electric current, and electric current output pull-up current is read according to described simulation.

3. sense amplifier as claimed in claim 2 is it is characterised in that described analog module includes：

At least one is " 0 " for analog storage data with described memory element identical effective storage unit Memory element；Described effective storage unit is passed through simulation bit line and is connected with described current mirror module all the time.

4. sense amplifier as claimed in claim 3 is it is characterised in that described analog module also includes：

Multiple with memory element identical invalid storage unit, described invalid storage cell distribution has described Around effect memory element.

5. sense amplifier as claimed in claim 2 is it is characterised in that described current mirror module includes：

At least one input metal-oxide-semiconductor and at least one output mos pipe；

Described input metal-oxide-semiconductor includes first end, the second end and control end, the control of described input metal-oxide-semiconductor End processed is used for controlling leading between the first end of described input metal-oxide-semiconductor and the second end of described input metal-oxide-semiconductor Lead to and block；

Described output mos pipe includes first end, the second end and control end, the control of described output mos pipe End processed control conducting between the first end of described output mos pipe and the second end of described output mos pipe and Block；

The described first end of input metal-oxide-semiconductor and the first end of described output mos pipe are used for receiving power supply electricity Pressure；

Second end of described input metal-oxide-semiconductor is connected with the control end of described output mos pipe with control end, and It is connected with described analog module；

Second end of described output mos pipe is connected with described amplification reading circuit, to export described pull-up electricity Stream；

The size of described input metal-oxide-semiconductor becomes integral multiple relation with the size of described output mos pipe.

6. sense amplifier as claimed in claim 5 is it is characterised in that described current mirror module also includes：

At least one input controls metal-oxide-semiconductor, and described input controls the quantity of metal-oxide-semiconductor and described input MOS The quantity of pipe is equal, and when the quantity that described input controls metal-oxide-semiconductor is multiple, the plurality of input controls The size of metal-oxide-semiconductor is all equal；

Described input control metal-oxide-semiconductor include first end, the second end and and control end, described input controls The control end of metal-oxide-semiconductor controls described input to control the first end of metal-oxide-semiconductor and described input to control metal-oxide-semiconductor The second end between conducting and block；

Described input controls the first end of metal-oxide-semiconductor to receive supply voltage；

Described input controls the second end of metal-oxide-semiconductor and the first end of described input metal-oxide-semiconductor to correspond even Connect；

Described input controls the control end receives input control signal of metal-oxide-semiconductor, described input control signal control System at least one input described controls the conducting of metal-oxide-semiconductor or blocks, to control the input metal-oxide-semiconductor of access Quantity.

7. sense amplifier as claimed in claim 5 is it is characterised in that described current mirror module also includes：

At least one output control metal-oxide-semiconductor, the quantity of described output control metal-oxide-semiconductor and described output mos The quantity of pipe is equal, when the quantity of described output control metal-oxide-semiconductor is multiple, the plurality of output control The size of metal-oxide-semiconductor is all equal；

Described output control metal-oxide-semiconductor include first end, the second end and and control end, described output control The control end of metal-oxide-semiconductor controls the first end of described output control metal-oxide-semiconductor and described output control metal-oxide-semiconductor The second end between conducting and block；

The first end of described output control metal-oxide-semiconductor receives supply voltage；

Second end of described output control metal-oxide-semiconductor is corresponded even with the first end of described output mos pipe Connect；

The control end of described output control metal-oxide-semiconductor receives output control signal, described output control signal control Make the conducting of at least one output control metal-oxide-semiconductor described or block, to control the output mos pipe of access Quantity.

8. sense amplifier as claimed in claim 7 is it is characterised in that described current mirror module also includes：

At least one input controls metal-oxide-semiconductor；Described input controls the size of metal-oxide-semiconductor and described output control The size of metal-oxide-semiconductor becomes integral multiple relation.

9. sense amplifier as claimed in claim 1 is it is characterised in that described amplification reading circuit includes：

Read phase inverter, the input of described reading phase inverter is connected with described memory element by bit line, Outfan is coupled with described trigger, according to the change of electric current on described pull-up current and bit line, senses The change of voltage on bit line, and stored in the change output of voltage and memory element on bit line by amplifying The related output voltage of data.

10. sense amplifier as claimed in claim 1 is it is characterised in that described on-off circuit includes：

First switch, is connected between the described input amplifying reading circuit and outfan, for controlling The described conducting amplified between the input of reading circuit and outfan and blocking.

11. sense amplifiers as claimed in claim 10 it is characterised in that read data when, described bit line It is precharged to high potential；Described first switch is used for closing after bit line precharge.

12. sense amplifiers as claimed in claim 10 are it is characterised in that described on-off circuit also includes：

Second switch, in parallel with described first switch, be connected to described amplify reading circuit input and Between outfan, with the cooperation of described first switch, control described amplification reading circuit input and outfan Between conducting and block；

The size being smaller in size than described first switch of described second switch.

13. sense amplifiers as claimed in claim 12 it is characterised in that read data when, described bit line It is precharged to high potential；

Described first switch is used for the first moment closing after bit line precharge；

Described second switch is used for the second moment closing after bit line precharge, and described second moment is later than institute Stated for the first moment.

14. sense amplifiers as claimed in claim 10 are it is characterised in that described first switch includes at least one Individual first switch metal-oxide-semiconductor；

Described first switch metal-oxide-semiconductor includes first end, the second end and control end, described first switch MOS The control end of pipe controls the first end of described first switch metal-oxide-semiconductor and the second of described first switch metal-oxide-semiconductor Conducting between end and blocking；

The first end of described first switch metal-oxide-semiconductor is connected with the described input amplifying reading circuit；

Second end of described first switch metal-oxide-semiconductor is connected with the described outfan amplifying reading circuit；

The control end of described first switch metal-oxide-semiconductor receives first switch control signal, according to first switch control Signal processed is realized the conducting of described first switch metal-oxide-semiconductor or is blocked, to control described amplification reading circuit defeated Enter the conducting between end and outfan and block.

15. sense amplifiers as claimed in claim 12 are it is characterised in that described second switch includes at least one Individual second switch metal-oxide-semiconductor；

Described second switch metal-oxide-semiconductor includes first end, the second end and control end, described second switch MOS The control end of pipe controls the first end of described second switch metal-oxide-semiconductor and the second of described first switch metal-oxide-semiconductor Conducting between end and blocking；

The first end of described second switch metal-oxide-semiconductor is connected with the described input amplifying reading circuit；

Second end of described second switch metal-oxide-semiconductor is connected with the described outfan amplifying reading circuit；

The control end of described second switch metal-oxide-semiconductor receives second switch control signal, according to second switch control Signal processed is realized the conducting of described second switch metal-oxide-semiconductor and is blocked, to control described amplification reading circuit defeated Enter the conducting between end and outfan and block.

16. sense amplifiers as claimed in claim 1 are it is characterised in that described sense amplifier also includes：

Drive amplification circuit, for amplify described amplify reading circuit output with memory element in stored The related output voltage of data.

17. sense amplifiers as claimed in claim 16 are it is characterised in that described drive amplification circuit includes：

At least one drives phase inverter, and described driving phase inverter is connected to described amplification reading circuit and triggering Between device.

18. sense amplifiers as claimed in claim 1 are it is characterised in that described sense amplifier also includes：

Control circuit, for producing control signal to control the conducting of described on-off circuit and to block.

19. sense amplifiers as claimed in claim 10 are it is characterised in that described sense amplifier also includes：

Control circuit, described control circuit includes the first control circuit being connected with described first switch, uses In producing first switch control signal, to control the conducting of described first switch or to block.

20. sense amplifiers as claimed in claim 12 are it is characterised in that described sense amplifier also includes：

Control circuit, described control circuit includes：

The first control circuit being connected with described first switch, for producing first switch control signal, with Control the conducting of described first switch or block；

The second control circuit being connected with described second switch, for producing second switch control signal, with Control the conducting of described second switch or block.