CN106484583A - A kind of UPI protocol model link layer module checking system based on UVM verification platform - Google Patents
A kind of UPI protocol model link layer module checking system based on UVM verification platform Download PDFInfo
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Abstract
The invention discloses a kind of UPI protocol model link layer module checking system based on UVM verification platform, including UVM base class file, for carrying out UVM checking to link layer module；The parameter setting class file integrated with UVM base class file, for setting corresponding to the UVM environmental interior variable parameter of link layer module and the constrained parameters of link layer module.The present invention enables the link layer module application UVM verification platform in UPI protocol model to be verified, it is ensured that the verification efficiency of link layer module by increasing parameter setting class file.
Description
Technical field
The present invention relates to IC verification technique field, more particularly to a kind of UPI protocol model chain based on UVM verification platform
Road floor module verification system.
Background technology
With the increase of chip-scale, verifying in chip design becomes the maximum work of expense in flow process, accounts for and entirely sets
The ratio in meter cycle is increasing.The workload of checking has accounted for 70% to the 80% of whole SOC research and development, therefore improves chip
The efficiency of checking has become most important.UVM (Universal Verification Methodology, generic validation method
Learn), originate from OVM, be to be combined the authentication that a new generation for releasing is ripe, increase income by Cadence, Mentor and Synopsys
The science of law, it employ optimal validation framework and go to realize Coverage- Driven checking, effectively combine test randomly generate, self-test
The features such as platform and randomization are constrained.
At present, the most basic purpose of the checking of UVM verification platform is to test the correctness of DUT (equipment under test), and which is most
The method for often using is exactly to apply different excitations to DUT, and observes the output result of DUT, by this output result with identical
The lower normal data for producing of excitation is compared, and thus judges the correctness of DUT.
In UPI protocol verification model, link layer module is its important part, main be responsible for connection physical layer with
Protocol layer, is responsible for the scheduling of data, distributes.And link layer module can not be verified using UVM platform that what which adopted tests at present
For card mode compares UVM, verification efficiency is low.
Therefore, how a kind of UPI agreement mould based on UVM verification platform that link layer module can be verified is provided
Type link layer module checking system is the problem that those skilled in the art need to solve at present.
Content of the invention
It is an object of the invention to provide a kind of UPI protocol model link layer module checking system based on UVM verification platform,
The link layer module application UVM verification platform in UPI protocol model is enable to be verified, verification efficiency is high.
For solving above-mentioned technical problem, the invention provides a kind of UPI protocol model link layer based on UVM verification platform
Module verification system, including：
UVM base class file, for carrying out UVM checking to link layer module；
The parameter setting class file integrated with the UVM base class file, for setting corresponding to the link layer module
UVM environmental interior variable parameter and the constrained parameters of the link layer module.
Preferably, the UVM base class file includes：
Excitation generation module, the parameters generation set for receiving and according to the parameter setting module is different to swash
Signal is encouraged, and the pumping signal is exported to the link layer module；
First monitoring module, makees for monitoring the pumping signal of the excitation generation module output and sending to contrast module
On the basis of signal；
Second monitoring module, for monitoring the consequential signal of link layer module output and sending to the contrast mould
Block；
The contrast module, for the consequential signal is compared with the reference signal, obtains comparative result.
Preferably, the UVM base class file also includes：
There is module in sequence, for starting the sequence of itself setting, receive and set according to the parameter setting module
Parameters obtain different item data units from the sequence；
Accordingly, described excitation generation module be used for by the Transaction Information unit according to preset rules be converted to corresponding to
The pumping signal of the link layer module.
Preferably, the UVM base class file also includes：
Function coverage analysis module, for receiving the consequential signal of second monitoring module monitoring, from the result
The functional coverage point information defined in default coverage rate group is gathered in signal, according to the functional coverage point information minute of collection
Analysis obtains the function coverage of the link layer module.
Preferably, first monitoring module is additionally operable to monitor the consequential signal of link layer module output；
The UVM base class file also includes：
Function coverage analysis module, for receiving the consequential signal of first monitoring module monitoring, from the result
The functional coverage point information defined in default coverage rate group is gathered in signal, according to the functional coverage point information minute of collection
Analysis obtains the function coverage of the link layer module.
Preferably, the function coverage analysis module is additionally operable to：
The code coverage point information defined in the default coverage rate group, foundation is gathered from the consequential signal for receiving
The code coverage point information analysis of collection obtains the code coverage of the link layer module.
The invention provides a kind of UPI protocol model link layer module checking system based on UVM verification platform, the system
Inside be provided with parameter setting class file, such file configuration have UVM environmental interior variable parameter corresponding with link layer module with
And constrained parameters, then the UVM base class file in parameter setting class file and UVM verification platform is carried out integrated, it is seen then that this is
System enables the link layer module application UVM verification platform in UPI protocol model to be verified, it is ensured that the testing of link layer module
Card efficiency.
Description of the drawings
For the technical scheme being illustrated more clearly that in the embodiment of the present invention, below will be to institute in prior art and embodiment
The accompanying drawing for using is needed to be briefly described, it should be apparent that, drawings in the following description are only some enforcements of the present invention
Example, for those of ordinary skill in the art, on the premise of not paying creative work, can also obtain according to these accompanying drawings
Obtain other accompanying drawings.
A kind of UPI protocol model link layer module checking system based on UVM verification platform that Fig. 1 is provided for the present invention
Structural representation；
UPI protocol model link layer module checking system of the another kind that Fig. 2 is provided for the present invention based on UVM verification platform
Structural representation；
UPI protocol model link layer module checking system of the another kind that Fig. 3 is provided for the present invention based on UVM verification platform
Structural representation；
UPI protocol model link layer module checking system of the another kind that Fig. 4 is provided for the present invention based on UVM verification platform
Structural representation；
UPI protocol model link layer module checking system of the another kind that Fig. 5 is provided for the present invention based on UVM verification platform
Structural representation.
Specific embodiment
The core of the present invention is to provide a kind of UPI protocol model link layer module checking system based on UVM verification platform,
The link layer module application UVM verification platform in UPI protocol model is enable to be verified, verification efficiency is high.
Purpose, technical scheme and advantage for making the embodiment of the present invention is clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
The a part of embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art
The every other embodiment obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.
The invention provides a kind of UPI protocol model link layer module checking system based on UVM verification platform, including：
UVM base class file, for carrying out UVM checking to link layer module；
The parameter setting class file 1 integrated with UVM base class file, for setting the UVM environment corresponding to link layer module
Built-in variable parameter and the constrained parameters of link layer module.
It is understood that UPI protocol model link layer includes two modules, SI and PD module, two of which SI pair
Answer PD, a SI to be responsible for for physical layer FLIT message being combined into, PD is sent to, while the message from protocol layer is combined into
FLIT, is sent to physical layer.Link layer can produce seven kinds of different type of messages, i.e. REQ, SNP, WB, NCB, NCS, RSP and band
The response request RSPD of Data, is sent to protocol layer by seven virtual channels respectively.PD module is responsible for all types message
By link layer to protocol layer, by protocol layer to link layer scheduled transmission.Because two SI correspond to PD, either by SI to
PD, or by PD to SI, be not to correspond, need to be scheduling, on the premise of without particular/special requirement, still using rotation
Arbitration is transmitted to message with this.
In addition, in UVM verification method, the various pieces in UVM verification platform are all based on a System
The class (or class file) of Verilog come realized, as above-mentioned UVM base class file uvm_component, UVM verification platform
UVM base class file is pre-defined, the UVM base class file includes some functions and task, then each in UVM verification platform
Individual part etc. will be derived from from this class file, and completes the function of itself according to these functions and task.In addition, should
Member variable can be included in UVM base class file, for controlling the behavior of its various pieces for deriving from.
Specifically, shown in Figure 1, a kind of UPI protocol model based on UVM verification platform that Fig. 1 is provided for the present invention
The structural representation of link layer module checking system；Here UVM base class file includes：
Excitation generation module 21, the parameters set for receiving and according to parameter setting module generate different excitations
Signal, and pumping signal is exported to link layer module；
First monitoring module 22, for monitoring the pumping signal of the excitation output of generation module 21 and sending to contrast module 24
As reference signal；
Second monitoring module 23, for monitoring the consequential signal of link layer module output and sending to contrast module 24；
Contrast module 24, for consequential signal is compared with reference signal, obtains comparative result.
It is understood that above modules are UVM base class file fork class out.
In addition, 24 synchronous collection consequential signal of contrast module is compared with corresponding reference signal, and also for right
Comparative result is printed, and certainly, can not also be printed comparative result, but comparative result be sent to display device and is shown
Show, the present invention is not construed as limiting to this.
Preferably, UVM base class file also includes：
There is module 25 in sequence, for starting the sequence of itself setting, received and set according to parameter setting module is each
Individual parameter obtains different item data units from sequence；
Accordingly, excitation generation module 21 is used for being converted to corresponding to link layer Transaction Information unit according to preset rules
The pumping signal of module.
It is understood that by increase sequence occur module 25, for link layer module is entered the data of row energization by
Sequence occurs module 25 to produce, and encourages generation module 21 to be only used for the conversion of data, and this function is divided and causes modules
Function becomes apparent from, it is easier to use.Wherein, preset rules here include default agreement and sequential relationship, specifically
Here default agreement is link layer interface agreement, and the pumping signal for being converted to is specially port signal.But the present invention is not limited
Determine the particular content of preset rules.
Wherein, the selection of sequence occurs module 25 to determine with scheduling by sequence, typically sets sequence in UVM environment and sends out
Acquiescence default_sequence of raw module 25, you can load automatically acquiescence default_ after UVM verification platform starts
The random data bag that sequence is produced.
In addition, the pumping signal for collecting and consequential signal are being sent out by the first monitoring module 22 with the second monitoring module 23
When contrast module 24 is delivered to, need to convert a signal into Transaction Information unit and be transmitted again.
Preferably, UVM base class file also includes：
Function coverage analysis module 26, for receiving the consequential signal that the second monitoring module 23 is monitored, from consequential signal
The middle functional coverage point information gathered defined in default coverage rate group, obtains chain according to the functional coverage point information analysis of collection
The function coverage of road floor module.In addition, also include multiple proxy programs in UVM verification platform, different proxy program pair
Should there are different physical interface agreements, physical interface agreement defines the DIF of data and mode, proxy program is by swashing
Encourage generation module 21 and monitoring module to realize these contents of interface protocol.Wherein, in the above-described embodiments, there is mould in sequence
Block 25, excitation generation module 21, the first monitoring module 22 are located in main proxy program, function coverage analysis module 26, second
Monitoring module 23 is located at from proxy program.Shown in Figure 2, Fig. 2 is based on UVM verification platform for the another kind that the present invention is provided
UPI protocol model link layer module checking system structural representation.
In another kind of embodiment, the first monitoring module 22 is additionally operable to monitor the consequential signal of link layer module output；
UVM base class file also includes：
Function coverage analysis module 26, for receiving the consequential signal that the first monitoring module 22 is monitored, from consequential signal
The middle functional coverage point information gathered defined in default coverage rate group, obtains chain according to the functional coverage point information analysis of collection
The function coverage of road floor module.
It is understood that there is several to need the function point information of collection (including each defined in default coverage rate group
Plant type of message and data message etc.), after function coverage analysis module 26 receives consequential signal, i.e., according to covering for setting
Gathering corresponding function point from consequential signal, then the function to collecting is clicked through function point information defined in lid rate group
Row analysis (for example, determines that the function point for collecting accounts for the ratio of repertoire point quantity, and compares each function of collecting
Normal data in the function point information of the data of point and definition etc.), obtain the function coverage of link layer module.Wherein, this
In function coverage embodies is that the result of link layer module reality output accounts for the ratio of the result that export, cover from function
Actual realization degree of the link layer module to function which should be realized can be reflected in lid rate.Certainly, the present invention is not limited
The information type included in function point information and the analysis mode of the function point to collecting.
In this embodiment, there is module 25, excitation generation module 21, the first monitoring module 22, function coverage in sequence
Analysis module 26 is located in main proxy program, and the second monitoring module 23 is located at from proxy program.Shown in Figure 3, Fig. 3 is this
Structural representation of the another kind that invention is provided based on the UPI protocol model link layer module checking system of UVM verification platform.
Preferably, function coverage analysis module 26 is additionally operable to：
The code coverage point information defined in default coverage rate group is gathered from the consequential signal for receiving, according to collection
Code coverage point information analysis obtain the code coverage of link layer module.
Several code point information for needing collection are there is also defined in i.e. default coverage rate group, by arriving actual acquisition
Code point with definition code point information in data compare, will be understood that what link layer module should be completed to which
Code actually accomplish degree (can reflect any partial code completed, and which partial code is not completed), the reality
Performance level is code coverage.In addition, code here refers to the operation code arranged in link layer module.Certainly,
The information type that the present invention does not include in restricted code point information and the analysis mode of the code point to collecting.
Further, the function coverage for obtaining and code coverage can also be carried out beating by function coverage analysis module 26
Print, certainly, can not also print, but function coverage and code coverage be sent to display device and is shown, the present invention
This is not construed as limiting.
In addition, UVM base class file may also include a model module 27, the model module 27 receives excitation generation module 21
The pumping signal of output, and output reference signal is to contrast module 24；Now, if function coverage analysis module 26 receives second
The signal of monitoring module 23, then can be not provided with the first monitoring module 22 in UVM base class file；If function coverage analysis module 26
The signal of the first monitoring module 22 is received, then the first monitoring module 22 is set, but the first monitoring module 22 need not receive excitation
The signal that generation module 21 is exported is also without outputing signal to contrast module 24.Certainly, preferred version these are only, if set
Put 27 present invention of model module not limit.Referring to shown in Fig. 4 and Fig. 5, the another kind that Fig. 4 is provided for the present invention is tested based on UVM
The structural representation of the UPI protocol model link layer module checking system of card platform；The another kind that Fig. 5 is provided for the present invention is based on
The structural representation of the UPI protocol model link layer module checking system of UVM verification platform.
The invention provides a kind of UPI protocol model link layer module checking system based on UVM verification platform, the system
Inside be provided with parameter setting class file, such file configuration have UVM environmental interior variable parameter corresponding with link layer module with
And constrained parameters, then the UVM base class file in parameter setting class file and UVM verification platform is carried out integrated, it is seen then that this is
System enables the link layer module application UVM verification platform in UPI protocol model to be verified, it is ensured that the testing of link layer module
Card efficiency.
It should be noted that in this manual, such as first and second or the like relational terms are used merely to one
Individual entity or operation are made a distinction with another entity or operation, and are not necessarily required or implied these entities or operate it
Between exist any this actual relation or order.And, term " including ", "comprising" or its any other variant are intended to
Cover including for nonexcludability, so that a series of process including key elements, method, article or equipment not only include those
Key element, but also other key elements including being not expressly set out, or also include for this process, method, article or set
Standby intrinsic key element.In the absence of more restrictions, the key element for being limited by sentence "including a ...", it is not excluded that
Also there is other identical element in process, method, article or the equipment for including the key element.
The foregoing description of the disclosed embodiments, enables professional and technical personnel in the field to realize or uses the present invention.
Multiple modifications to these embodiments will be apparent for those skilled in the art, as defined herein
General Principle can be realized without departing from the spirit or scope of the present invention in other embodiments.Therefore, the present invention
The embodiments shown herein is not intended to be limited to, and is to fit to and principles disclosed herein and features of novelty phase one
The most wide scope for causing.
Claims (6)
1. a kind of UPI protocol model link layer module checking system based on UVM verification platform, it is characterised in that include：
UVM base class file, for carrying out UVM checking to link layer module；
The parameter setting class file integrated with the UVM base class file, for setting the UVM ring corresponding to the link layer module
Domestic portion's variable parameter and the constrained parameters of the link layer module.
2. system according to claim 1, it is characterised in that the UVM base class file includes：
Excitation generation module, the parameters set for receiving and according to the parameter setting module generate different excitation letters
Number, and the pumping signal is exported to the link layer module；
First monitoring module, for monitoring the pumping signal of the excitation generation module output and sending to contrast module as base
Calibration signal；
Second monitoring module, for monitoring the consequential signal of link layer module output and sending to the contrast module；
The contrast module, for the consequential signal is compared with the reference signal, obtains comparative result.
3. system according to claim 2, it is characterised in that the UVM base class file also includes：
Sequence occur module, for start itself setting sequence, receive and according to the parameter setting module set each
Parameter obtains different item data units from the sequence；
Accordingly, the excitation generation module is used for being converted to corresponding to described the Transaction Information unit according to preset rules
The pumping signal of link layer module.
4. system according to claim 3, it is characterised in that the UVM base class file also includes：
Function coverage analysis module, for receiving the consequential signal of second monitoring module monitoring, from the consequential signal
The middle functional coverage point information gathered defined in default coverage rate group, obtains according to the functional coverage point information analysis of collection
Function coverage to the link layer module.
5. system according to claim 3, it is characterised in that first monitoring module is additionally operable to monitor the link layer
The consequential signal of module output；
The UVM base class file also includes：
Function coverage analysis module, for receiving the consequential signal of first monitoring module monitoring, from the consequential signal
The middle functional coverage point information gathered defined in default coverage rate group, obtains according to the functional coverage point information analysis of collection
Function coverage to the link layer module.
6. the system according to claim 4 or 5, it is characterised in that the function coverage analysis module is additionally operable to：
The code coverage point information defined in the default coverage rate group is gathered from the consequential signal for receiving, according to collection
The code coverage point information analysis obtain the code coverage of the link layer module.
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| CN108196976A (en) * | 2017-12-28 | 2018-06-22 | 湖南国科微电子股份有限公司 | A kind of LDPC simulation and verification platforms, verification method |
| CN109492269A (en) * | 2018-10-22 | 2019-03-19 | 北方电子研究院安徽有限公司 | A kind of digital fuse timing circuit verification platform based on UVM |
| CN109726476A (en) * | 2018-12-29 | 2019-05-07 | 杭州迪普科技股份有限公司 | Verification method and device based on UVM verification platform |
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Application publication date: 20170308 |