CN106470046A - A kind of utilization 4b/6b technology and the method with double pseudo-random code spread-spectrum - Google Patents
A kind of utilization 4b/6b technology and the method with double pseudo-random code spread-spectrum Download PDFInfo
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Abstract
A kind of utilization 4b/6b technology and the method with double pseudo-random code spread-spectrum, the invention discloses the binary spreading code of two a length of N of a utilization, it spreads into the spectrum spreading method of 10N bit binary code the dual code of 16 bits, and it comprises the following steps：A) front 6 bits of use 16 bit binary codes to be spread generate the 10 bit binary codes that containing 50 and 51；B) replace 0 and 1 in the rear 10 bit binary codes of use 16 bit binary codes to be spread with the binary spreading code of two a length of N respectively, obtain the dual code of a 10N bit；C) each bit in the 10 bit binary codes that step a is generated repeats n times, and the 10N bit binary code being obtained with step b after obtaining the dual code of a 10N bit is done XOR by turn and obtains the dual code that 10N bit binary code is exactly that disclosed spectrum spreading method generates.
Description
Technical field
Radio spread spectrum communication.
Technical background
In conventional wireless spread spectrum communication, spread with double pseudo noise codes, a baseband signalling only transmits 1 bit data.
The invention discloses a new method being spread with double pseudo noise codes.The channel that profit is set up in this way, using 16 bit numbers
During according to form, a baseband signalling can transmit 1.6 bit datas.That is, we can bring up to original 1.6 times data rate.
Content of the invention
The invention discloses a kind of 4b/6b coded method.This 4b/6b coded method weaves into 6 bit binary codes 4 bit binary codes, and this 6
Bit binary code contains 30 and 31.We are designated as abcd 4 bit binary codes to be encoded, with symbol-note inverse symbol.Disclosed
Method comprise the following steps：
A) as d=1, abcd is weaved into abc；
B) as cd=10, abcd is weaved into abb；
C) as cd=00, abcd is weaved into aab.
The invention discloses the construction of a 4b/6b encoder.This 4b/6b encoder weaves into 6 bit binary codes 4 bit binary codes, and this 6
Bit binary code contains 30 and 31.This 4b/6b encoder is made up of following equipment：
A) a 4b/8b Manchester encoder.The input of this 4b/8b Manchester encoder is the input of this 4b/6b encoder, its handle
Input in described 4 bit binary codes 1 and 0 and be substituted for 10 and 01 respectively and obtain 8 bit binary codes；
B) modulo 2 adder, three and door and five XOR gates.6 of this 4b/6b encoder output are by the of Manchester encoder
One output, the output of second XOR gate, the output of the 3rd XOR gate, the output of the 4th XOR gate, the 5th XOR gate
The output composition of output and modulo 2 adder.First with door two inputs be respectively the 6th of 4b/8b Manchester encoder defeated
Go out and export with the 8th.Two inputs of first XOR gate are the 2nd of 4b/8b Manchester encoder respectively and export and the 3rd
Output.Second with door two inputs be respectively first with door export and first XOR gate output.3rd with door two
Individual input is that the 3rd output of 4b/8b Manchester encoder exports with the 8th respectively.Two inputs of second XOR gate are respectively
It is the 2nd of 4b/8b Manchester encoder output and first output with door.Two inputs of the 3rd XOR gate are respectively
3rd output of 4b/8b Manchester encoder and second output with door.Two inputs of the 4th XOR gate are 4b/8b respectively
7th output of Manchester encoder and the output of the 3rd XOR gate.Two inputs of the 5th XOR gate are that 4b/8b is graceful respectively
5th output of Che Site encoder and the 3rd output with door.Modulo 2 adder has three input ports, its three inputs point
It is not the output of the 7th output, first output with door and the 5th XOR gate of 4b/8b Manchester encoder.
The invention discloses a kind of 4b/6b interpretation method.This 4b/6b interpretation method is translated into 4 bit binary codes 6 bit binary codes.We
6 bit binary codes to be decoded are designated as abcdef.Disclosed interpretation method comprises the following steps：
A) as c ≠ d, abcdef is translated into acd1；
B) as e=f, abcdef is translated into ac10；
C) as a=b, abcdef is translated into ae00.
The invention discloses the construction of a 4b/6b decoder.This 4b/6b decoder is translated into 4 bit binary codes 6 bit binary codes, and it has 6
Individual input port and 4 output ports.This 4b/6b decoder by two not gates, three form with door and five XOR gates.This 4b/6b translates
4 of device outputs of code are different by first input of this 4b/6b decoder, the output of the 4th XOR gate, the output of the 5th XOR gate and the 3rd
The output composition of OR gate.Two inputs of first XOR gate are that first input of this 4b/6b decoder inputs with second respectively.Second different
Two inputs of OR gate are that the 3rd input of this 4b/6b decoder inputs with the 5th respectively.The input of first not gate is first XOR gate
Output.First two input with door is the output of second XOR gate and the output of first not gate respectively.Two inputs of the 3rd XOR gate
It is the 3rd of this 4b/6b decoder input and the 4th input respectively.The input of second not gate is the output of the 3rd XOR gate.Second with
Two inputs of door are the 5th input of this 4b/6b decoder and the output of the 3rd XOR gate respectively.3rd two inputs with door are respectively
The output of first XOR gate and the output of second not gate.Two inputs of the 4th XOR gate are the 3rd input of this 4b/6b decoder respectively
With first output with door.Two inputs of the 5th XOR gate are second output with door and the 3rd output with door respectively.
The invention discloses a kind of spectrum spreading method.This spectrum spreading method depends on the binary spreading code of a length of N of given two.1 in each spreading code
Number 1 more than 0 number.This spectrum spreading method spreads into 10N bit binary code 16 bit binary codes, and it comprises the following steps：
A) 16 bit binary codes to be spread are truncated into the dual code of 6 bit binary codes and 10 bits；
B) with a fixing algorithm, 6 bit binary codes in step a are weaved into 10 bit binary codes, this 10 bit binary code contains 50
With 51.This fixing algorithm can be merged with a 2b/4b Manchester encoding method and 4b/6b coded method disclosed by the invention
Composition；
C) each bit of the 10 bit binary codes that step b is obtained repeats n times, obtains a 10N bit binary code；
D) with 0 and 1 in 10 bit binary codes in binary spreading code difference replacement step a of two given a length of N, obtain a 10N
The dual code of bit；
E) two 10N bit binary codes that step c and step d are obtained do XOR by bit, and the 10N bit binary code obtaining is exactly this
The dual code that spectrum spreading method generates.
The invention discloses the construction of a frequency multiplier.This frequency multiplier depends on given positive integer parameter N, and it expands 16 bit binary codes
Frequency is a 10N bit binary code.Disclosed frequency multiplier is made up of following equipment；
A) decomposer.The input of this decomposer is the input of this frequency multiplier, and it has two output end door.First outfan of this decomposer
Mouth parallel output inputs foremost 6 bit of 16 bit binary codes of decomposer.Second output port of this decomposer is defeated by bit
Go out to input last 10 bits of 16 bit binary codes of decomposer；
B) a 6b/10b encoder.The input of this 6b/10b encoder is the output of first output port of decomposer.This 6b/10b
6 bit binary codes of parallel input are weaved into 10 bit binary codes, this 10 bit binary code contains 50 and 51.This 6b/10b
Encoder can merge composition with a 2b/4b Manchester encoder and 4b/6b encoder described in a claim 2；
C) an initial state selector and a spread spectrum code generator.The input of initial state selector is the output of second output port of decomposer.Initial state is selected
Select device often read in a bit just export an initial state give spread spectrum code generator.Spread spectrum code generator exports spreading code, spread spectrum according to its initial state
In code, 1 number is 1 more than 0 number；
D) chip-rate clock.This chip-rate clock make spread code generator by bit output rate be 6b/10b encoder by
N times of bit output rate；
E) XOR gate.This XOR gate does XOR spread spectrum code generator by bit output and exporting by bit of 6b/10b encoder
The output of after-cost frequency multiplier.
The invention discloses the construction of a transmitter.This transmitter is made up of following equipment：
A) frequency multiplier.The input of this frequency multiplier is exactly the input of this transmitter, it input data spread spectrum become some spreading codes and it
Radix-minus-one complement composition sequence.In spreading code, 1 number is 1 more than 0 number.This frequency multiplier can be frequency multiplier disclosed by the invention；
B) a Chip Waveform manipulator.This Chip Waveform manipulator is modulated into corresponding waveform the output of frequency multiplier；
C) agitator.This agitator exports the cosine carrier of this transmitter needs；
D) phase shifter.The carrier wave that this phase shifter exports agitator is converted into sinusoidal carrier；
E) two multipliers.The waveform that this two multipliers export Chip Waveform manipulator carrier multiplication and the phase shifter with agitator output respectively
The carrier multiplication of output；
F) adder.This adder is added the output of two multipliers；
G) broadband filter.This broadband filter filters out the out-of-band frequency of the waveform of adder output, and its output is exactly this transmitter
Transmission signal.
The invention discloses a kind of despreading method.This despreading method depends on the binary spreading code of a length of N of given two.In spreading code 1
1 more than the number than 0 for the number.This despreading method de-spreads into 16 bit binary codes the sequence of real numbers of a length of 10N, and it comprises the following steps：
A) sequence of real numbers of a length of 10N to be de-spread is cut and is divided into the 10 sections long sequence of real numbers for N, every segment length be N sequence of real numbers change into
There is in the fixed spreading code of two a length of N and their radix-minus-one complement the dual code of maximum correlation coefficient therewith, thus obtain one by 10 sections
The dual code of a length of 10N that the dual code of a length of N is constituted.Here, the phase relation of the dual code of the sequence of real numbers of a length of N and a length of N
Number be this length of N sequence of real numbers and the bipolar code wise multiplication of the dual code of this length of N after sue for peace and obtain；
B) dual code being N segment length every in the dual code of a length of 10N being divided into 10 sections in step a changes the parity of their Hamming weight into,
Obtain 10 bit binary codes；
C) it is translated into 6 bit binary codes with the 10 bit binary codes that the decoding algorithm of a fixation obtains step b.This decoding algorithm can be by one
Individual 2b/4b Manchester decoding algorithm and interpretation method disclosed by the invention merge composition；
D) set up the one-to-one corresponding between the given binary spreading code of two a length of N and 0,1, according to this one-to-one corresponding dividing in step a
Become the dual code that every segment length in 10 sections of the dual code of a length of 10N is N or directly change 0 and 1 into, or after changing their radix-minus-one complement into
Change 0 and 1 again into, thus obtain 10 bit binary codes；
E) the 10 bit binary codes that the step c 6 bit binary codes that obtain of decoding and step d are obtained are merged into the dual code of 16 bits and make
The code obtaining for this despreading method.
The invention discloses the construction of sequence despreaders.This sequence despreaders depends on given positive integer parameter N, and it is a length of 10N
Sequence of real numbers de-spread into 16 bit binary codes.Disclosed sequence despreaders are made up of following equipment：
A) a spread spectrum code generator.This spread spectrum code generator has two output ports, the binary spreading code of their two a length of N of synchronism output,
In each spreading code, 1 number is 1 more than 0 number；
B) lock unit.This lock unit controls described spread spectrum code generator；
C) two correlators.This two correlators have two input ports, and their first input port continuously reads input this sequence solution every time
Expand the N position of the sequence of real numbers of a length of 10N of device.Second input of this two correlators is two outputs of spread spectrum code generator respectively.
The correlation coefficient of their two list entries of output of each correlator.Here, the correlation coefficient of two list entries is first input
Sue for peace after sequence and the bipolar sequence wise multiplication of second list entries and obtain；
D) two decision devices.This two decision devices have two input ports, and their two inputs are all the output of two correlators.Sentence for first
Certainly device exports the true value of proposition " in two correlation coefficienies being inputted, the absolute value of first is larger ".Second decision device exports proposition " institute
Input two dependency numbers in maximum absolute value be positive number " true value；
E) a 6b/10b decoder.This 6b/10b decoder exports into row decoding continuous 10 of second decision device, obtains one 6
Bit binary code.This 6b/10b decoder can be a 2b/4b manchester decoder and 4b/6b decoder disclosed by the invention
Merge composition；
F) combiner.6 bit binary codes that this combiner exports 6b/10b decoder and 10 ratios of the continuous output of first decision device
Spy is merged into 16 bit binary codes as the output of this sequence despreaders.
The invention discloses the construction of a narrow-band receiver, it is made up of following equipment：
A) radio-frequency front-end；
B) agitator.This agitator exports the cosine carrier used by this transmitter；
C) lock unit.This lock unit controls agitator；
D) phase shifter.The carrier wave that this phase shifter exports agitator is converted into sinusoidal carrier；
E) two multipliers.The waveform that this two multipliers export radio-frequency front-end is just exported with the cosine carrier of agitator output and phase shifter respectively
String carrier multiplication；
F) adder.The waveform adder that this adder exports described two multipliers；
G) an integration sampling device.The waveform segments that this integration sampling device exports to described adder duration integration as shared by 1 bit spreading code；
H) sequence despreaders.This sequence despreaders carries out de-spreading the output obtaining this narrow-band receiver to the output of integration sampling device.This sequence
Row despreader can be sequence despreaders disclosed by the invention.
The invention discloses a kind of despreading method.This despreading method depends on binary spreading code and one a length of N of transmission of a length of N of given two
The duration T shared by binary spreading code.In this two spreading codes, 1 number is 1 more than 0 number.This despreading method is the ripple of duration 10T
Shape de-spreads into 16 bit binary codes, and it comprises the following steps：
A) spreading code of two given a length of N is modulated into respectively the rectangular pulse waveform of two cycle T, duration 10T；
B) waveform of duration 10T to be de-spread is multiplied with two cycle T of step a, the rectangular pulse waveform of duration 10T respectively, obtains two
The waveform of duration 10T；
The waveform segments of the two duration 10T c) step b being obtained are integrated by duration T, obtain the sequence of real numbers of two a length of 10；
D) successively to i from 1 to 10, take the true value of proposition " in i-th of two sequences being obtained by step c, absolute value is larger is positive number ",
Thus obtain the binary sequence of a length of 10；
E) it is translated into 6 bit binary codes with 10 bits that the decoding algorithm of a fixation obtains step d.This decoding algorithm can be by a 2b/4b
Manchester decoding algorithm and interpretation method disclosed by the invention merge composition；
F) successively to i from 1 to 10, take the true value of proposition " in i-th of two sequences being obtained by step c, the absolute value of first is larger ",
Thus obtain the binary sequence of a length of 10；
G) a length of 10 binary sequence that the step e 6 bit binary codes that obtain of decoding and step f are obtained is merged into 16 bit binary codes and makees
The code obtaining for this despreading method.
The invention discloses the construction of a waveform despreader.This waveform despreader depends on given positive integer parameter N and transmission one long
Duration T shared by the spreading code of N.This waveform despreader de-spreads into 16 bit binary codes the waveform of duration 10T, and it is by following equipment group
Become：
A) a frequency spreading wave maker.This frequency spreading wave maker has two output ports, and the binary of their two a length of N of synchronism output expands
The rectangular pulse waveform of frequency code.This two rectangular pulse waveform duration 10T, cycle are T；
B) lock unit.This lock unit controls frequency spreading wave maker；
C) two multipliers.This two multipliers the waveform of the duration 10T of input waveform despreader respectively with the output of frequency spreading wave maker two
Individual waveform is multiplied；
D) two integrators.This two integrators press duration T integration, output to the waveform segments of two duration 10T of two multiplier outputs respectively
Obtain the sequence of real numbers of two a length of 10；
E) two decision devices.This two decision devices have two input ports, and they all read in the output of described two integrators by turn.First
Decision device is sequentially output the true value of proposition " in two numbers being inputted, the absolute value of first is larger ".Second decision device is sequentially output
The true value of proposition " maximum absolute value in two numbers being inputted is positive number "；
F) a 6b/10b decoder.This 6b/10b decoder exports into row decoding continuous 10 of second decision device, obtains one 6
Bit binary code.This 6b/10b decoder can be a 2b/4b manchester decoder and 4b/6b decoder disclosed by the invention
Merge composition；
G) combiner.6 bit binary codes that this combiner exports 6b/10b decoder and 10 of the continuous output of first decision device
Bit is merged into the output as this waveform despreader for the dual code of 16 bits.
The invention discloses the construction of a broadband receiver, it is made up of following equipment：
A) radio-frequency front-end；
B) agitator.This agitator exports the cosine carrier used by this transmitter；
C) lock unit.This lock unit controls agitator；
D) phase shifter.The carrier wave that this phase shifter exports described agitator is converted into sinusoidal carrier；
E) two multipliers.The waveform that this two multipliers export radio-frequency front-end is just exported with the cosine carrier of agitator output and phase shifter respectively
String carrier multiplication；
F) adder.The waveform adder that this adder exports two multipliers；
G) a waveform despreader.This waveform despreader carries out de-spreading the output obtaining this broadband receiver to the output of adder.This waveform solution
Expanding device can be waveform despreader disclosed by the invention.
Brief description
Accompanying drawing 1 is the structure chart of a 4b/6b encoder.This 4b/6b encoder weaves into 6 bit binary codes 4 bit binary codes, and this 6
Bit binary code contains 30 and 31.This 4b/6b encoder is made up of following equipment：
A) a 4b/8b Manchester encoder.The input of this 4b/8b Manchester encoder is the input of this 4b/6b encoder, its handle
Input in described 4 bit binary codes 1 and 0 and be substituted for 10 and 01 respectively and obtain 8 bit binary codes；
B) modulo 2 adder, three and door and five XOR gates.6 of this 4b/6b encoder output are by the of Manchester encoder
One output, the output of second XOR gate, the output of the 3rd XOR gate, the output of the 4th XOR gate, the 5th XOR gate
The output composition of output and modulo 2 adder.First with door two inputs be respectively the 6th of 4b/8b Manchester encoder defeated
Go out and export with the 8th.Two inputs of first XOR gate are the 2nd of 4b/8b Manchester encoder respectively and export and the 3rd
Output.Second with door two inputs be respectively first with door export and first XOR gate output.3rd with door two
Individual input is that the 3rd output of 4b/8b Manchester encoder exports with the 8th respectively.Two inputs of second XOR gate are respectively
It is the 2nd of 4b/8b Manchester encoder output and first output with door.Two inputs of the 3rd XOR gate are respectively
3rd output of 4b/8b Manchester encoder and second output with door.Two inputs of the 4th XOR gate are 4b/8b respectively
7th output of Manchester encoder and the output of the 3rd XOR gate.Two inputs of the 5th XOR gate are that 4b/8b is graceful respectively
5th output of Che Site encoder and the 3rd output with door.Modulo 2 adder has three input ports, its three inputs point
It is not the output of the 7th output, first output with door and the 5th XOR gate of 4b/8b Manchester encoder.
Accompanying drawing 2 is the structure chart of a 4b/6b decoder.This 4b/6b decoder is translated into 4 bit binary codes 6 bit binary codes, and it has 6
Individual input port and 4 output ports.This 4b/6b decoder by two not gates, three form with door and five XOR gates.This 4b/6b translates
4 of device outputs of code are different by first input of this 4b/6b decoder, the output of the 4th XOR gate, the output of the 5th XOR gate and the 3rd
The output composition of OR gate.Two inputs of first XOR gate are that first input of this 4b/6b decoder inputs with second respectively.Second different
Two inputs of OR gate are that the 3rd input of this 4b/6b decoder inputs with the 5th respectively.The input of first not gate is first XOR gate
Output.First two input with door is the output of second XOR gate and the output of first not gate respectively.Two inputs of the 3rd XOR gate
It is the 3rd of this 4b/6b decoder input and the 4th input respectively.The input of second not gate is the output of the 3rd XOR gate.Second with
Two inputs of door are the 5th input of this 4b/6b decoder and the output of the 3rd XOR gate respectively.3rd two inputs with door are respectively
The output of first XOR gate and the output of second not gate.Two inputs of the 4th XOR gate are the 3rd input of this 4b/6b decoder respectively
With first output with door.Two inputs of the 5th XOR gate are second output with door and the 3rd output with door respectively.
Accompanying drawing 3 is the structure chart of frequency multiplier disclosed by the invention.This frequency multiplier depends on given positive integer parameter N, and it is 16 bits two
First code spreads to a 10N bit binary code.Disclosed frequency multiplier is made up of following equipment：
A) decomposer.The input of this decomposer is the input of this frequency multiplier, and it has two output ports.First outfan of this decomposer
Mouth parallel output inputs foremost 6 bit of 16 bit binary codes of decomposer.Second output port of this decomposer is defeated by bit
Go out to input last 10 bits of 16 bit binary codes of decomposer；
B) a 6b/10b encoder.The input of this 6b/10b encoder is the output of first output port of decomposer.This 6b/10b
6 bit binary codes of parallel input are weaved into 10 bit binary codes, this 10 bit binary code contains 50 and 51.This 6b/10b
Encoder can merge composition with a 2b/4b Manchester encoder and 4b/6b encoder described in a claim 2；
C) an initial state selector and a spread spectrum code generator.The input of initial state selector is the output of second output port of decomposer.Initial state is selected
Select device often read in a bit just export an initial state give spread spectrum code generator.Spread spectrum code generator exports spreading code, spread spectrum according to its initial state
In code, 1 number is 1 more than 0 number；
D) chip-rate clock.This chip-rate clock make spread code generator by bit output rate be 6b/10b encoder by
N times of bit output rate；
E) XOR gate.This XOR gate does XOR spread spectrum code generator by bit output and exporting by bit of 6b/10b encoder
The output of after-cost frequency multiplier.
Accompanying drawing 4 is the structure chart of transmitter disclosed by the invention.This transmitter is made up of following equipment：
A) frequency multiplier.The input of this frequency multiplier is exactly the input of this transmitter, it input data spread spectrum become some spreading codes and they
Radix-minus-one complement composition sequence.In spreading code, 1 number is 1 more than 0 number.This frequency multiplier can be frequency multiplier disclosed by the invention；
B) a Chip Waveform manipulator.This Chip Waveform manipulator is modulated into corresponding waveform the output of frequency multiplier；
C) agitator.This agitator exports the cosine carrier of this transmitter needs；
D) phase shifter.The carrier wave that this phase shifter exports agitator is converted into sinusoidal carrier；
E) two multipliers.The waveform that this two multipliers export Chip Waveform manipulator is defeated with the carrier multiplication of agitator output and phase shifter respectively
The carrier multiplication going out；
F) adder.This adder is added the output of two multipliers；
G) broadband filter.This broadband filter filters out the out-of-band frequency of the waveform of adder output, and its output is exactly this transmitter
Transmission signal.
Accompanying drawing 5 is the structure chart of sequence despreaders disclosed by the invention.This sequence despreaders depends on given positive integer parameter N, its handle
The sequence of real numbers of a length of 10N de-spreads into 16 bit binary codes.Disclosed sequence despreaders are made up of following equipment：
A) a spread spectrum code generator.This spread spectrum code generator has two output ports, the binary spreading code of their two a length of N of synchronism output,
In each spreading code, 1 number is 1 more than 0 number；
B) lock unit.This lock unit controls described spread spectrum code generator；
C) two correlators.This two correlators have two input ports, and their first input port continuously reads every time and input this sequence
The N position of the sequence of real numbers of a length of 10N of despreader.Second of this two correlators input be respectively two of spread spectrum code generator defeated
Go out.The correlation coefficient of their two list entries of output of each correlator.Here, the correlation coefficient of two list entries is first
Sue for peace after individual list entries and the bipolar sequence wise multiplication of second list entries and obtain；
D) two decision devices.This two decision devices have two input ports, and their two inputs are all the output of two correlators.First
Decision device exports the true value of proposition " in two correlation coefficienies being inputted, the absolute value of first is larger ".Second decision device output life
The true value of topic " maximum absolute value in two dependency numbers being inputted is positive number "；
E) a 6b/10b decoder.This 6b/10b decoder exports into row decoding continuous 10 of second decision device, obtains one 6
Bit binary code.This 6b/10b decoder can be a 2b/4b manchester decoder and 4b/6b decoder disclosed by the invention
Merge composition；
F) combiner.6 bit binary codes that this combiner exports 6b/10b decoder and 10 of the continuous output of first decision device
Bit is merged into 16 bit binary codes as the output of this sequence despreaders.
Accompanying drawing 6 is the structure chart of narrow-band receiver disclosed by the invention.It is made up of following equipment：
A) radio-frequency front-end；
B) agitator.This agitator exports the cosine carrier used by this transmitter；
C) lock unit.This lock unit controls agitator；
D) phase shifter.The carrier wave that this phase shifter exports agitator is converted into sinusoidal carrier；
E) two multipliers.The waveform that this two multipliers export radio-frequency front-end respectively with agitator output cosine carrier and the phase shifter output
Sinusoidal carrier is multiplied；
F) adder.The waveform adder that this adder exports described two multipliers；
G) an integration sampling device.The waveform segments that this integration sampling device exports to described adder duration integration as shared by 1 bit spreading code；
H) sequence despreaders.This sequence despreaders carries out de-spreading the output obtaining this narrow-band receiver to the output of integration sampling device.This
Sequence despreaders can be sequence despreaders disclosed by the invention.
Accompanying drawing 7 is the structure chart of waveform despreader disclosed by the invention.This waveform despreader depends on given positive integer parameter N and transmission
Duration T shared by the spreading code of one a length of N.This waveform despreader de-spreads into 16 bit binary codes the waveform of duration 10T, and it is by following
Equipment forms：
A) a frequency spreading wave maker.This frequency spreading wave maker has two output ports, and the binary of their two a length of N of synchronism output expands
The rectangular pulse waveform of frequency code.This two rectangular pulse waveform duration 10T, cycle are T；
B) lock unit.This lock unit controls frequency spreading wave maker；
C) two multipliers.This two multipliers the waveform of the duration 10T of input waveform despreader respectively with the output of frequency spreading wave maker two
Individual waveform is multiplied；
D) two integrators.This two integrators press duration T integration, output to the waveform segments of two duration 10T of two multiplier outputs respectively
Obtain the sequence of real numbers of two a length of 10；
E) two decision devices.This two decision devices have two input ports, and they all read in the output of described two integrators by turn.First
Decision device is sequentially output the true value of proposition " in two numbers being inputted, the absolute value of first is larger ".Second decision device is sequentially output
The true value of proposition " maximum absolute value in two numbers being inputted is positive number "；
F) a 6b/10b decoder.This 6b/10b decoder exports into row decoding continuous 10 of second decision device, obtains one 6
Bit binary code.This 6b/10b decoder can be a 2b/4b manchester decoder and 4b/6b decoder disclosed by the invention
Merge composition；
G) combiner.6 bit binary codes that this combiner exports 6b/10b decoder and 10 of the continuous output of first decision device
Bit is merged into the output as this waveform despreader for the dual code of 16 bits.
Accompanying drawing 8 is the structure chart the invention discloses broadband receiver.It is made up of following equipment：
A) radio-frequency front-end；
B) agitator.This agitator exports the cosine carrier used by this transmitter；
C) lock unit.This lock unit controls agitator；
D) phase shifter.The carrier wave that this phase shifter exports described agitator is converted into sinusoidal carrier；
E) two multipliers.The waveform that this two multipliers export radio-frequency front-end is just exported with the cosine carrier of agitator output and phase shifter respectively
String carrier multiplication；
F) adder.The waveform adder that this adder exports two multipliers；
G) a waveform despreader.This waveform despreader carries out de-spreading the output obtaining this broadband receiver to the output of adder.This waveform solution
Expanding device can be waveform despreader disclosed by the invention.
Specific embodiment
We be the present invention be embodied as propose to advise as follows.
In actual applications, it is desirable to use corresponding despreading method using corresponding receiver after transmitter applies spectrum spreading method disclosed in this invention.
Two reception schemes of the present invention.The first reception scheme is that first unloading wave de-spreads again.At this moment the integrating range of our integrator is no longer character pitch,
And must be chip-spaced.This can have higher requirement to lock unit and integrator.Second reception scheme is first to de-spread unloading wave again.At this moment we
The integrating range of integrator be character pitch.At this moment, because we employ two spreading code spread spectrums, circuit design is slightly more complex.
Claims (13)
1. a kind of 4b/6b coded method, described 4b/6b coded method weaves into 6 bit binary codes 4 bit binary codes, and described 6 bit binary codes contain
There is 30 and 31, described 4 bit binary codes to be encoded are designated as abcd, the method comprising the steps of：
A) as d=1, abcd is weaved intoDescribed symbol-it is non-operator；
B) as cd=10, abcd is weaved intoDescribed symbol-it is non-operator；
C) as cd=00, abcd is weaved intoDescribed symbol-it is non-operator.
2. a 4b/6b encoder, described 4b/6b encoder weaves into 6 bit binary codes 4 bit binary codes, and described 6 bit binary codes contain 3
Individual 0 and 31, described 4b/6b encoder is made up of following equipment：
A) a 4b/8b Manchester encoder, the input of described 4b/8b Manchester encoder is the input of described 4b/6b encoder, institute
State 4b/8b Manchester encoder and be substituted for 10 and 01 respectively and obtain 8 bits two inputting in described 4 bit binary codes 1 and 0
First code, the described 8 bit binary codes that described 4b/8b Manchester encoder is obtained by 8 output port parallel outputs；
B) modulo 2 adder, three and door and five XOR gates, 6 outputs of described 4b/6b encoder are by described Manchester encoder
First output, the output of described second XOR gate, the output of described 3rd XOR gate, the output of described 4th XOR gate,
The output composition of the output of described 5th XOR gate and described modulo 2 adder, described first two inputs with door are described respectively
6th output of 4b/8b Manchester encoder and the 8th output, two inputs of described first XOR gate are described 4b/8b respectively
2nd output of Manchester encoder and the 3rd output, described second two inputs with door are described first and door respectively
Output and described first XOR gate output, described 3rd two inputs with door are described 4b/8b Manchester's code respectively
3rd output of device and the 8th output, two inputs of described second XOR gate are described 4b/8b Manchester encoder respectively
The 2nd output and described first output with door, two inputs of described 3rd XOR gate are described 4b/8b Man Chesi respectively
3rd output of special encoder and described second output with door, two inputs of described 4th XOR gate are described 4b/8b respectively
The 7th of Manchester encoder exports the output with described 3rd XOR gate, and two inputs of described 5th XOR gate are respectively
5th output of described 4b/8b Manchester encoder and described 3rd output with door, described modulo 2 adder has three inputs
Port, three of described modulo 2 adder inputs be respectively the 7th output of described 4b/8b Manchester encoder, described first
With the output of door and the output of described 5th XOR gate.
3. a kind of 4b/6b interpretation method, described 4b/6b interpretation method is translated into 4 bit binary codes, described 6 bits to be decoded 6 bit binary codes
Dual code is designated as abcdef, the method comprising the steps of：
A) as c ≠ d, abcdef is translated into acd1；
B) as e=f, abcdef is translated into ac10；
C) as a=b, abcdef is translated into ae00.
4. a 4b/6b decoder, described 4b/6b decoder is translated into 4 bit binary codes 6 bit binary codes, and described 4b/6b decoder has 6
Input port and 4 output ports, described 4b/6b decoder by two not gates, three form with door and five XOR gates, described 4b/6b
4 outputs of decoder are by first input, the output of described 4th XOR gate, described 5th XOR gate of described 4b/6b decoder
Output and described 3rd XOR gate output composition, two of described first XOR gate inputs are the of described 4b/6b decoder respectively
One input and second input, two inputs of described second XOR gate are the 3rd input and the 5th of described 4b/6b decoder respectively
Individual input, the input of described first not gate is the output of described first XOR gate, and described first two inputs with door are described respectively
The output of second XOR gate and the output of described first not gate, two inputs of described 3rd XOR gate are described 4b/6b decoding respectively
3rd input of device and the 4th input, the input of described second not gate is the output of described 3rd XOR gate, described second and door
Two inputs be the 5th of described 4b/6b decoder input and the output of described 3rd XOR gate respectively, described 3rd with door two
Individual input is the output of described first XOR gate and the output of described second not gate respectively, and two inputs of described 4th XOR gate are respectively
It is the 3rd input of described 4b/6b decoder and described first output with door, two inputs of described 5th XOR gate are institute respectively
State second output with door and described 3rd output with door.
5. a kind of spectrum spreading method, described spectrum spreading method depends on the binary spreading code of two a length of N, and in described spreading code, 1 number is more than 0 number
1, described spectrum spreading method spreads into 10N bit binary code 16 bit binary codes, and described spectrum spreading method comprises the following steps：
A) described 16 bit binary codes are truncated into the dual code of 6 bit binary codes and 10 bits；
B) with a fixing algorithm, 6 bit binary codes described in step a are weaved into 10 bit binary codes, described 10 bit binary codes contain 50 and 5
Individual 1, described fixing algorithm can be closed with a 2b/4b Manchester encoding method and 4b/6b coded method described in a claim 1
And form；
C) each bit of 10 bit binary codes described in step b is repeated n times, obtain a 10N bit binary code：
D) with 0 and 1 in 10 bit binary codes described in binary spreading code difference replacement step a of described two a length of N, obtain a 10N ratio
Special dual code；
E) step c and step d described two 10N bit binary code are done XOR by bit, the 10N bit binary code obtaining is exactly described
The dual code that spectrum spreading method generates.
6. a frequency multiplier, described frequency multiplier depends on positive integer parameter N, and described frequency multiplier spreads to a 10N bit 16 bit binary codes
Dual code, described frequency multiplier is made up of following equipment：
A) decomposer, the input of described decomposer is the input of described frequency multiplier, and described decomposer has two output ports, described decomposer
One output port parallel output inputs foremost 6 bit of 16 bit binary codes of described decomposer, and described decomposer second is defeated
Exit port exports last 10 bits of the 16 bit binary codes inputting described decomposer by bit；
B) a 6b/10b encoder, the input of described 6b/10b encoder is the output of first output port of described decomposer, described 6b/10b
6 bit binary codes of parallel input are weaved into 10 bit binary codes, described 10 bit binary codes contain 50 and 51, described 6b/10b
Encoder can merge composition with a 2b/4b Manchester encoder and 4b/6b encoder described in a claim 2；
C) an initial state selector and a spread spectrum code generator, the input of described initial state selector is the output of described second output port of decomposer,
Described initial state selector often reads in a bit and just exports an initial state to described spread spectrum code generator, and described spread spectrum code generator is according at the beginning of it
State exports spreading code, and in described spreading code, 1 number is 1 more than 0 number；
D) chip-rate clock, what described chip-rate clock made described spread spectrum code generator is that described 6b/10b compiles by bit output rate
N times by bit output rate of code device.
E) XOR gate, described XOR gate does described spread spectrum code generator by bit output and exporting by bit of described 6b/10b encoder
The output of described frequency multiplier is generated after XOR.
7. a transmitter, described transmitter is made up of following equipment：
A) frequency multiplier, the input of described frequency multiplier is exactly the input of described transmitter, and described frequency multiplier becomes the data spread spectrum of input
Spreading code and the sequence of their radix-minus-one complement composition, in described spreading code, 1 more than 0 number, described frequency multiplier can be right to 1 number
Require frequency multiplier described in 4；
B) a Chip Waveform manipulator, described Chip Waveform manipulator is modulated into corresponding waveform the output of described frequency multiplier；
C) agitator, described agitator exports the cosine carrier that described transmitter needs；
D) phase shifter, the carrier wave that the described phase shifter exports described agitator is converted into sinusoidal carrier；
E) two multipliers, the waveform that described two multipliers the export described Chip Waveform manipulator carrier wave phase with the output of described agitator respectively
Take advantage of the carrier multiplication with the output of described phase shifter；
F) adder, described adder is added the output of described two multipliers；
G) broadband filter, becomes described transmitting after the out-of-band frequency that the waveform of described adder output filters out via described broadband filter
The transmission signal of machine.
8. a kind of despreading method, described despreading method depends on the binary spreading code of two a length of N, and in described spreading code, 1 number is more than 0 number
1, described despreading method de-spreads into 16 bit binary codes the sequence of real numbers of a length of 10N, and described despreading method comprises the following steps：
A) sequence of real numbers of described a length of 10N to be de-spread is cut and be divided into the 10 sections long sequence of real numbers for N, be the real number sequence of N described every segment length
Row change the dual code therewith in the spreading code of described two a length of N and their radix-minus-one complement with maximum correlation coefficient into, obtain one by 10
Segment length is the dual code of a length of 10N of dual code composition of N, the phase relation of the sequence of real numbers of described a length of N and the dual code of a length of N
Number be described a length of N sequence of real numbers and the bipolar code wise multiplication of the dual code of described a length of N after sue for peace and obtain；
B) dual code being N segment length every in the dual code of a length of 10N being divided into 10 sections described in step a changes the parity of their Hamming weight into,
Obtain 10 bit binary codes；
C) it is translated into 6 bit binary codes with the described 10 bit binary codes that the decoding algorithm of a fixation obtains step b, described decoding algorithm is permissible
Merged by 2b/4b Manchester decoding algorithm and interpretation method described in a claim 3 and form；
D) set up the one-to-one corresponding between the binary spreading code of described two a length of N and 0,1, be divided into according to described one-to-one corresponding is step a
In 10 sections of the dual code of a length of 10N, every segment length is the dual code of N or directly changes 0 and 1 into, or changes into after their radix-minus-one complement again
Change 0 and 1 into, obtain 10 bit binary codes；
E) the described 10 bit binary codes that the step c described 6 bit binary codes that obtain of decoding and step d are obtained are merged into 16 bits
The code that dual code obtains as described despreading method.
9. sequence despreaders, described sequence despreaders depend on positive integer parameter N, and described sequence despreaders are the sequence of real numbers of a length of 10N
De-spread into 16 bit binary codes, described sequence despreaders are made up of following equipment：
A) a spread spectrum code generator, described spread spectrum code generator has two output ports, and two output ports of described spread spectrum code generator are synchronously defeated
Go out the binary spreading code of two a length of N, in described spreading code, 1 number is 1 more than 0 number；
B) lock unit, described lock unit controls described spread spectrum code generator；
C) two correlators, described two correlators have two input ports, and first input port of described two correlators continuously reads every time
Input the N position of the sequence of real numbers of a length of 10N of described sequence despreaders, second input of described two correlators is described spread spectrum respectively
Two outputs of code generator, the correlation coefficient of their two list entries of output of each correlator described, described two list entries
Correlation coefficient be described first list entries with the bipolar sequence wise multiplication of second list entries after sue for peace and obtain；
D) two decision devices, described two decision devices have two input ports, and two inputs of described two decision devices are all described two correlators
Output, described first decision device export the true value of proposition " in two correlation coefficienies being inputted, the absolute value of first is larger ", institute
State the true value that second decision device exports proposition " maximum absolute value in two dependency numbers being inputted is positive number "；
E) a 6b/10b decoder, described 6b/10b decoder exports into row decoding continuous 10 of described second decision device, obtains one
Individual 6 bit binary codes, described 6b/10b decoder can be a 2b/4b manchester decoder and 4b/6b described in a claim 4
Decoder merges composition；
F) combiner, the 6 bit binary codes that described combiner exports described 6b/10b decoder and described first decision device continuously export
10 bits be merged into 16 bit binary codes as the output of described sequence despreaders.
10. a narrow-band receiver, described narrow-band receiver is made up of following equipment：
A) radio-frequency front-end；
B) agitator, described agitator exports the cosine carrier used by described transmitter；
C) lock unit, described lock unit controls described agitator；
D) phase shifter, the carrier wave that the described phase shifter exports described agitator is converted into sinusoidal carrier；
E) two multipliers, the waveform that described two multipliers the export described radio-frequency front-end cosine carrier and described with the output of described agitator respectively
The sinusoidal carrier of phase shifter output is multiplied；
F) adder, the waveform adder that described adder exports described two multipliers；
G) an integration sampling device, the waveform segments that described integration sampling device exports to described adder duration integration as shared by transmission 1 bit spreading code；
H) sequence despreaders, described sequence despreaders carry out de-spreading the output obtaining described narrow-band receiver to the output of described integration sampling device.
Described sequence despreaders can be sequence despreaders described in claim 10.
A kind of 11. despreading methods, described despreading method depends on shared by the binary spreading code of two a length of N and the binary spreading code of one a length of N of transmission
Duration T, in described spreading code, 1 more than 0 number, described despreading method de-spreads into 16 bits two the waveform of duration 10T to 1 number
First code, described despreading method comprises the following steps：
A) spreading code of described two a length of N is modulated into respectively the rectangular pulse waveform of two cycle T, duration 10T；
B) the waveform of described duration 10T to be de-spread respectively cycle T described two with step a, duration 10T rectangular pulse waveform be multiplied, obtain
Waveform to two duration 10T；
The waveform segments of the described two duration 10T c) step b being obtained are integrated by duration T, obtain the sequence of real numbers of two a length of 10；
D) successively to i from 1 to 10, take the true value of proposition " in i-th of two sequences being obtained by step c, absolute value is larger is positive number ",
Thus obtain the binary sequence of a length of 10；
E) with the decoding algorithm of a fixation, step d is obtained described 10 bits and be translated into 6 bit binary codes, described decoding algorithm can be by one
2b/4b Manchester decoding algorithm and interpretation method described in a claim 3 merge composition；
F) successively to i from 1 to 10, take the true value of proposition " in i-th of two sequences being obtained by step c, the absolute value of first is larger ",
Thus obtain the binary sequence of a length of 10；
G) described a length of 10 binary sequence that the step e described 6 bit binary codes that obtain of decoding and step f are obtained is merged into 16 bits
The code that dual code obtains as described despreading method.
12. 1 waveform despreaders, described waveform despreader depends on positive integer parameter N and the duration shared by spreading code of one a length of N of transmission
T, described waveform despreader de-spreads into 16 bit binary codes the waveform of duration 10T, and described waveform despreader is made up of following equipment：
A) a frequency spreading wave maker, described frequency spreading wave maker has two output ports, two outfans of described frequency spreading wave maker
The rectangular pulse waveform of the binary spreading code of mouth two a length of N of synchronism output, described two rectangular pulse waveform duration 10T, described two
The individual rectangular pulse waveform cycle is T；
B) lock unit, described lock unit controls described frequency spreading wave maker；
C) two multipliers, described two multipliers are generated the waveform of the duration 10T inputting described waveform despreader respectively with described frequency spreading wave
Two waveforms of device output are multiplied and product are exported；
D) two integrators, described two integrators are pressed duration T to the waveform segments of two duration 10T of described two multipliers output respectively and are amassed
Point, output obtains the sequence of real numbers of two a length of 10；
E) two decision devices, described two decision devices have two input ports, and two input ports of described two decision devices read in respectively by turn
The output of described two integrators, described first decision device is sequentially output proposition, and " in two numbers being inputted, the absolute value of first is relatively
True value greatly ", described second decision device is sequentially output the true of proposition " maximum absolute value in two numbers being inputted is positive number "
Value；
F) a 6b/10b decoder, described 6b/10b decoder exports into row decoding continuous 10 of described second decision device, obtains one
Individual 6 bit binary codes, described 6b/10b decoder can be described in a 2b/4b manchester decoder and a claim 7
4b/6b decoder merges composition；
G) combiner, the 6 bit binary codes that described combiner exports described 6b/10b decoder and described first decision device continuously export
10 bits be merged into the output as described waveform despreader for the dual code of 16 bits.
13. 1 broadband receivers, described broadband receiver is made up of following equipment：
A) radio-frequency front-end；
B) agitator, described agitator exports the cosine carrier used by described transmitter；
C) lock unit, described lock unit controls described agitator；
D) phase shifter, the carrier wave that the described phase shifter exports described agitator is converted into sinusoidal carrier；
E) two multipliers, the waveform that described two multipliers the export described radio-frequency front-end cosine carrier and described with the output of described agitator respectively
The sinusoidal carrier of phase shifter output is multiplied；
F) adder, the waveform adder that described adder exports described two multipliers；
G) a waveform despreader, described waveform despreader carries out de-spreading, to the output of described adder, the output obtaining described broadband receiver, described
Waveform despreader can be waveform despreader described in claim 12.
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