CN106449629B - electrostatic discharge clamping circuit - Google Patents
electrostatic discharge clamping circuit Download PDFInfo
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- CN106449629B CN106449629B CN201610404711.4A CN201610404711A CN106449629B CN 106449629 B CN106449629 B CN 106449629B CN 201610404711 A CN201610404711 A CN 201610404711A CN 106449629 B CN106449629 B CN 106449629B
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- static discharge
- electrostatic
- contact
- high potential
- power supply
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- 230000003068 static effect Effects 0.000 claims description 83
- 230000004888 barrier function Effects 0.000 claims description 18
- 230000005611 electricity Effects 0.000 claims description 6
- 238000009434 installation Methods 0.000 claims 2
- 230000000903 blocking effect Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 8
- 238000004088 simulation Methods 0.000 description 4
- 230000006378 damage Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 210000000080 chela (arthropods) Anatomy 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Abstract
The invention provides an electrostatic discharge clamping circuit, which comprises an electrostatic discharge device, an electrostatic discharge trigger device and a blocking element. The electrostatic discharge device is connected to a power supply, and the power supply has a high potential and a ground. The first end of the electrostatic discharge device is connected with the high potential, and the second end of the electrostatic discharge device is connected with the ground so as to discharge the electrostatic generated by the power supply. The electrostatic discharge trigger device is connected to the power supply and the electrostatic discharge device, and generates a control signal to a third end of the electrostatic discharge device according to the high potential of the power supply, so as to control the electrostatic discharge device to be turned on or off, and the electrostatic discharge device discharges the electrostatic generated by the power supply. The blocking element is connected to the electrostatic discharge triggering device and the electrostatic discharge device to improve the discharge speed of the electrostatic discharge device.
Description
Technical field
The present invention relates to the technical field of static discharge, espespecially a kind of electrostatic discharge clamp.
Background technology
Static discharge (Electrostatic Discharge, ESD) is to cause most of electronic component or electronic system
By the excessive principal element that electrically stress (Electrical Overstress, EOS) destroys.This destruction can cause partly to lead
The permanent destruction of volume elements part and computer system etc., thus influence integrated circuit (Integrated Circuits, ICs)
Circuit function, and make electronic product work abnormal.
Fig. 1 is an existing electrostatic discharge circuit 100.It is by NMOS transistor Q1, Q3, a PMOS transistor Q2, one
Resistance R1 and a capacitance C1 are constituted.Wherein, NMOS transistor Q1 is a static discharge transistor.When usual, by Vdd
It via resistance R1, and charges to capacitance C1, the voltage of nodes X is about 5V, close with Vdd voltage, therefore PMOS transistor Q2 is to close
Closed state (OFF), NMOS transistor Q3 are conducting state (ON), therefore the voltage of node Y is close with the voltage of node Z, about
For 0V.Therefore NMOS transistor Q1 is in off state.
When Vdd is formed by positive surge voltage by electrostatic, due to slower to capacitor charging, PMOS transistor Q2
Source electrode and grid between there is pressure difference, and PMOS transistor Q2 is made to be connected, therefore the voltage of node Y therefore makes NMOS toward pull-up
Transistor Q1 conductings, an earth point Gnd is oriented to by the positive surge voltage on Vdd.The work of this i.e. electrostatic discharge circuit 100 is former
Reason.
However, when PMOS transistor Q2 is begun to turn on and the voltage of node Y starts toward pull-up, due to NMOS transistor Q3
It is also conducting state, and node Z ground connection, therefore node Y and can not be rapid toward pull-up, it cause NMOS transistor Q1 conductings slowly.Therefore
Positive surge voltage on Vdd is easy to damage interlock circuit.Therefore, existing electrostatic discharge circuit structure still has improved sky
Between.
Invention content
The purpose of the present invention predominantly provides an electrostatic discharge clamp, can promote the velocity of discharge, will be on power supply
Positive surge voltage or negative surge voltage are discharged rapidly, and then protect interlock circuit.
A feature according to the present invention, the present invention propose a kind of electrostatic discharge clamp, including：One static discharge
(Electrostatic Discharge, ESD) device, is connected to a power supply, which has a high potential and a ground connection, should
One first end of static discharge device is connected to the high potential, and one second end is connected to the ground connection, which is generated
Static discharge, wherein the static discharge device is one first NMOS transistor, and a drain electrode of first NMOS transistor is connected to
The high potential, one source electrode are connected to the ground connection；One static discharge trigger device is connected to the power supply and static discharge dress
It sets, according to the high potential of the power supply, to generate a control signal to a third end of the static discharge device, to which control should
Static discharge device is turned on and off, so that the static discharge that the static discharge device generates the power supply；And one barrier member
Part is connected to the static discharge trigger device and the static discharge device, to promote the velocity of discharge of the static discharge device,
In, which is resistance, inductance, MOS transistor or diode, and the barrier element one end is connected to one second contact,
Its other end is connected to the second end of the static discharge device；Wherein, when the high potential of the power supply has one by electrostatic institute
When the positive surge voltage of formation, which is not connected to the ground connection, the voltage quilt of second contact and a third contact
The surge voltage should be formed by by electrostatic to draw high, so that first NMOS transistor is opened ahead of time, to repid discharge.
A feature according to the present invention, the present invention propose a kind of electrostatic discharge clamp, including：One static discharge fills
It sets, is connected to a power supply, which there is a high potential and a ground connection, a first end of the static discharge device to be connected to the height
Current potential, one second end are connected to the ground connection, the static discharge which is generated, wherein the static discharge device is one
One source electrode of the first PMOS transistor, first PMOS transistor is connected to the high potential, and one drain electrode is connected to the ground connection；One
Static discharge trigger device is connected to the power supply and the static discharge device, according to the high potential of the power supply, to generate a control
Signal processed is turned on and off to a third end of the static discharge device to control the static discharge device, so that the electrostatic
The static discharge that electric discharge device generates the power supply；And a barrier element, it is connected to the static discharge trigger device and this is quiet
Between discharge of electricity device, to promote the velocity of discharge of the static discharge device, wherein the barrier element is resistance, inductance, MOS
Transistor or diode, and the barrier element one end is connected to the static discharge trigger device, the other end is connected to height electricity
Position and the static discharge device；It wherein, should when the high potential of the power supply is formed by positive surge voltage with one by electrostatic
Static discharge trigger device is not connected to the high potential, and the voltage of a third contact is formed by surge electricity by this by electrostatic
Pressure is drawn high, so that first PMOS transistor is opened ahead of time, to repid discharge.
Description of the drawings
Fig. 1 is an existing electrostatic discharge circuit.
Fig. 2 is the block diagram of the electrostatic discharge clamp of the present invention.
Fig. 3 is the detailed circuit diagram of the electrostatic discharge clamp of the present invention.
Fig. 4 is present invention figure compared with a simulation of the prior art.
Fig. 5 is present invention figure compared with another simulation of the prior art.
Fig. 6 is another block diagram of the electrostatic discharge clamp of the present invention.
Fig. 7 is a kind of detailed circuit diagram of electrostatic discharge clamp of Fig. 6 of the present invention.
Symbol description：
Electrostatic discharge circuit 100 NMOS transistor Q1, Q3
PMOS transistor Q2 resistance R1
Capacitance C1
Electrostatic discharge clamp 200
210 static discharge trigger device 220 of static discharge device
Barrier element 230
High potential Vdd is grounded Gnd
First the first PMOS transistors of NMOS transistor N1 P1
Second NMOS transistor N2 first resistors R
Capacitance C rectangles N
600 second PMOS transistor P2 of electrostatic discharge clamp.
Specific implementation mode
Fig. 2 is a kind of block diagram of electrostatic discharge clamp 200 of a first embodiment of the invention.The static discharge pincers
Position circuit 200 includes a static discharge (Electrostatic Discharge, ESD) device 210, static discharge triggering dress
Set (ESD gate trigger circuit) 220 and a barrier element (Blocking component) 230.
The static discharge device 210 is connected to a power supply and a ground connection Gnd with a high potential Vdd.The static discharge
One first end of device is connected to high potential Vdd, and one second end is connected to ground connection Gnd, which is generated quiet
Discharge of electricity.
The static discharge trigger device 220 is connected to the power supply and the static discharge device 210, the height according to the power supply
Current potential Vdd, to generate a control signal (Control signal) to a third end of the static discharge device 210, to control
It makes the static discharge device 210 to be turned on and off, so that the static discharge that the static discharge device 210 generates the power supply.
The barrier element 230 be connected to the static discharge trigger device 220 and the static discharge device 210 this second
End, to promote the velocity of discharge of the static discharge device 210.
Fig. 3 is the detailed circuit diagram of first embodiment of the present invention electrostatic discharge clamp 200.As shown in figure 3, this is quiet
Discharge of electricity device 210 is a three-terminal element.The static discharge device 210 can be MOS transistor, BJT transistors, FET transistor
Or thyristor (Silicon Controlled Rectifier, SCR).Wherein, in the present embodiment, which fills
It is set to one first NMOS transistor N1, a drain D of first NMOS transistor N1 is connected to high potential Vdd, one source S
It is connected to ground connection Gnd.
The static discharge trigger device 220 includes one first PMOS transistor P1, one second NMOS transistor N2, one first
A resistance R and capacitance C.Wherein, a source S of first PMOS transistor P1 is connected to high potential Vdd, grid G connection
To one first contact A.A source S of second NMOS transistor N2 is connected to one second contact B, grid G be connected to this
One contact A, drain D are connected to a drain D and the first NMOS crystal of a third contact C, first PMOS transistor P1
A grid G of pipe N1.One end of first resistor R is connected to high potential Vdd, and the other end is connected to first contact A.It should
Capacitance C is connected to first contact A, and the other end is connected to second contact B.
The barrier element 230 can be resistance, inductance, MOS transistor or diode.In the present embodiment, the barrier element
230 one end are connected to second contact B, and the other end is connected to ground connection Gnd.
When the high potential Vdd of the power supply is formed by positive surge voltage with one by electrostatic, simultaneously due to the second contact B
It is disconnected to ground connection Gnd so that contact A, B, C moment all be high resistance point, therefore third contact C voltage be easy faster by
The surge voltage should be formed by by electrostatic to draw high and second NMOS transistor N2 is made to be connected, to rapidly by the high potential
Positive surge tension discharge on Vdd.
When the ground connection Gnd of the power supply have one negative surge voltage is formed by by electrostatic when, due to the second contact B with
There is barrier element between Gnd, therefore the moment that contact B comes in surge voltage will not be born surge voltage toward drop-down by this.And second
NMOS transistor N2 is open so that the voltage of the second contact B and third contact C maintain certain value, such as are about
0V.Due to, the reason of surge voltage is born, therefore pressure difference occur between the source S and grid G of first NMOS transistor N1, and
First NMOS transistor N1 is set to be connected, so that first NMOS transistor N1 is opened, thus rapidly will be on ground connection Gnd
Negative surge voltage electric discharge.However, as shown in Figure 1, in the prior art, node Z is directly grounded, as the ground connection Gnd of the power supply
When being formed by negative surge voltage by electrostatic with one, the voltage of node Z makes the voltage of node Y at the first time by toward drop-down
By toward drop-down, causes the voltage difference between the source electrode and grid of NMOS transistor Q1 little, therefore NMOS transistor Q1 can not be allowed to exist
Rapid conducting at the first time.Therefore, the embodiment of the present invention has the effect of repid discharge, can solve the disadvantage that the prior art.
Fig. 4 is present invention figure compared with a simulation of the prior art, and the horizontal axis of Fig. 4 is the time, and the longitudinal axis is electric current, difference
For the electric current of the NMOS transistor Q1 and the present invention of the prior art first NMOS transistor N1.As shown in figure 4, working as the high potential
When Vdd is formed by positive surge voltage with one by electrostatic, the electric current for flowing through first NMOS transistor N1 of the invention is much larger than
The electric current of the NMOS transistor Q1 of the prior art is flowed through, this indicates that the present invention can actually relatively efficiently will be on high potential Vdd
Positive surge tension discharge.
Fig. 5 is present invention figure compared with another simulation of the prior art, will to be amplified at the rectangle N in Fig. 4.
As shown in figure 5, when conducting of the turn-on time of the present invention first NMOS transistor N1 compared with the NMOS transistor Q1 of the prior art
Between it is early, this indicates that first NMOS transistor N1 of the present invention can rapidly be connected, to effectively will be on high potential Vdd
Positive surge tension discharge.
Fig. 6 is a block diagram of the electrostatic discharge clamp 600 of a second embodiment of the invention.Fig. 7 is the present invention the
A kind of detailed circuit diagram of electrostatic discharge clamp 600 of two embodiments.Difference lies in the resistances with embodiment Fig. 2, Fig. 3 for it
High potential Vdd and static discharge device 210 are connected every one end of element 230, the other end connects static discharge trigger device
220.It is noted that compared to above-described embodiment, in the present embodiment, static discharge device 210 can be by this first
NMOS transistor N1 is changed to one second PMOS transistor P2, and simultaneously in static discharge trigger device 220, the first resistor
The location swap of R and capacitance C.The explanation that its operation principle can refer to above-described embodiment is learnt, therefore details are not described herein.
By preceding description it is found that compared with the prior art, the present invention proposes a new electrostatic discharge clamp framework,
Including the barrier element 230, it can make first NMOS transistor N1 that can rapidly be connected, to effectively by the surge on power supply
Tension discharge.
Above-described embodiment is illustrated only for facilitating explanation, and interest field of the presently claimed invention should be wanted certainly with right
Subject to asking described, not just the above examples.
Claims (7)
1. a kind of electrostatic discharge clamp, including：
One static discharge device is connected to a power supply, which is grounded with a high potential and one, and the one of the static discharge device
First end is connected to the high potential, and one second end is connected to the ground connection, the static discharge which is generated, wherein should
Static discharge device is one first NMOS transistor, and a drain electrode of first NMOS transistor is connected to the high potential, one source
Pole is connected to the ground connection；
One static discharge trigger device is connected to the power supply and is connected to the static discharge device via a third contact, according to
It is put with generating a control signal to a third end of the static discharge device to control the electrostatic according to the high potential of the power supply
Electric installation is turned on and off, so that the static discharge that the static discharge device generates the power supply；And
One barrier element is connected between the static discharge trigger device and the static discharge device, to promote the static discharge
The velocity of discharge of device, wherein the barrier element is resistance, inductance, MOS transistor or diode, and the barrier element one end
Be connected to the static discharge trigger device via one second contact, the other end be connected to the static discharge device this second
End；
Wherein, when the high potential of the power supply is formed by positive surge voltage with one by electrostatic, which not connects
It is connected to the ground connection, the voltage of second contact and the third contact is formed by the surge voltage by electrostatic by this and draws high, so that
First NMOS transistor is opened ahead of time, to repid discharge.
2. electrostatic discharge clamp according to claim 1, wherein the static discharge trigger device includes one first
PMOS transistor, one second NMOS transistor, a first resistor and a capacitance.
3. electrostatic discharge clamp according to claim 2, wherein a source electrode of first PMOS transistor is connected to
The high potential, grid are connected to one first contact, and a source electrode of second NMOS transistor is connected to second contact, grid
Pole is connected to first contact, drain electrode be connected to the third contact, first PMOS transistor a drain electrode and this first
One grid of NMOS transistor.
4. electrostatic discharge clamp according to claim 3, wherein one end of the first resistor is connected to height electricity
Position, the other end are connected to first contact, and for the capacitance connection to first contact, the other end is connected to second contact.
5. electrostatic discharge clamp according to claim 1, wherein when the ground connection of the power supply has one by electrostatic institute
When the negative surge voltage formed, which is not connected to the ground connection, the voltage dimension of second contact and the third contact
It holds in certain value, so that first NMOS transistor is opened, to repid discharge.
6. a kind of electrostatic discharge clamp, including：
One static discharge device is connected to a power supply, which is grounded with a high potential and one, and the one of the static discharge device
First end is connected to the high potential, and one second end is connected to the ground connection, the static discharge which is generated, wherein should
Static discharge device is one first PMOS transistor, and a source electrode of first PMOS transistor is connected to the high potential, one leakage
Pole is connected to the ground connection；
One static discharge trigger device is connected to the power supply and is connected to the static discharge device via a third contact, according to
It is put with generating a control signal to a third end of the static discharge device to control the electrostatic according to the high potential of the power supply
Electric installation is turned on and off, so that the static discharge that the static discharge device generates the power supply；And
One barrier element is connected between the static discharge trigger device and the static discharge device, to promote the static discharge
The velocity of discharge of device, wherein the barrier element is resistance, inductance, MOS transistor or diode, and the barrier element one end
It is connected to the static discharge trigger device, the other end is connected to the high potential and the static discharge device；
Wherein, when the high potential of the power supply is formed by positive surge voltage with one by electrostatic, static discharge triggering dress
It sets and is not connected to the high potential, the voltage of the third contact is formed by the surge voltage by electrostatic by this and draws high, so that should
First PMOS transistor is opened ahead of time, to repid discharge.
7. electrostatic discharge clamp according to claim 6, wherein when the ground connection of the power supply has one by electrostatic institute
When the negative surge voltage formed, which is not connected to the high potential, and the voltage of the third contact maintains
In certain value, so that first PMOS transistor is opened, to repid discharge.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104125740 | 2015-08-07 | ||
| TW104125740A TWI547096B (en) | 2015-08-07 | 2015-08-07 | Electrostatic discharge clamp circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106449629A CN106449629A (en) | 2017-02-22 |
| CN106449629B true CN106449629B (en) | 2018-10-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610404711.4A Active CN106449629B (en) | 2015-08-07 | 2016-06-08 | electrostatic discharge clamping circuit |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN106449629B (en) |
| TW (1) | TWI547096B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI662759B (en) * | 2017-11-16 | 2019-06-11 | 和碩聯合科技股份有限公司 | Circuit for preventing surge and electronic apparatus having the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101359825A (en) * | 2007-03-08 | 2009-02-04 | 沙诺夫公司 | Method and aparatus for improved electrostatic discharge protection |
| CN104319275A (en) * | 2014-04-23 | 2015-01-28 | 上海兆芯集成电路有限公司 | Electrostatic discharge protection circuit |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI264106B (en) * | 2002-04-30 | 2006-10-11 | Winbond Electronics Corp | Static charge protection circuit of adopting gate-coupled MOSFET (metal-oxide-semiconductor field effect transistor) |
| US7755871B2 (en) * | 2007-11-28 | 2010-07-13 | Amazing Microelectronic Corp. | Power-rail ESD protection circuit with ultra low gate leakage |
| US8654488B2 (en) * | 2010-07-12 | 2014-02-18 | Nxp B.V. | Secondary ESD circuit |
| US8767360B2 (en) * | 2012-05-29 | 2014-07-01 | Globalfoundries Singapore Pte. Ltd. | ESD protection device for circuits with multiple power domains |
-
2015
- 2015-08-07 TW TW104125740A patent/TWI547096B/en active
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2016
- 2016-06-08 CN CN201610404711.4A patent/CN106449629B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101359825A (en) * | 2007-03-08 | 2009-02-04 | 沙诺夫公司 | Method and aparatus for improved electrostatic discharge protection |
| CN104319275A (en) * | 2014-04-23 | 2015-01-28 | 上海兆芯集成电路有限公司 | Electrostatic discharge protection circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI547096B (en) | 2016-08-21 |
| CN106449629A (en) | 2017-02-22 |
| TW201707377A (en) | 2017-02-16 |
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