CN106449441A - Modified digital isolator coil and manufacturing method thereof - Google Patents
Modified digital isolator coil and manufacturing method thereof Download PDFInfo
- Publication number
- CN106449441A CN106449441A CN201610948113.3A CN201610948113A CN106449441A CN 106449441 A CN106449441 A CN 106449441A CN 201610948113 A CN201610948113 A CN 201610948113A CN 106449441 A CN106449441 A CN 106449441A
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- China
- Prior art keywords
- coil
- layer
- insulating barrier
- digital isolator
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title abstract description 6
- 239000002184 metal Substances 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000013078 crystal Substances 0.000 claims abstract description 11
- 238000001259 photo etching Methods 0.000 claims abstract description 4
- 230000004888 barrier function Effects 0.000 claims description 26
- 229920000642 polymer Polymers 0.000 claims description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 239000004642 Polyimide Substances 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 239000010949 copper Substances 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 238000000151 deposition Methods 0.000 abstract description 7
- 238000003860 storage Methods 0.000 abstract description 5
- 238000002955 isolation Methods 0.000 abstract description 4
- 239000004033 plastic Substances 0.000 abstract description 4
- 230000008569 process Effects 0.000 abstract description 3
- 239000000084 colloidal system Substances 0.000 abstract 1
- 238000012858 packaging process Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 16
- 238000005538 encapsulation Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000003292 glue Substances 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 238000009795 derivation Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000004952 Polyamide Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002466 imines Chemical class 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002372 labelling Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Coils Or Transformers For Communication (AREA)
Abstract
The invention discloses a modified digital isolator coil and a manufacturing method thereof. The manufacturing method of the modified digital isolator coil includes the steps: 1, providing a wafer substrate including a lower layer coil; 2, depositing a first insulating layer on the wafer substrate; 3, partially depositing a seed crystal layer on the first insulating layer; 4, on the seed crystal layer, photoetching and defining a pattern, wherein the pattern and the lower layer coil are overlapped; 5, depositing a metal layer at the phtoetching position in the step 4; 6, removing the first insulating layer of the step 2, and reserving the metal layer; 7, removing the seed crystal layer of the step 3, and reserving the metal layer; 8, forming an upper layer coil by the reserved metal layer, and forming an isolation coil by overlapping of the upper and lower layer coils; and 9, depositing a second insulating layer on the upper layer coil. By increasing one process and using the second insulating layer P1 instead of plastic package colloid to isolate metal layers with different potential on the same horizontal plane, the modified digital isolator coil and the manufacturing method thereof can improve the isolating capability in the horizontal direction, can reduce the influence of the back section packaging process or storage environment, and can reduce the area of a chip and reduce the cost.
Description
Technical field
The present invention relates to the digital isolator in semicon industry, especially a kind of improved digital isolator coil and its
Manufacture method.
Background technology
Digital isolator retarder top layer is wire coil.The top layer coil and side are drawn in the pad of inner coil
Between generally rely on encapsulation filling plastic packaging glue completely cut off.
As shown in figure 1, after the inner coil of digital isolator is completed, traditional way is that one layer of redeposition is exhausted
Edge layer, and form the derivation lead 11 of upper coil on the insulating layer, the derivation lead 12 of inner coil is drawn, this producer
Method is in same level and close together due to the top edge of coil and 12 pads for being connect, when coil working, two
Very big pressure reduction is had between person, and higher pressure reduction can cause the adverse consequencess for puncturing of horizontal direction.Through measuring, such as
Fruit needs to completely cut off the voltage of 2500V, and both spacing at least will the empty safe distance to more than 200um.And plastic packaging glue is exhausted
Edge characteristic is affected than larger by encapsulation process technique and storage environment (steam).After traditional handicraft encapsulation shown in Fig. 2
Schematic diagram.
Content of the invention
For the problems referred to above, the present invention provides a kind of improved digital isolator coil and preparation method thereof, by improving
The horizontal direction of digital isolator coil is pressure, reduces by encapsulating and follow-up storage environment is affected.
The invention discloses a kind of improved digital isolator coil, it is characterised in that include：One wafer substrate；Once
Layer line circle, is arranged on the substrate；First insulating barrier, is arranged on the inner coil；One upper coil, overlaps
On the inner coil；Second insulating barrier, is arranged on the upper coil.
Reasonable be, invention further discloses a kind of improved digital isolator coil, it is characterised in that bag
Include：
First insulating barrier and the second insulating barrier include polymolecular polymer.
Reasonable be, invention further discloses a kind of improved digital isolator coil, it is characterised in that bag
Include：
The polymolecular polymer includes polyimides.
The present invention further discloses a kind of method of digital isolator coil, it is characterised in that include：
Step one, provides the wafer substrate comprising the inner coil；
Step 2, in the first insulating barrier described in the wafer deposition on substrate；
Step 3, one inculating crystal layer of local deposits on first insulating barrier；
Step 4, on the inculating crystal layer, one pattern of lithographic definition, the pattern is Chong Die with the inner coil；
Step 5, deposits a metal level in the photoetching position of the step 4；
Step 6, removes first insulating barrier of step 2, retains the metal level；
Step 7, removes the inculating crystal layer of step 3, retains the metal level；
Step 8, the metal level of the reservation constitutes the upper coil, the upper and lower layer line circle overlap to form described every
Offline circle；
Step 9, deposits the second insulating barrier on the upper coil.
Reasonable be, invention further discloses a kind of method of digital isolator coil, it is characterised in that bag
Include：
The thickness of second insulating barrier is 2um～10um, and the thickness of first insulating barrier is 10～20um.
Reasonable be, invention further discloses a kind of method of digital isolator coil, it is characterised in that bag
Include：The upper coil include gold, copper, nickel,.
The isolation capacity of horizontal direction is invention not only improves, reduces the shadow of back segment packaging technology or storage environment
Ring, and the area of chip is reduced, reduce cost.
Description of the drawings
Below, referring to the drawings, for those skilled in the art, from retouching in detail to the present invention and its method
In stating, the above and other objects, features and advantages of the present invention will be evident that.
Fig. 1 is the schematic diagram of the digital isolator levels coil lead of prior art；
Fig. 2 is the schematic diagram using digital isolator coil after prior art encapsulation；
Fig. 3 illustrates the flow sheet of the present invention.
Reference
11 --- upper coil lead
12 --- inner coil lead
Specific embodiment
Now with detailed reference to Description of Drawings embodiment of the disclosure.Present being preferable to carry out with detailed reference to the disclosure
Example, its example is shown in the drawings.In the case of any possible, phase will be represented using identical labelling in all of the figs
Same or similar part.Additionally, the term although used in the disclosure is selected from public term, but this
Some terms mentioned in prospectus are probably that applicant carrys out selection by his or her judgement, and its detailed meanings is at this
Explanation in the relevant portion of the description of text.In addition, it is desirable to not only by the actual terms for being used, and be also to by each
The meaning contained by term is understanding the disclosure.
Fig. 3 is referred to, the production technological process of the present invention is shown, in conjunction with the figure, each step is described：
Step 1, provides a wafer substrate comprising inner coil；
Step 2, depositing first insulator layer over the substrate, the insulating barrier generally adopts polymolecular polymer P I, i.e. polyamides
Imines (Polimide), PI OPEN photo (protective layer windowing) is used for routing；
Step 3, by UBM technique local deposits inculating crystal layer；
Step 4, using the pattern of lithographic definition upper coil, the pattern is Chong Die with inner coil；
Step 5, deposits a metal level in the photoetching position of step 4, and typically Au, to form upper coil；
Step 6, removes the insulating barrier in step 2, and the insulating barrier in addition to metal level is all removed；
Step 7, etches away inculating crystal layer, the upper coil being made up of metal Au of reservation；
Step 8, forms completely overlapped upper and lower layer line circle, as retarder；
Step 9, deposits the second insulating barrier on upper coil, still adopts polymolecular polymer P I, i.e. polyimides
(Polimide).
Lower layer line is drawn on the digital isolator retarder for being ultimately formed by above-mentioned technique, such upper coil and side
It is also PI isolation between the pad of circle, rather than molding powder machine or air insulated, so, spacing between the two can be narrowed down to
20um.
In above-mentioned steps, the PI thickness for depositing the second insulating barrier is 2um～10um, to cover second layer coil as mesh
Mark.
By increase one procedure, using the second insulating barrier PI rather than plastic packaging glue in same level difference electricity
Position metal level is completely cut off.The isolation capacity of horizontal direction is so not only improved, reduces back segment packaging technology or storage ring
The impact in border, and the area of chip is reduced, reduce cost.
The description to preferred embodiment provided above so that any technical staff in the art can using or using this
Invention.Various modifications to these embodiments are evident for personnel skilled in the art, can be described here total
Principle be applied to other embodiment and do not use creativeness.Thus, the present invention is not limited to embodiment depicted herein, and answers
According to the widest range for meeting teachings disclosed herein and new feature.
Claims (6)
1. a kind of improved digital isolator coil, it is characterised in that include：
One wafer substrate；
One inner coil, is arranged on the substrate；
First insulating barrier, is arranged on the inner coil；
One upper coil, overlaps on the inner coil；
Second insulating barrier, is arranged on the upper coil.
2. improved digital isolator coil according to claim 1, it is characterised in that include：
First insulating barrier and the second insulating barrier include polymolecular polymer.
3. improved digital isolator coil according to claim 1, it is characterised in that
The polymolecular polymer includes polyimides.
4. a kind of method for making according to any one of claims 1 to 3 digital isolator coil, it is characterised in that
Including：
Step one, provides the wafer substrate comprising the inner coil；
Step 2, in the first insulating barrier described in the wafer deposition on substrate；
Step 3, one inculating crystal layer of local deposits on first insulating barrier；
Step 4, on the inculating crystal layer, one pattern of lithographic definition, the pattern is Chong Die with the inner coil；
Step 5, deposits a metal level in the photoetching position of the step 4；
Step 6, removes first insulating barrier of step 2, retains the metal level；
Step 7, removes the inculating crystal layer of step 3, retains the metal level；
Step 8, the metal level of the reservation constitutes the upper coil, and the upper and lower layer line circle overlaps to form the shielding wire
Circle；
Step 9, deposits the second insulating barrier on the upper coil.
5. the method for digital isolator coil according to claim 4, it is characterised in that include：
The thickness of second insulating barrier is 2um～10um, and the thickness of first insulating barrier is 10～20um.
6. the method for digital isolator coil according to claim 5, it is characterised in that include：
The upper coil include gold, copper, nickel,.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610948113.3A CN106449441B (en) | 2016-10-26 | 2016-10-26 | A kind of improved digital isolator coil and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610948113.3A CN106449441B (en) | 2016-10-26 | 2016-10-26 | A kind of improved digital isolator coil and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106449441A true CN106449441A (en) | 2017-02-22 |
| CN106449441B CN106449441B (en) | 2019-02-12 |
Family
ID=58178799
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610948113.3A Expired - Fee Related CN106449441B (en) | 2016-10-26 | 2016-10-26 | A kind of improved digital isolator coil and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106449441B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5852866A (en) * | 1996-04-04 | 1998-12-29 | Robert Bosch Gmbh | Process for producing microcoils and microtransformers |
| JP2002057032A (en) * | 2000-08-10 | 2002-02-22 | Nippon Shokubai Co Ltd | Thin film magnetic device |
| US20150061813A1 (en) * | 2013-08-30 | 2015-03-05 | Qualcomm Incorporated | Varying thickness inductor |
| CN104517941A (en) * | 2013-09-29 | 2015-04-15 | 澜起科技（上海）有限公司 | Coil applied to inductance components and method for manufacturing coil |
-
2016
- 2016-10-26 CN CN201610948113.3A patent/CN106449441B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5852866A (en) * | 1996-04-04 | 1998-12-29 | Robert Bosch Gmbh | Process for producing microcoils and microtransformers |
| JP2002057032A (en) * | 2000-08-10 | 2002-02-22 | Nippon Shokubai Co Ltd | Thin film magnetic device |
| US20150061813A1 (en) * | 2013-08-30 | 2015-03-05 | Qualcomm Incorporated | Varying thickness inductor |
| CN104517941A (en) * | 2013-09-29 | 2015-04-15 | 澜起科技（上海）有限公司 | Coil applied to inductance components and method for manufacturing coil |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106449441B (en) | 2019-02-12 |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20190212 Termination date: 20211026 |
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| CF01 | Termination of patent right due to non-payment of annual fee |