CN106449400B - The method that short circuit caused by metal layer itself defect is leaked electricity before eliminating - Google Patents
The method that short circuit caused by metal layer itself defect is leaked electricity before eliminating Download PDFInfo
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- CN106449400B CN106449400B CN201610984912.6A CN201610984912A CN106449400B CN 106449400 B CN106449400 B CN 106449400B CN 201610984912 A CN201610984912 A CN 201610984912A CN 106449400 B CN106449400 B CN 106449400B
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 65
- 239000002184 metal Substances 0.000 title claims abstract description 65
- 238000000034 method Methods 0.000 title claims abstract description 59
- 230000007547 defect Effects 0.000 title claims abstract description 27
- 230000005611 electricity Effects 0.000 title claims description 19
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 44
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 44
- 239000010937 tungsten Substances 0.000 claims abstract description 44
- 230000008030 elimination Effects 0.000 claims abstract description 21
- 238000003379 elimination reaction Methods 0.000 claims abstract description 21
- 230000008569 process Effects 0.000 claims abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- 239000010703 silicon Substances 0.000 claims abstract description 15
- 238000000231 atomic layer deposition Methods 0.000 claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 14
- 229920005591 polysilicon Polymers 0.000 claims abstract description 14
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 238000001259 photo etching Methods 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 7
- 238000003701 mechanical milling Methods 0.000 claims description 5
- 239000003989 dielectric material Substances 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 230000015654 memory Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 241000416536 Euproctis pseudoconspersa Species 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000035755 proliferation Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides the methods of the electric leakage of short circuit caused by metal layer itself defect before a kind of elimination, comprising: polysilicon gate first step: is formed on silicon wafer；Second step: metal layer is before depositing on silicon wafer to be completely covered polysilicon gate；Third step: preceding metal layer is ground and is thinned at the predetermined thickness above polysilicon gate；Four steps: opening hole between the position that will carry out tungsten vias by photoetching and dry etch process, wherein the width of the through-hole makes the through-hole with the tungsten through-hole that will be opened with Chong Die；5th step: atomic layer deposition is executed, to fill up the through-hole；6th step: so that preceding metal layer grows into the required thickness of tungsten via etch；7th step: tungsten via etch is carried out to the preceding metal layer after growth；8th step: tungsten fill process is carried out in tungsten through-hole.
Description
Technical field
The present invention relates to field of semiconductor manufacture, it is more particularly related to which metal layer itself lacks before a kind of elimination
The method of short circuit electric leakage caused by falling into.
Background technique
The preceding metal layer fill process of nor gate flash memories memory cell areas cannot have cavity blemish or weak spot,
It otherwise, can be because adjacent drain leads to electric leakage, breakdown or short circuit there are voltage difference in reading or erasing.
Existing fill process is mainly that high-density plasma technique (HDP, High Density Plasma) and profundity are wide
Than technique (HARP, High Aspect Ratio Process)；From filling principle, both techniques are all easy to more
Hole or weak spot are formed in groove between crystal silicon grid (floating gate and control gate).This weak spot is laterally to deposit in the trench
?；Therefore, in both sides making alive, i.e., electric leakage, short circuit or breakdown be will result in when draining making alive.
For filling the higher structure of difficulty, simple by adjusting fill process, it is particularly difficult to eliminate in preceding metal layer channel
Weak spot, and because memory cell areas area is huge, it is difficult to process monitoring is carried out to this weak spot by effective method
And inspection, therefore this weak spot will lead to apparent yield loss.
Accordingly, it is desirable to be capable of providing a kind of method that can be eliminated short circuit caused by preceding metal layer itself defect and leak electricity.
Summary of the invention
The technical problem to be solved by the present invention is to for drawbacks described above exists in the prior art, providing one kind can be eliminated
The method of the electric leakage of short circuit caused by preceding metal layer itself defect.
In order to achieve the above technical purposes, according to the present invention, it provides before a kind of elimination caused by metal layer itself defect
The method of short circuit electric leakage, comprising:
First step: polysilicon gate is formed on silicon wafer；
Second step: metal layer is before depositing on silicon wafer to be completely covered polysilicon gate；
Third step: preceding metal layer is ground and is thinned at the predetermined thickness above polysilicon gate；
Four steps: opening hole between the position that will carry out tungsten vias by photoetching and dry etch process,
Wherein the width of the through-hole has the through-hole with the tungsten through-hole that will be opened Chong Die；
5th step: atomic layer deposition is executed, to fill up the through-hole；
6th step: so that preceding metal layer grows into the required thickness of tungsten via etch；
7th step: tungsten via etch is carried out to the preceding metal layer after growth；
8th step: tungsten fill process is carried out in tungsten through-hole.
Preferably, in the method that short circuit caused by metal layer itself defect is leaked electricity before the elimination, in first step,
Shallow trench isolation is formed in silicon wafer to separate the active area in silicon wafer.
Preferably, in the method that short circuit caused by metal layer itself defect is leaked electricity before the elimination, third step is used
Preceding metal layer is ground and is thinned by chemical mechanical milling tech.
Preferably, in the method that short circuit caused by metal layer itself defect is leaked electricity before the elimination, in third step,
Predetermined thickness is between 500A~1000A.
Preferably, in the method that short circuit caused by metal layer itself defect is leaked electricity before the elimination, in four steps, institute
The width for stating through-hole makes the through-hole have the overlapping of predetermined area with the tungsten through-hole that will be opened.
Preferably, in the method that short circuit caused by metal layer itself defect is leaked electricity before the elimination, in four steps,
Make etch stop using etching stopping layer, so that etch stop is in etching stopping layer.
Preferably, in the method that short circuit caused by metal layer itself defect is leaked electricity before the elimination, the 6th step is used
Thickness needed for metal layer grows into tungsten via etch before being made using PETEOS technique.
Preferably, in the method that short circuit caused by metal layer itself defect is leaked electricity before the elimination, in the 6th step,
So that preceding metal layer is grown into after the required thickness of tungsten via etch, using chemical mechanical milling tech to the preceding gold after growth
Belong to layer to be ground.
The present invention is by applying the method for atomic layer deposition to deposit film in the aperture between tungsten through-hole, thus before instead
The dielectric material with lateral weak spot between polysilicon gate that preceding metal layer fill process generates, avoids adjacent drain electrode
Electric leakage, breakdown or short circuit between tungsten through-hole at work.
Detailed description of the invention
In conjunction with attached drawing, and by reference to following detailed description, it will more easily have more complete understanding to the present invention
And its adjoint advantage and feature is more easily to understand, in which:
Fig. 1 schematically shows short circuit caused by metal layer itself defect before elimination according to the preferred embodiment of the invention
The flow chart of the method for electric leakage.
It should be noted that attached drawing is not intended to limit the present invention for illustrating the present invention.Note that indicating that the attached drawing of structure can
It can be not necessarily drawn to scale.Also, in attached drawing, same or similar element indicates same or similar label.
Specific embodiment
In order to keep the contents of the present invention more clear and understandable, combined with specific embodiments below with attached drawing in of the invention
Appearance is described in detail.
In the present invention, after preceding metal layer (PMD, Pre-Metal Dielectric) fill process, with chemical machine
Preceding metal layer is ground and is thinned to above polysilicon by tool grinding (CMP, Chemical Mechanical Polish) technique
500A~1000A opens hole between the position that will carry out tungsten vias by photoetching and dry etch process, and etching stops
Only at etching stopping layer (CESL, Contact Etch Stop Layer), guarantees the width of this through-hole, make it and will open
Tungsten through-hole have enough overlappings.Deposited atom layer deposit (ALD, Atom Layer Deposition), makes it in this through-hole
Fill up through-hole.Atomic layer deposition processes are the technique of isotropism conformal growth, not will form when growing in through-holes lateral
Defect or weak spot.Thus, originally just led to by the atomic layer deposition of no lateral weak spot in the presence of the dielectric layer of lateral weak spot
Hole replaces.Preceding metal layer is grown to using PETEOS (plasma enhancing ethyl orthosilicate) technique the height of needs later
(reapplying CMP process if necessary to be ground).Continue tungsten through-hole in the preceding metal layer repaired and tungsten is filled out
Fill technique.Guarantee that the material between tungsten through-hole is all substituted by the atomic layer deposition through-hole without lateral weak spot in this way.
Fig. 1 schematically shows short circuit caused by metal layer itself defect before elimination according to the preferred embodiment of the invention
The flow chart of the method for electric leakage.
As shown in Figure 1, the electric leakage of short circuit caused by metal layer itself defect before elimination according to the preferred embodiment of the invention
Method includes:
First step S1: polysilicon gate is formed on silicon wafer；Generally, shallow trench isolation is formed also in silicon wafer so as to by silicon
Active area in piece separates.
Second step S2: metal layer is before depositing on silicon wafer to be completely covered polysilicon gate；
Third step S3: preceding metal layer is ground and is thinned at the predetermined thickness above polysilicon gate；
For example, preceding metal layer is ground and is thinned using chemical mechanical milling tech by third step.For example, in third step
In rapid, predetermined thickness is between 500A~1000A.
Four steps S4: open-minded between the position that will carry out tungsten vias by photoetching and dry etch process
Hole, wherein the width of the through-hole has the through-hole (preferably enough heavy with Chong Die with the tungsten through-hole that will be opened
It is folded)；For example, the width of the through-hole makes the through-hole have the overlapping of predetermined area with the tungsten through-hole that will be opened.
For example, making etch stop using etching stopping layer, i.e., etch stop is in etching stopping layer in four steps.
5th step S5: atomic layer deposition is executed, to fill up the through-hole；
Atomic layer deposition processes are the technique of isotropism conformal growth, not will form lateral lack when growing in through-holes
Sunken or weak spot.Thus, originally there is the dielectric layer of lateral weak spot just by the atomic layer deposition through-hole of no lateral weak spot
It replaces.
6th step S6: so that preceding metal layer grows into the required thickness of tungsten via etch；
For example, the 6th step uses thickness needed for making preceding metal layer grow into tungsten via etch using PETEOS technique
Degree.
Preferably, in the 6th step, metal layer is grown into after the required thickness of tungsten via etch before making, and utilizes change
Mechanical milling tech is learned to grind the preceding metal layer after growth.
7th step S7: tungsten via etch is carried out to the preceding metal layer after growth；
8th step S8: tungsten fill process is carried out in tungsten through-hole.Guarantee the material between tungsten through-hole all by nothing in this way
The atomic layer deposition through-hole of lateral weak spot substitutes.
It, can as a result, by substituting original preceding metal layer thin film that there is lateral weak spot using atomic layer deposition through-hole
So that, without transverse direction weak spot between tungsten through-hole, tungsten and its adhesion layer horizontal proliferation are avoided after the filling of tungsten through-hole, thus
Avoid electric leakage caused by after drain electrode pressurization, breakdown or short circuit.It ensure that yield and reliability.
The present invention will have the defects that lateral material is replaced with atomic layer deposition film between preceding metal layer groove, thus from root
The defect of lateral thin dielectric weakness is eliminated in sheet, so as to avoid the leakage between the drain electrode of memory cell areas under elevated pressure
The phenomenon of electricity, breakdown or short circuit, improves yield and reliability.
In addition, it should be noted that, unless stated otherwise or point out, the otherwise term " first " in specification, "
Two ", the descriptions such as " third " are used only for distinguishing various components, element, the step etc. in specification, each without being intended to indicate that
Component, element, the logical relation between step or ordinal relation etc..
It is understood that although the present invention has been disclosed in the preferred embodiments as above, above-described embodiment not to
Limit the present invention.For any person skilled in the art, without departing from the scope of the technical proposal of the invention,
Many possible changes and modifications all are made to technical solution of the present invention using the technology contents of the disclosure above, or are revised as
With the equivalent embodiment of variation.Therefore, anything that does not depart from the technical scheme of the invention are right according to the technical essence of the invention
Any simple modifications, equivalents, and modifications made for any of the above embodiments still fall within the range of technical solution of the present invention protection
It is interior.
And it should also be understood that the present invention is not limited thereto and locate the specific method described, compound, material, system
Technology, usage and application are made, they can change.It should also be understood that term described herein be used merely to describe it is specific
Embodiment, rather than be used to limit the scope of the invention.Must be noted that herein and appended claims used in
Singular "one", "an" and "the" include complex reference, unless context explicitly indicates that contrary.Therefore, example
Such as, the citation to one or more elements is meaned to the citation of " element ", and including known to those skilled in the art
Its equivalent.Similarly, as another example, the citation of " step " or " device " is meaned to one or
The citation of multiple steps or device, and may include secondary step and second unit.It should be managed with broadest meaning
All conjunctions that solution uses.Therefore, word "or" should be understood that the definition with logical "or", rather than logical exclusive-OR
Definition, unless context explicitly indicates that contrary.Structure described herein will be understood as the function of also quoting from the structure
Equivalent.It can be interpreted that approximate language should be understood like that, unless context explicitly indicates that contrary.
Claims (8)
1. a kind of method that short circuit caused by metal layer itself defect is leaked electricity before elimination, characterized by comprising:
First step: polysilicon gate is formed on silicon wafer；
Second step: carrying out the deposit of first time dielectric material, and metal layer is before depositing on silicon wafer to be completely covered polysilicon gate；
Third step: preceding metal layer being ground and is thinned at the predetermined thickness above polysilicon gate, metal layer before obtaining first；
Four steps: will be carried out in metal layer before first by photoetching and dry etch process tungsten vias position it
Between open hole, wherein to have the through-hole with the tungsten through-hole that will open Chong Die for the width of the through-hole；
5th step: carrying out second of dielectric material deposit, atomic layer deposition is executed, to fill up the through-hole；
6th step: carrying out the deposit of third time dielectric material, metal layer before forming second on metal layer before first, so that preceding gold
Belong to the required thickness that layer grows into tungsten via etch；
7th step: tungsten via etch is carried out to the preceding metal layer after growth；
8th step: tungsten fill process is carried out in tungsten through-hole.
2. the method that short circuit caused by metal layer itself defect is leaked electricity before elimination according to claim 1, which is characterized in that
In first step, shallow trench isolation is formed in silicon wafer to separate the active area in silicon wafer.
3. the method that short circuit caused by metal layer itself defect is leaked electricity before elimination according to claim 1 or 2, feature exist
In preceding metal layer is ground and be thinned using chemical mechanical milling tech by third step.
4. the method that short circuit caused by metal layer itself defect is leaked electricity before elimination according to claim 1 or 2, feature exist
In in third step, predetermined thickness is between 500 angstroms~1000 angstroms.
5. the method that short circuit caused by metal layer itself defect is leaked electricity before elimination according to claim 1 or 2, feature exist
In in four steps, the width of the through-hole makes the through-hole have the overlapping of predetermined area with the tungsten through-hole that will be opened.
6. the method that short circuit caused by metal layer itself defect is leaked electricity before elimination according to claim 1 or 2, feature exist
In in four steps, making etch stop using etching stopping layer, so that etch stop is in etching stopping layer.
7. the method that short circuit caused by metal layer itself defect is leaked electricity before elimination according to claim 1 or 2, feature exist
In thickness needed for metal layer grows into tungsten via etch before the 6th step is made using PETEOS technique.
8. the method that short circuit caused by metal layer itself defect is leaked electricity before elimination according to claim 1 or 2, feature exist
In in the 6th step, metal layer is grown into after the required thickness of tungsten via etch before making, and utilizes chemical mechanical grinding work
Skill grinds the preceding metal layer after growth.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610984912.6A CN106449400B (en) | 2016-11-09 | 2016-11-09 | The method that short circuit caused by metal layer itself defect is leaked electricity before eliminating |
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| CN106449400B true CN106449400B (en) | 2019-09-17 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104617093A (en) * | 2013-11-05 | 2015-05-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN105789050A (en) * | 2014-12-24 | 2016-07-20 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6723597B2 (en) * | 2002-07-09 | 2004-04-20 | Micron Technology, Inc. | Method of using high-k dielectric materials to reduce soft errors in SRAM memory cells, and a device comprising same |
| US7115974B2 (en) * | 2004-04-27 | 2006-10-03 | Taiwan Semiconductor Manfacturing Company, Ltd. | Silicon oxycarbide and silicon carbonitride based materials for MOS devices |
| US20070218685A1 (en) * | 2006-03-17 | 2007-09-20 | Swaminathan Sivakumar | Method of forming trench contacts for MOS transistors |
| CN102082119B (en) * | 2010-11-16 | 2013-04-10 | 复旦大学 | Method for selectively depositing tungsten contact hole or through hole |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104617093A (en) * | 2013-11-05 | 2015-05-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN105789050A (en) * | 2014-12-24 | 2016-07-20 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
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