CN106445869A - FPGA (field programmable gate array) and PCIe (peripheral component interface express) based high-speed data exchange architecture - Google Patents
FPGA (field programmable gate array) and PCIe (peripheral component interface express) based high-speed data exchange architecture Download PDFInfo
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- CN106445869A CN106445869A CN201610833434.9A CN201610833434A CN106445869A CN 106445869 A CN106445869 A CN 106445869A CN 201610833434 A CN201610833434 A CN 201610833434A CN 106445869 A CN106445869 A CN 106445869A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
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- Data Exchanges In Wide-Area Networks (AREA)
- Multi Processors (AREA)
Abstract
The invention provides an FPGA (field programmable gate array) and PCIe (peripheral component interface express) based high-speed data exchange architecture. The high-speed data exchange architecture comprises a general or special computer platform and an FPGA chip based data exchange module; the data exchange module is provided with a PCIe hardcore connected with the computer platform through a PCIe bus and a dual-channel DMA (direct memory access) core connected with the PCIe hardcore, and a first DMA channel and a second DMA channel are arranged in the dual-channel DMA core; the first DMA channel is connected with an input processing module, and the second DMA channel is connected with an output processing module. The high-speed data exchange architecture has the advantages of high speed, high flexibility, diversified functions, low cost and high reliability.
Description
Technical field
The present invention relates to a kind of high-speed data based on FPGA and PCIe exchanges framework, belong to communication technical field, also fall within
In field of computer technology and Radar Technology field.
Background technology
With scientific and technical continuous progress, radar system, communication system, remote sensing system, image capturing system and high speed
Data collecting system etc. increasingly improves to data transmission rates demands, needs to hand over using the transfer bus of high speed and efficient data
Change framework to carry out data transmission.
PCI-Express (PCIe) is a kind of wide variety of very fast high-bandwidth transfer bus, is particularly suited for high speed number
According to transmission and exchange.For single system and slow data transmission, using adopting the technical scheme that PCIe carries out data transmission more
Special integrated chip（ASSP）Or the FPGA of simple framework is realizing.But, existing solution cannot meet complex data
The demand of exchange system, and have the shortcomings that speed is slow and very flexible.
Content of the invention
For overcome available data switching solution speed slow and very flexible shortcoming, for complex data exchange system
High speed data transfer, the present invention proposes a kind of high-speed data based on FPGA and PCIe and exchanges framework.
Technical solution of the present invention is as follows：
A kind of high-speed data based on FPGA and PCIe exchanges framework, and the data including computer platform with based on fpga chip is handed over
Die change block；
Described data exchange module is provided with the PCIe stone that PCIe bus is connected and hard with PCIe with computer platform
The binary channels DMA core that nuclear phase connects, is provided with DMA channel one and DMA channel two in described binary channels DMA core；
Described DMA channel one is connected with input processing module, and described DMA channel two is connected with output processing module.
As a further improvement on the present invention：Described input processing module includes the input being connected with DMA channel one
AXI4 bus, also include some Optical Receivers；It is defeated that each Optical Receivers is connected with one by the high-speed serial I/O of FPGA respectively
Enter fifo buffer, each input fifo buffer is turned AXI4 interface module by a FIFO respectively and is connected with input AXI4 bus
Connect.
As a further improvement on the present invention：The a width of 16bit of input bit of described input fifo buffer, carry-out bit is a width of
128bit.
As a further improvement on the present invention：Described output processing module is provided be connected with DMA channel two N number of defeated
Go out FIFO first-level buffer area, the data in described DMA channel two is divided into and N number of output FIFO one-level according to DMA interface address
Buffering area N road output data corresponding one by one, N road output data is respectively delivered to corresponding output FIFO first-level buffer
Qu Zhong；
Described output processing module is additionally provided with M output AXI4 one-level bus, and M is less than N, and described N number of output FIFO one-level is delayed
Rushing the output in area, to be divided into M group, each group corresponding and connect with an output AXI4 one-level bus respectively；
Each output AXI4 one-level bus is connected to a virtual fifo module, and described virtual fifo module is connected with one and is used for delaying
The DDR chip of deposit data, each virtual fifo module has been also respectively connected with output AXI4 secondary bus, bis- grades of described output AXI4
Bus is connected with some output FIFO Secondary buffer, and bis- grades of each output FIFO that described output AXI4 secondary bus are connected delays
Rush each output FIFO first-level buffer area one-to-one corresponding that area is connected with this output AXI4 secondary bus place branch road, thus will
The N road output data of DMA channel two output is respectively delivered to N number of output FIFO Secondary buffer through M virtual fifo module
In；
Each output FIFO Secondary buffer is connected to one for the pretreatment mould completing packet header detection and reject redundant information
Block；
Described output processing module is additionally provided with data simultaneous module, and each pretreatment module is all connected with described data simultaneous module
Connect, pass through high-speed serial I/O and the optical transmission module output of a FPGA through synchronous each road output data respectively；Or, respectively
The output data of pretreatment module without synchronous, pass sequentially through a high-speed serial I/O and optical transmission module output respectively.
As a further improvement on the present invention：The a width of 64bit of input bit of described output FIFO Secondary buffer, carry-out bit
A width of 256bit.
With respect to prior art, the present invention has advantages below：（1）This framework employs many AXI4 bus, multichannel data
The technological means such as parallel processing, big bit wide, multi-level buffer, multichannel virtual fifo and many DDR chip it is ensured that data parallel
High-speed transfer；（2）The present invention adopts computer system to process with outside multipath high-speed input processing module and multipath high-speed output
Module realizes data exchange jointly, disclosure satisfy that the demand of complex data exchange system；（3）This framework adopts binary channels DMA to tie
Structure, it can be avoided that the blocking effect of single DMA channel, and make input and output separate, it is independent of each other；（4）Speedy carding process number
According to can be synchronism output or asynchronous output；（5）Data exchange module is based on fpga chip, have flexibility strong,
Advantage vdiverse in function.
Brief description
Fig. 1 is the overall architecture schematic diagram of the present invention.
Fig. 2 is the framework schematic diagram of DMA channel one and input processing module part.
Fig. 3 is the framework schematic diagram of DMA channel two and output processing module part.
Specific embodiment
Describe technical scheme below in conjunction with the accompanying drawings in detail：
As Fig. 1, a kind of high-speed data exchange framework based on FPGA and PCIe, including computer platform（Including all-purpose computer
And special-purpose computer）With the data exchange module based on fpga chip；
Described data exchange module is provided with the PCIe stone that PCIe bus is connected with computer platform（I.e. PCIe X8
IP core）And the binary channels DMA core being connected with PCIe stone, it is provided with DMA channel one and DMA in described binary channels DMA core
Passage two；PCIe bus is connected to PCIe stone by the high-speed serial I/O in FPGA；
Described DMA channel one is connected with input processing module, and described DMA channel two is connected with output processing module.
As Fig. 2, in the present embodiment, provide a kind of input processing module of 4 tunnel inputs, described input processing module includes
The input AXI4 bus that is connected with DMA channel one, also include 4 Optical Receivers；Each Optical Receivers passes through FPGA respectively
High-speed serial I/O be connected with an input fifo buffer, each input fifo buffer turns AXI4 interface mould by a FIFO respectively
Block is connected with input AXI4 bus.
The a width of 16bit of input bit, a width of 128bit of carry-out bit of described input fifo buffer；
Outer input data sends into input FIFO buffering after the high speed serialization I O process of optical fiber, Optical Receivers and FPGA
Area, computer platform passes through PCIe bus, DMA channel one and input AXI4 bus and reads the data in input fifo buffer.
As Fig. 3, in the present embodiment, provide a kind of output processing module of 6 tunnel outputs, described output processing module setting
There are 6 be connected with DMA channel two and export FIFO first-level buffer area, the data in described DMA channel two is according to DMA interface ground
Location is divided into the 6 tunnel output datas corresponding one by one with 6 output FIFO first-level buffer areas, and 6 tunnel output datas are conveyed respectively
To in corresponding output FIFO first-level buffer area；
Described output processing module is additionally provided with 2 output AXI4 one-level buses, described 63, FIFO first-level buffer areas of output
Become one group, each group is corresponding with an output AXI4 one-level bus respectively and connects；
Each output AXI4 one-level bus is connected to virtual fifo module VFIFO_X3, and described virtual fifo module is connected with
One is used for caching the DDR3 chip of mass data, and each virtual fifo module has been also respectively connected with output AXI4 secondary bus, respectively
Output AXI4 secondary bus are connected to 3 output FIFO Secondary buffer, and described output AXI4 secondary bus are connected
Each output FIFO first-level buffer area that each output FIFO Secondary buffer is connected with this output AXI4 secondary bus place branch road
Correspond, thus the 6 tunnel output datas that DMA channel two is exported are respectively delivered to 6 outputs through 2 virtual fifo modules
In FIFO Secondary buffer；The a width of 64bit of input bit, a width of 256bit of carry-out bit of described output FIFO Secondary buffer；
Described output AXI4 one-level bus and output AXI4 secondary bus are respectively provided with AXI4-Stream function；
Each output FIFO Secondary buffer is connected to one for the pretreatment mould completing packet header detection and reject redundant information
Block；
Described output processing module is additionally provided with data simultaneous module, and each pretreatment module is all connected with described data simultaneous module
Connect, pass through high-speed serial I/O and the optical transmission module output of a FPGA through synchronous each road output data respectively；Or, respectively
The output data of pretreatment module without synchronous, pass sequentially through a high-speed serial I/O and optical transmission module output respectively.
This framework adopts binary channels DMA structure, it can be avoided that the blocking effect of single DMA channel, and make input and output phase
Mutually independent, it is independent of each other；Additionally use many AXI bus, multichannel data parallel transmission, big bit wide, multi-level buffer, multichannel void simultaneously
Intend the technological means such as FIFO and many DDR chip it is ensured that the parallel high-speed of data transmits.Through experimental verification, using this framework
Carry out data transmission, using PCIe2.0 bus, be configured to X8 form（8 parallel data channels）When, input data exchange rate
Up to 2.5GBps, output data exchange rate is up to 2.3GBps.
Claims (5)
1. a kind of high-speed data based on FPGA and PCIe exchange framework it is characterised in that：The described height based on FPGA and PCIe
Fast data exchange frameworks include computer platform and the data exchange module based on fpga chip；
Described data exchange module is provided with the PCIe stone that PCIe bus is connected and hard with PCIe with computer platform
The binary channels DMA core that nuclear phase connects, is provided with DMA channel one and DMA channel two in described binary channels DMA core；
Described DMA channel one is connected with input processing module, and described DMA channel two is connected with output processing module.
2. the high-speed data based on FPGA and PCIe as claimed in claim 1 exchange framework it is characterised in that：Described input
Input AXI4 bus that reason module includes being connected with DMA channel one, also include some Optical Receivers；Each Optical Receivers divides
An input fifo buffer is not connected with by the high-speed serial I/O of FPGA, each input fifo buffer is turned by a FIFO respectively
AXI4 interface module is connected with input AXI4 bus.
3. the high-speed data based on FPGA and PCIe as claimed in claim 2 exchange framework it is characterised in that：Described input
The a width of 16bit of input bit of fifo buffer, a width of 128bit of carry-out bit.
4. the described high-speed data based on FPGA and PCIe as arbitrary in claims 1 to 3 exchange framework it is characterised in that：Institute
State output processing module and be provided with the N number of output FIFO first-level buffer area being connected with DMA channel two, in described DMA channel two
Data the N road output data corresponding one by one with N number of output FIFO first-level buffer area, N road are divided into according to DMA interface address
Output data is respectively delivered in corresponding output FIFO first-level buffer area；
Described output processing module is additionally provided with M output AXI4 one-level bus, and M is less than N, and described N number of output FIFO one-level is delayed
Rushing the output in area, to be divided into M group, each group corresponding and connect with an output AXI4 one-level bus respectively；
Each output AXI4 one-level bus is connected to a virtual fifo module, and described virtual fifo module is connected with one and is used for delaying
The DDR chip of deposit data, each virtual fifo module has been also respectively connected with output AXI4 secondary bus, bis- grades of described output AXI4
Bus is connected with some output FIFO Secondary buffer, and bis- grades of each output FIFO that described output AXI4 secondary bus are connected delays
Rush each output FIFO first-level buffer area one-to-one corresponding that area is connected with this output AXI4 secondary bus place branch road, thus will
The N road output data of DMA channel two output is respectively delivered to N number of output FIFO Secondary buffer through M virtual fifo module
In；
Each output FIFO Secondary buffer is connected to one for the pretreatment mould completing packet header detection and reject redundant information
Block；
Described output processing module is additionally provided with data simultaneous module, and each pretreatment module is all connected with described data simultaneous module
Connect, pass through high-speed serial I/O and the optical transmission module output of a FPGA through synchronous each road output data respectively；Or, respectively
The output data of pretreatment module without synchronous, pass sequentially through a high-speed serial I/O and optical transmission module output respectively.
5. the high-speed data based on FPGA and PCIe as claimed in claim 4 exchange framework it is characterised in that：Described output
The a width of 64bit of input bit of FIFO Secondary buffer, a width of 256bit of carry-out bit.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108519857A (en) * | 2018-03-16 | 2018-09-11 | 中北大学 | Multi-source unformatted wideband data high speed magnanimity formats storage and feature security method |
| CN109388590A (en) * | 2018-09-28 | 2019-02-26 | 中国电子科技集团公司第五十二研究所 | Promote the dynamic buffering block management method and device of multi-channel DMA access performance |
| CN109975764A (en) * | 2019-03-19 | 2019-07-05 | 安徽雷炎电子科技有限公司 | A kind of transmission of general purpose radar integratedization high speed fibre and control interface plate and its application |
| CN113655956A (en) * | 2021-07-26 | 2021-11-16 | 武汉极目智能技术有限公司 | Method and system for high-bandwidth multi-channel data storage and reading unit based on FPGA and DDR4 |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201465562U (en) * | 2009-06-29 | 2010-05-12 | 北京理工大学 | Two-channel digital radiofrequency storage board |
| CN102185833A (en) * | 2011-03-30 | 2011-09-14 | 无锡众志和达存储技术有限公司 | Fiber channel (FC) input/output (I/O) parallel processing method based on field programmable gate array (FPGA) |
| CN103559156A (en) * | 2013-11-11 | 2014-02-05 | 北京大学 | Communication system between FPGA (field programmable gate array) and computer |
| CN204256732U (en) * | 2014-11-13 | 2015-04-08 | 海德盟数控技术（深圳）有限公司 | The high-speed data transmission apparatus of Based PC I-Express interface |
| CN105550133A (en) * | 2015-12-08 | 2016-05-04 | 天津津航计算技术研究所 | AXIS-FIFO bridge circuit based on ZYNQ and data transmission method using same |
-
2016
- 2016-09-20 CN CN201610833434.9A patent/CN106445869B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201465562U (en) * | 2009-06-29 | 2010-05-12 | 北京理工大学 | Two-channel digital radiofrequency storage board |
| CN102185833A (en) * | 2011-03-30 | 2011-09-14 | 无锡众志和达存储技术有限公司 | Fiber channel (FC) input/output (I/O) parallel processing method based on field programmable gate array (FPGA) |
| CN103559156A (en) * | 2013-11-11 | 2014-02-05 | 北京大学 | Communication system between FPGA (field programmable gate array) and computer |
| CN204256732U (en) * | 2014-11-13 | 2015-04-08 | 海德盟数控技术（深圳）有限公司 | The high-speed data transmission apparatus of Based PC I-Express interface |
| CN105550133A (en) * | 2015-12-08 | 2016-05-04 | 天津津航计算技术研究所 | AXIS-FIFO bridge circuit based on ZYNQ and data transmission method using same |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108519857A (en) * | 2018-03-16 | 2018-09-11 | 中北大学 | Multi-source unformatted wideband data high speed magnanimity formats storage and feature security method |
| CN109388590A (en) * | 2018-09-28 | 2019-02-26 | 中国电子科技集团公司第五十二研究所 | Promote the dynamic buffering block management method and device of multi-channel DMA access performance |
| CN109388590B (en) * | 2018-09-28 | 2021-02-26 | 中国电子科技集团公司第五十二研究所 | Dynamic cache block management method and device for improving multichannel DMA (direct memory access) access performance |
| CN109975764A (en) * | 2019-03-19 | 2019-07-05 | 安徽雷炎电子科技有限公司 | A kind of transmission of general purpose radar integratedization high speed fibre and control interface plate and its application |
| CN113655956A (en) * | 2021-07-26 | 2021-11-16 | 武汉极目智能技术有限公司 | Method and system for high-bandwidth multi-channel data storage and reading unit based on FPGA and DDR4 |
| CN113655956B (en) * | 2021-07-26 | 2024-02-02 | 武汉极目智能技术有限公司 | Method and system for high-bandwidth multi-channel data storage and reading unit based on FPGA and DDR4 |
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