CN106445748A - Verification method for triplication redundancy - Google Patents
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1608—Error detection by comparing the output signals of redundant hardware
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Abstract
The invention relates to a verification method for triplication redundancy. The method comprises the steps that (1) whether a triplication redundancy implementation mode of a field-programmable gate array (FPGA) is a mode based on a function route is determined, wherein the step (2) will be executed if the implementation mode is not based on the function route, and the step (3) will be executed if the mode is based on the function route; (2) the FPGA is processed, a triplication redundancy scope in the FPGA needing to be verified as well as the triplication redundancy implementation mode are determined, and the step (3) is executed; (3) the triplication redundancy implementation mode is classified and judged, wherein the step (4) will be executed if the implementation mode is structural triplication redundancy, and the step (5) will be executed if the implementation mode is time sequence triplication redundancy; (4) the structural triplication redundancy is verified; and (5) the time sequence triplication redundancy is verified. The verification method for the triplication redundancy provided by the invention has the advantages that verification efficiency is increased; verification for validity of the triplication redundancy implementation mode is more comprehensive and objective; and accuracy and reliability of the triplication redundancy verification method are enhanced.
Description
Technical field
The present invention relates to system detectio field, more particularly to a kind of triplication redundancy verification method.
Background technology
Triplication redundancy measure as simple and effective reliability reinforcement means in FPGA, be usually used in space flight, military project,
The systems such as nuclear industrial facility.With the lifting of integrated circuit fabrication process, with on-site programmable gate array FPGA as representative can
Programmed logic device scale exponentially increases, and triplication redundancy measure is also widely used in numerous areas.
For the advantage of triplication redundancy is given full play to, the triplication redundancy based on feature path in the engineer applied such as space flight, is explored
Optimal enforcement strategy, has not only used the redundancy approach of traditional circuit structure, i.e. structure triplication redundancy, belongs to space dimension
Reliability Strategy, and introduce the redundant operation mode that identical data is repeatedly received and dispatched in interface module, i.e. three mould of sequential is superfluous
Remaining, belong to time dimension Reliability Strategy.Used as the triplication redundancy implementation strategy for optimizing, the triplication redundancy based on feature path realizes stream
Journey can be summarized as：By sorting by significance level to fpga logic function, triplication redundancy measure is acted on to letter ground successively by numerous
In functional sequence, and further structure triplication redundancy and two kinds of embodiments of sequential triplication redundancy are selectively applied to each work(
Can be on the module that runs through of path or circuit.
In terms of FPGA triplication redundancy measure validation verification, traditional method is to realize result for structure triplication redundancy
Verified, inject in hardware fault or emulation etc. is under Condition of Strong Constraint, done to being verified FPGA internal register and carrying out physics
Relate to or simulate and overturn, do not consider the triplication redundancy mode based on feature path of industry application, do not take into account to sequential triplication redundancy
Test checking, do not include checking to particular cases such as one-channel signal and multiple signals, therefore, existing verification method has
Certain limitation, not enough comprehensively.
Content of the invention
The technical problem to be solved is for the deficiencies in the prior art, provides a kind of to triplication redundancy embodiment party
The method verified by the effectiveness of formula.
The technical scheme that the present invention solves above-mentioned technical problem is as follows：
A kind of triplication redundancy verification method, comprises the following steps：
Step 1, determine on-site programmable gate array FPGA triplication redundancy embodiment be whether based on feature path
Module or the triplication redundancy mode of circuit that mode, significance level including clearly each function and each feature path run through, if
The mode of feature path is not based on, then execution step 2, if the mode based on feature path, it is determined that the triplication redundancy
Interface and function sub-modules that embodiment includes, and execution step 3；
Step 2, to the FPGA process, determines the triplication redundancy scope for needing in the FPGA to be verified, and
Determine significance level and three moulds of the interface and function sub-modules for including in the range of the triplication redundancy for needing and being verified
Redundancy embodiment, and execution step 3；
Step 3, superfluous according to structure triplication redundancy embodiment and three mould of sequential respectively to the triplication redundancy embodiment
Remaining embodiment is classified, and the triplication redundancy embodiment is judged, if structure triplication redundancy, then executes step
Rapid 4, if sequential triplication redundancy, then execution step 5；
Step 4, verifies to the structure triplication redundancy, including determining the tool of the interface and the function sub-modules
Position of the body identifying object after sound code file, placement-and-routing in net meter file or fpga chip, and choose concrete identifying object
Circuit or depositor, then circuit or depositor are verified；
Step 5, verifies to the sequential triplication redundancy, sequential triplication redundancy is processed so as to which equivalence is considered as
Structure triplication redundancy, is then verified by structure triplication redundancy.
The invention has the beneficial effects as follows：By being whether the side based on feature path to the triplication redundancy embodiment of FPGA
Formula is judged, the FPGA is carried out processing, classifies, and has heightened verification efficiency, and triplication redundancy embodiment is sentenced
Disconnected, the judgement to structure triplication redundancy and sequential triplication redundancy is taken into account, for the checking of triplication redundancy embodiment effectiveness
More comprehensively objective, improve accuracy and the reliability of triplication redundancy verification method.
On the basis of technique scheme, the present invention can also do following improvement.
Further, in step 2, comprise the following steps：
Step 2.1, from the Core Feature of FPGA described in mission profile angle analysis, determines that what the Core Feature included connects
The all each self-contained significance level classifications of mouth and function sub-modules, the interface and function sub-modules；
Step 2.2, determines interface and the function sub-modules for having been carried out in the FPGA that triplication redundancy measure includes；
Step 2.3, the interface that the Core Feature is included and function sub-modules include with triplication redundancy measure is had been carried out
Interface and function sub-modules contrasted, take common factor part, obtain the triplication redundancy scope for needing to be verified；
Step 2.4, determines the weight of the interface for needing the triplication redundancy scope that is verified to include and function sub-modules
Want degree and triplication redundancy embodiment, and execution step 3.
Using the beneficial effect of above-mentioned further scheme it is：By to the FPGA process, determining that needs are tested
Interface and the significance level of function sub-modules and triplication redundancy embodiment that the triplication redundancy scope of card includes, can be more preferable
Ground is verified to the triplication redundancy embodiment for being not based on feature path.
Further, in step 3, by the triplication redundancy embodiment according to structure triplication redundancy embodiment and sequential
Triplication redundancy embodiment is classified, and by preset order, the sorted triplication redundancy embodiment is ranked up,
For example, preset order can be by the triplication redundancy order that determines by function significance level.
Using the beneficial effect of above-mentioned further scheme it is：By to triplication redundancy embodiment according to structure triplication redundancy
Embodiment and sequential triplication redundancy embodiment are classified, and improve verification efficiency.
Further, step 4 is comprised the following steps：
Step 4.1, determines the concrete identifying object of the interface and the function sub-modules in sound code file, placement-and-routing
Position in rear net meter file or fpga chip, and circuit or the depositor is located at by concrete identifying object is chosen, wherein, tool
Body identifying object includes input/output signal or voting machine；
Step 4.2, judges the signal type of input/output signal, if multiple signals, then execution step 4.3, if single
Road signal, then execution step 4.4；
The multiple signals are verified by step 4.3, until all circuits being selected or depositor are verified；
Step 4.4, verifies to the one-channel signal, until all circuits being selected or depositor are verified.
Further, the one-channel signal is the signal for transmitting 1 bit information, and the multiple signals compare for multiple transmission 1
The ordered set of the one-channel signal of special information.
Further, step 4.3 is comprised the following steps：
Step 4.3.1, when three mould values of multiple signals are different, optional 3 in the effective span of each mould
Different value, and 3 different values are randomly assigned to three moulds, output signal is obtained, and the output signal is put to the vote,
If the output signal after voting is that preset value, the triplication redundancy embodiment is effective, otherwise invalid；
Step 4.3.2, excludes the different situation of three mould values of multiple signals, the value of each mould signal is carried out about
Bundle, for example, it is assumed that when three mould value of multiple signals is different, value is respectively { x, y, z }, then enter each mould signal by value
After row constraint, value z is removed, value can be { x, y, y }；
Step 4.3.3, each mould equivalence is considered as one-channel signal, is verified by the verification method of one-channel signal.
Further, step 4.4 is comprised the following steps：
Step 4.4.1, the one-channel signal includes three mould signals, the side randomly selected by logical value 0 or 1 by each mould signal
Formula carries out fault simulation；
Step 4.4.2, obtains the one-channel signal all possible 8 kinds of states；
Step 4.4.3, the one-channel signal all put to the vote by voting machine by possible 8 kinds of states, separately verifies institute
State the effectiveness of triplication redundancy embodiment；
Step 4.4.4, the effectiveness of all triplication redundancy embodiments to obtaining carries out comprehensive analysis, completes checking.
Further, in step 5, comprise the following steps：
Three communication equivalences of the sequential triplication redundancy are considered as the redundancy in structure triplication redundancy by step 5.1 successively
Structure；
Step 5.2, the sequential triplication redundancy is verified according to the verification method of the structure triplication redundancy.
Using the beneficial effect of above-mentioned further scheme it is：By three communication equivalences of sequential triplication redundancy are considered as knot
Redundancy structure in structure triplication redundancy, can regard sequential triplication redundancy equivalence as structure triplication redundancy and be processed, make to three
The checking of mould redundancy is more objective comprehensively.
Further, if the triplication redundancy embodiment includes structure triplication redundancy and sequential triplication redundancy, first right
The sequential triplication redundancy is verified, then the structure triplication redundancy is verified.
The advantage of the aspect that the present invention is added will be set forth in part in the description, and partly will become from the following description
Obtain substantially, or recognized by present invention practice.
Description of the drawings
Fig. 1 is a kind of schematic flow sheet of triplication redundancy verification method provided in an embodiment of the present invention；
A kind of schematic flow sheet of triplication redundancy verification method that Fig. 2 is provided for another embodiment of the present invention；
A kind of process of triplication redundancy embodiment for being not based on feature path that Fig. 3 is provided for another embodiment of the present invention
The schematic flow sheet of method.
Specific embodiment
Below in conjunction with accompanying drawing, the principle of the present invention and feature are described, example is served only for explaining the present invention, and
Non- for limiting the scope of the present invention.
As shown in figure 1, for a kind of schematic flow sheet of triplication redundancy verification method provided in an embodiment of the present invention, the method
Including：
S101, determines that whether the triplication redundancy embodiment of on-site programmable gate array FPGA is the side based on feature path
Module or the triplication redundancy mode of circuit that formula, significance level including clearly each function and each feature path run through, if not
It is the mode based on feature path, then S102 is executed, if the mode based on feature path, then executes S103.
S102, to FPGA process, determines the triplication redundancy scope and triplication redundancy reality for needing to be verified in FPGA
Mode is applied, and executes S103.
S103, implements according to structure triplication redundancy embodiment and sequential triplication redundancy respectively to triplication redundancy embodiment
Mode is classified, and triplication redundancy embodiment is judged, if structure triplication redundancy, then executes S104, if when
Sequence triplication redundancy, then execute S105.
S104, verifies to structure triplication redundancy.
S105, verifies to sequential triplication redundancy.
To the triplication redundancy embodiment of FPGA whether a kind of triplication redundancy verification method that above-described embodiment is provided, by
It is to be judged based on the mode of feature path, FPGA is carried out processing, classifies, verification efficiency has been heightened, and to triplication redundancy
Embodiment is judged, has taken into account the judgement to structure triplication redundancy and sequential triplication redundancy, for triplication redundancy embodiment party
The checking of formula effectiveness is more comprehensively objective, improves accuracy and the reliability of triplication redundancy verification method.
In another embodiment, as shown in Figure 2, it is assumed that certain product is to be opened based on Xilinx company 2V3000 model FPGA
Send out, the FPGA realizes major function for numerical operation, secondary function is that data forwarding, miscellaneous function controls for indicator light switch,
Major function, secondary function and miscellaneous function are respectively defined as function A, function B and function C.To above-mentioned functions using being based on
The triplication redundancy embodiment of feature path, concrete measure is：The multiple signals type interface A-1 is related to by function A and multichannel letter
Number type data operation circuit A-2 carries out " sequential triplication redundancy " and " structure triplication redundancy " respectively；The single channel letter is related to by function B
Number type interface B-1 carries out " sequential triplication redundancy "；Function C does not implement triplication redundancy.
The present embodiment is comprised the following steps to the verification method of the triplication redundancy of 2V3000 model FPGA：
S201, determines the triplication redundancy embodiment for being verified object.In this example, FPGA is employed based on feature path
Triplication redundancy embodiment.
S202, classifies to triplication redundancy embodiment.In the present embodiment, to triplication redundancy embodiment respectively according to
Structure triplication redundancy embodiment and sequential triplication redundancy embodiment are classified, and respectively to sorted triplication redundancy reality
Apply mode by significance level classified in sequence, the logic function for needing to carry out triplication redundancy is A, B, therefore, by each work(
The interface that can relate to and module are A-1, A-2, B-1 by importance sorting, wherein, implement sequential triplication redundancy interface be A-1,
B-1, the module for implementing structure triplication redundancy is A-2, for interface A-1, B-1 for implementing sequential triplication redundancy, executes S203-
S205, for the module for implementing structure triplication redundancy, executes S206.
S203, verifies to structure triplication redundancy.Selecting circuit or depositor, and according to the circuit that chooses or depositor
Determine the positional information of concrete identifying object, the physical name including port input/output signal in RTL sound code file, signal
The information such as designation number, bit wide in the information, or net meter file of the voting machine after placement-and-routing such as name, signal bit wide, or respectively
Position area information (be only used for the verification method of physical fault injection) of the moding circuit in fpga chip.
Multiple signals are verified by S204.The positional information of the concrete identifying object for being determined according to S202, by A-2 mould
Each redundancy structure of block is labeled as A-2_R0, A-2_R1, A-2_R2, and the checking priority of A-2 module is set to as height.Because
Each mould signal of A-2 module is multiple signals, so special case situation different to three mould values first is verified,
Optional 3 different values in the effective span of each mould, respectively { 0,1, X }, wherein, X is in span, non-zero non-1 any
Value, span is determined according to the practical situation of multiple signals, for example, when multiple signals are for two-way, the span of X is two
Binary value 00～11.And 3 different values are randomly assigned to three moulds, output signal is obtained, and the output signal is carried out
Voting, if the output signal after voting is that preset value, triplication redundancy embodiment is effective, if during other values, then three moulds are superfluous
Remaining embodiment is invalid.
S205, verifies to one-channel signal.After verifying to special case situation, special case situation is excluded, by multiple signals
Each mould signal value be constrained to " type 0 " and " Class1 ", and by above-mentioned value type equivalence for one-channel signal signal logic
Value " logical zero " and " logic 1 ", are processed by one-channel signal to A-2 module：" logic 1 " is made to represent normal, " logical zero " table
Show fault, then by each mould signal in the way of logical value 0 or 1 is randomly selected simulated failure, all possible to three mould signals
2*2*2=8 kind state does ergodic checking, is decided by vote by voting machine, obtains the effective of triplication redundancy embodiment under 8 kinds of states
Property conclusion, then in conjunction with the effectiveness of triplication redundancy embodiment in the case of special case, comprehensive descision, it was therefore concluded that, concrete outcome
With reference to following table.
S206, verifies to sequential triplication redundancy.By call duration time precedence, sequentially logical by three times of A-1 interface
Beacon is designated as A-1_Tr0, A-1_Tr1, A-1_Tr2, and the checking priority of A-1 interface is set to height；Then sequentially B-1 is connect
Three communication marks of mouth are B-1_Tr0, B-1_Tr1, B-1_Tr2, and the checking priority of B-1 interface are set to low.Above-mentioned
Suffix can be equal to for the communication marks of " _ Tr0 (the first mould), _ Tr1 (the second mould), _ Tr2 (the 3rd mould) " in subsequent treatment
Redundancy structure labelling " _ R0 (the first mould), _ R1 (the second mould), _ R2 (the 3rd mould) " in structure triplication redundancy, then presses S203
The step of～S205, is verified.
S207, checking is completed.If necessary, can be excellent only for selected checking according to external conditions such as the cost of checking, progresses
The interface of first level or module are verified, improve checking task performance.
In another embodiment, as shown in Figure 3, it is assumed that the triplication redundancy embodiment of the FPGA of certain company's production is not base
In the mode of feature path, then need to carry out which following process and verify, process step includes again：
S301, from the Core Feature of mission profile angle analysis FPGA, determines interface and function that Core Feature includes
Module；
S302, determines interface and the function sub-modules for having been carried out in FPGA that triplication redundancy measure includes；
S303, the interface that Core Feature is included and function sub-modules with have been carried out interface that triplication redundancy measure includes and
Function sub-modules are contrasted, and take common factor part, obtain the triplication redundancy scope for needing to be verified；
S304, determine the significance level of the interface and function sub-modules for needing the triplication redundancy scope verified to include with
And triplication redundancy embodiment.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all spirit in the present invention and
Within principle, any modification, equivalent substitution and improvement that is made etc., should be included within the scope of the present invention.
Claims (10)
1. a kind of triplication redundancy verification method, it is characterised in that comprise the following steps：
Step 1, determines that whether the triplication redundancy embodiment of on-site programmable gate array FPGA is the mode based on feature path,
If it is not, then execution step 2, if so, then execution step 3；
Step 2, to the FPGA process, determines that the triplication redundancy scope for needing to be verified in the FPGA and three moulds are superfluous
Remaining embodiment, and execution step 3；
Step 3, classifies to the triplication redundancy embodiment, and the triplication redundancy embodiment is judged, if
For structure triplication redundancy, then execution step 4, if sequential triplication redundancy, then execution step 5；
Step 4, verifies to the structure triplication redundancy；
Step 5, verifies to the sequential triplication redundancy.
2. a kind of triplication redundancy verification method according to claim 1, it is characterised in that in step 2, including following step
Suddenly：
Step 2.1, from the Core Feature of FPGA described in mission profile angle analysis, determine interface that the Core Feature includes and
Function sub-modules；
Step 2.2, determines interface and the function sub-modules for having been carried out in the FPGA that triplication redundancy measure includes；
Step 2.3, the interface that the Core Feature is included and function sub-modules and connecing of having been carried out that triplication redundancy measure includes
Mouth and function sub-modules are contrasted, and are taken common factor part, are obtained the triplication redundancy scope for needing to be verified；
Step 2.4, determines the important journey of the interface for needing the triplication redundancy scope that is verified to include and function sub-modules
Degree and triplication redundancy embodiment, and execution step 3.
3. a kind of triplication redundancy verification method according to claim 1, it is characterised in that in step 3, will be superfluous for three mould
Remaining embodiment is classified according to structure triplication redundancy embodiment and sequential triplication redundancy embodiment, and presses preset order
The sorted triplication redundancy embodiment is ranked up.
4. a kind of triplication redundancy verification method according to any one of claim 1 to 3, it is characterised in that in step 1,
If the triplication redundancy embodiment is the mode based on feature path, it is determined that the triplication redundancy embodiment includes
Interface and function sub-modules.
5. a kind of triplication redundancy verification method according to claim 4, it is characterised in that step 4 is comprised the following steps：
Step 4.1, determines the concrete identifying object of the interface and the function sub-modules；
Step 4.2, judges the signal type of the concrete identifying object, if multiple signals, then execution step 4.3, if single
Road signal, then execution step 4.4；
The multiple signals are verified by step 4.3；
Step 4.4, verifies to the one-channel signal.
6. a kind of triplication redundancy verification method according to claim 5, it is characterised in that the one-channel signal is transmission 1
The signal of bit information, the multiple signals are the ordered set of the one-channel signal of 1 bit information of multiple transmission.
7. a kind of triplication redundancy verification method according to claim 5, it is characterised in that step 4.3 is comprised the following steps：
Step 4.3.1, when three mould values of multiple signals are different, optional 3 differences in the effective span of each mould
Value, and 3 different values are randomly assigned to three moulds, output signal is obtained, and the output signal is put to the vote, if table
Output signal after certainly is preset value, then the triplication redundancy embodiment is effective, otherwise invalid；
Step 4.3.2, excludes the different situation of three mould values of multiple signals, the value of each mould signal is entered row constraint；
Step 4.3.3, each mould equivalence is considered as one-channel signal, is verified by the verification method of one-channel signal.
8. a kind of triplication redundancy verification method according to claim 5, it is characterised in that step 4.4 is comprised the following steps：
Step 4.4.1, the one-channel signal includes three mould signals, and each mould signal is entered in the way of logical value 0 or 1 is randomly selected
Row fault simulation；
Step 4.4.2, obtains the one-channel signal all possible 8 kinds of states；
Step 4.4.3, separately verifies the effectiveness of the triplication redundancy embodiment according to the 8 kinds of states for obtaining；
Step 4.4.4, the effectiveness of all triplication redundancy embodiments to obtaining carries out comprehensive analysis, completes checking.
9. a kind of triplication redundancy verification method according to any one of claim 1 to 3, it is characterised in that in step 5,
Comprise the following steps：
Three communication equivalences of the sequential triplication redundancy are considered as the redundancy structure in structure triplication redundancy by step 5.1 successively；
Step 5.2, the sequential triplication redundancy is verified according to the verification method of the structure triplication redundancy.
10. a kind of triplication redundancy verification method according to claim 1, it is characterised in that if the triplication redundancy is implemented
Mode includes structure triplication redundancy and sequential triplication redundancy, then first the sequential triplication redundancy is verified, then to the knot
Structure triplication redundancy is verified.
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| CN111914504A (en) * | 2020-07-17 | 2020-11-10 | 中科亿海微电子科技（苏州）有限公司 | Triple-modular redundancy method and device of application circuit |
| CN113962176A (en) * | 2021-12-22 | 2022-01-21 | 中科亿海微电子科技（苏州）有限公司 | Method and device for verifying correctness of netlist file subjected to triple modular redundancy processing |
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