CN106411294B - The clock pulse data recovery circuit and method of estimation shake tolerance - Google Patents
The clock pulse data recovery circuit and method of estimation shake tolerance Download PDFInfo
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- CN106411294B CN106411294B CN201510446353.9A CN201510446353A CN106411294B CN 106411294 B CN106411294 B CN 106411294B CN 201510446353 A CN201510446353 A CN 201510446353A CN 106411294 B CN106411294 B CN 106411294B
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Abstract
The present invention proposes the clock pulse data recovery circuit and method for estimating shake tolerance.Phase detector can generate first phase signal, and second phase signal is for generating clock signal.During operating mode, second phase signal is identical as first phase signal.During test pattern, timing can be started and first phase signal can be reversed to generate second phase signal.It is wrong when detecting data-signal during test pattern, timing can be stopped generating count value.Next, calculating tracking speed according to count value and default unit gap.In this way, which shake tolerance can be estimated rapidly.
Description
Technical field
The invention relates to a kind of clock pulse data recovery circuits, and can estimate shake tolerance in particular to a kind of
Clock pulse data recovery circuit.
Background technique
Tandem (serial) is two different communication modes with parallel (parallel), both are communicated in order to obtain
Benefit can use both topology (topologies) in some applications simultaneously.Also therefore, serializer (serializer) and solution
The needs of serializer (de-serializer) are also more and more.Clock pulse data recovery circuit is serializer/deserializer
(SerDes) a mould group important in system.In order to shake (jotter) present in tolerance system, clock pulse data recovery electricity
The shake tolerance that road must possess.It, in general must be in the input of high speed in measurement/analog dither tolerance
The shake of various amplitudes and frequency is injected in data stream, is then judged whether wrong in the data of reduction.However in this way
The practice have to devote a tremendous amount of time and computing resource.Therefore, how quickly and easily to estimate clock pulse data recovery electricity
The shake tolerance on road, is a topic of concern to those skilled in the art.
Summary of the invention
The embodiment of the present invention propose it is a kind of estimation shake tolerance clock pulse data recovery circuit, including phase detector,
Circuit for reversing, filter circuit, numerically-controlled oscillator, decision circuitry and counting circuit.Phase detector is to detect input
Phase difference between signal and clock signal is to export first phase signal.Circuit for reversing is coupled to phase detector, to
According to first phase signal and test mode signal to export second phase signal.Filter circuit is coupled to circuit for reversing, uses
To filter second phase signal to generate a digital controlled signal.Numerically-controlled oscillator is coupled to filter circuit, to root
Clock signal is generated according to digital controlled signal.Decision circuitry is to sample input signal according to clock signal to obtain a data
Signal.Counting circuit is coupled to decision circuitry, to judge whether data-signal occurs mistake.When test mode signal indicates
When operating mode, circuit for reversing setting second phase signal is identical to first phase signal.When test mode signal indicates to test
When mode, counting circuit starts timing and the reversed first phase signal of circuit for reversing to generate second phase signal.When surveying
When judging that mistake occurs for data-signal during die trial formula, counting circuit stops timing to generate an at least count value, and according to meter
Numerical value and a default unit gap calculate at least one tracking speed.
In one embodiment, above-mentioned circuit for reversing includes the first multiplexer, and first input end is coupled to detecting phase
Device, the second input terminal is anti-phase coupled to phase detector, and control terminal receives test mode signal.Work as test mode signal
When indicating operating mode, the first multiplexer selects first input end.When test mode signal indicates test pattern, the first multiplexing
Device selects the second input terminal.
In one embodiment, above-mentioned phase detector is positive and negative (Bang-Bang) phase detector, first phase signal
Number be 2.
In one embodiment, above-mentioned circuit for reversing further includes the second multiplexer and third multiplexer.Second multiplexer
First input end receives preset value, and the second input terminal is coupled to the output end of the first multiplexer.First input of third multiplexer
End is coupled to the output end of the first multiplexer, and the second input terminal receives preset value.
In one embodiment, above-mentioned filter circuit includes following circuits.The input terminal of proportional gain amplifier is coupled to
The output end of second multiplexer.The input terminal of integral gain amplifier is coupled to the output end of third multiplexer.Delay circuit
Input terminal is coupled to the output end of integral gain amplifier.The input terminal of adder is coupled to the output end of proportional gain amplifier
With the output end of delay circuit.
In one embodiment, during operating mode, the second multiplexer selects the second input terminal of the second multiplexer, and
The first input end of third multiplexer selection third multiplexer.In the first time section of test pattern, the selection of the second multiplexer
Second input terminal of the second multiplexer, and the second input terminal of third multiplexer selection third multiplexer.In test pattern
Second time interval, the second multiplexer selects the first input end of the second multiplexer, and third multiplexer selects third multiplexing
The first input end of device.
In one embodiment, above-mentioned count value includes the first count value and the second count value, and track speed include than
Example tracking speed and integral tracking speed.In the first time section of test pattern, when judging that mistake occurs for data-signal, meter
It calculates circuit and stops timing to generate the first count value, and ratio tracking is calculated according to the first count value and default unit gap
Speed.In the second time interval of test pattern, when judging that mistake occurs for data-signal, counting circuit stops timing to generate
Second count value, and integral tracking speed is calculated according to the second count value and default unit gap.
Exemplary embodiment of the invention proposes that a kind of clock pulse data recovery circuit of estimation shake tolerance, including phase are detectd
Survey device, circuit for reversing, charge pump, filter circuit, voltage-controlled oscillator, decision circuitry and counting circuit.Phase detector is
To detect the phase difference between an input signal and clock signal to export first phase signal.Circuit for reversing is coupled to phase
Position detector, to according to first phase signal and a test mode signal to export second phase signal.Charge pump is coupled to
To circuit for reversing and receive second phase signal.Filter circuit is coupled to the output end of charge pump to generate voltage control letter
Number.Voltage-controlled oscillator is coupled to filter circuit, to generate clock signal according to voltage control signal.Decision circuitry is
To sample input signal according to clock signal to obtain data-signal.Counting circuit is coupled to decision circuitry, to judge
Whether data-signal occurs mistake.When test mode signal indicates operating mode, circuit for reversing sets second phase signal phase
It is same as first phase signal.When test mode signal indicates test pattern, counting circuit starts timing, and circuit for reversing is anti-
To first phase signal to generate second phase signal.When judging that mistake occurs for data-signal during test pattern, calculate
Circuit stops timing to generate at least one count value, and calculates at least one tracking according to count value and default unit interval
Speed.
In one embodiment, above-mentioned circuit for reversing includes multiplexer.The first input end of this multiplexer is coupled to phase
Detector, the second input terminal are anti-phase coupled to phase detector, and control terminal receives test mode signal.Work as test mode signal
When indicating operating mode, multiplexer selects first input end to export second phase signal to charge pump.Work as test mode signal
When indicating test pattern, multiplexer selects the second input terminal to export second phase signal to charge pump.
In one embodiment, above-mentioned filter circuit includes filter and switch.The first end of filter is coupled to charging
Between pump and voltage-controlled oscillator, second end is coupled to ground terminal, and filter includes resistance and capacitor.Distinguish at the both ends of switch
It is coupled to the both ends of resistance.During operating mode, switch is off.In the first time section of test pattern, switch is to lead
It is logical.In the second time interval of test pattern, switch is off.
In one embodiment, above-mentioned count value includes the first count value and the second count value, and tracking speed includes integral
It tracks speed and ratio tracks speed.In the first time section of test pattern, when judging that mistake occurs for data-signal, calculate
Circuit stops timing to generate the first count value, and calculates integral tracking speed according to the first count value and default unit gap
Degree.In the second time interval of test pattern, when judging that mistake occurs for data-signal, counting circuit stops timing to generate the
Two count values, and ratio tracking speed is calculated according to the second count value, default unit gap and integral tracking speed.
The embodiment of the present invention proposes a kind of shake tolerance estimating and measuring method for clock pulse data recovery circuit.This clock pulse
Data recovery circuit includes phase detector, filter circuit, control oscillator and decision circuitry.Phase detector detecting input letter
Phase difference number between clock signal is to generate first phase signal.Filter circuit filters second phase signal to generate control
Signal.It controls oscillator and clock signal is generated according to control signal, decision circuitry samples input signal according to clock signal to take
Obtain data-signal.This shake tolerance estimating and measuring method includes: during operating mode, and setting second phase signal is identical to first
Phase signal；During test pattern, start timing and reversed first phase signal to generate second phase signal；Judge data
Whether signal occurs mistake；And when judge during test pattern data-signal occur mistake when, stop timing with generate to
A few count value, and speed is tracked according at least one is calculated during this count value and default unit.
In one embodiment, above-mentioned tracking speed includes that integral tracking speed and ratio track speed.Shake tolerance
Estimating and measuring method further include: generate analog input signal, set the amplitude and frequency of dither signal in analog input signal；According to product
Tracking speed, ratio tracking speed and analog input signal is divided to generate simulation clock signal；Judge analog input signal and simulation
Whether the phase difference between clock signal is less than default unit gap；If the phase between analog input signal and simulation clock signal
Potential difference is not less than default unit gap, adjusts the amplitude of dither signal to regenerate analog input signal；And if simulation is defeated
The phase difference for entering signal and simulating between clock signal is less than default unit gap, and the amplitude for setting dither signal corresponds to frequency
One shake tolerance of rate, and the frequency of dither signal is adjusted to regenerate analog input signal.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and cooperate appended attached drawing
It is described in detail below.
Detailed description of the invention
Fig. 1 is the circuit diagram for being painted clock pulse data recovery circuit according to first embodiment；
Fig. 2 is the waveform diagram of clock signal during being shown in test pattern according to first embodiment；
Fig. 3 is the schematic diagram for being painted trace ability according to first embodiment；
Fig. 4 is the circuit diagram for being painted clock pulse data recovery circuit according to second embodiment；
Fig. 5 is the timing diagram for being painted reset signal according to second embodiment；
Fig. 6 is the circuit diagram for being painted clock pulse data recovery circuit according to third embodiment；
Fig. 7 is the flow chart that shake tolerance estimating and measuring method is painted according to fourth embodiment；
Fig. 8 is the waveform diagram that dither signal and clock signal are painted according to fourth embodiment；
Fig. 9 is the flow chart that shake tolerance estimating and measuring method is painted according to fourth embodiment；
Figure 10 is that the schematic diagram for calculating shake tolerance is painted according to fourth embodiment.
Specific embodiment
About " first " used herein, " second " ... etc., not refer in particular to the meaning of order or cis-position, only
In order to distinguish with the element of same technique term description or operation.In addition, can refer to two about " coupling " used herein
Element is either directly or indirectly electrically connected.That is, when " the first object is coupled to the second object " is described below, the
Also settable other objects between one object and the second object.
[first embodiment]
Fig. 1 is the circuit diagram for being painted clock pulse data recovery circuit according to first embodiment.Please refer to Fig. 1, when rapid pulse
It include phase detector 110, circuit for reversing 120, filter circuit 130, numerically-controlled oscillator 140, judgement according to reflex circuit 100
Circuit 150 and counting circuit 160.
Phase detector 110 is to detect the phase difference between input signal 101 and clock signal 106 to export at least
One first phase signal 102.
Circuit for reversing 120 is coupled to phase detector 110, to be believed according to first phase signal 102 and test pattern
Numbers 103 to export at least one second phase signal 104.Second phase signal 104 can be identical or be in reverse to first phase signal
102, can be described in detail how to generate second phase signal 104 again below.
Filter circuit 130 is coupled to circuit for reversing 120, digital control to generate to filter second phase signal 104
Signal 105.Numerically-controlled oscillator 140 is coupled to filter circuit 130, to generate clock pulse according to digital controlled signal 105
Signal 106.Decision circuitry 150 is to sample input signal 101 according to clock signal 106 to obtain data-signal 107.Calculate electricity
Road 160 is coupled to decision circuitry 150, to judge whether data-signal 107 occurs mistake and calculate clock pulse data recovery electricity
The tracking speed 108 on road 100.
Clock pulse data recovery circuit 100 is operable in operating mode or test pattern.When test mode signal 103 indicates to transport
When operation mode, circuit for reversing 120 sets second phase signal 104 and is identical to first phase signal 102.On the other hand, work as test
When mode signal 103 indicates test pattern, the reversed first phase signal 102 of the meeting of circuit for reversing 120 is to generate second phase signal
104.Here, " reversed first phase signal 102 is to generate second phase signal 104 " is if refer to first phase signal 102
The phase for pointing out input signal 101 is to fall behind (or leading) clock signal 106, then second phase signal 104 would indicate that input letter
Numbers 101 phase is leading (or backwardness) clock signal 106.In some embodiments, phase detector 110 is positive and negative (Bang-
Bang) phase detector, and the number of first phase signal 102 is 2, respectively upper signal and lower signal.Upper signal and lower letter
Number can be used to point out input signal 101 be it is leading, lag behind clock signal 106, or point out the case where can not judging.Therefore, exist
Circuit for reversing 120 can exchange signal and lower signal using as second phase signal 104 during test pattern.For example, if
First phase signal 102 is logical one and " 0 ", then second phase signal 104 can be logical zero and " 1 " respectively.However, at it
Phase detector 110 is also possible to Hogge phase detector or other suitable phase detectors in his embodiment.In addition, this
Field has usually intellectual, when be appreciated that when using other kinds of phase detector how " reversed " first phase signal
102 to generate second phase signal 104, and the present invention is not restricted in the above embodiments.
It is during being shown in test pattern according to first embodiment please with reference to Fig. 2, Fig. 2 for another angle
The waveform diagram of clock signal.When clock signal 106 is locked during operating mode, clock signal 106 can have waveform
106a, the rising edge of waveform 106a is the rising edge for being aligned to input signal 101 at this time.However, during test pattern,
Since second phase signal 104 is to be in reverse to first phase signal 102, clock signal 106 can sequentially have waveform 106b
~106e, and the drop edge of waveform 106e is the rising edge for being aligned to input signal 101.
It is worth noting that, decision circuitry 150 is believed with clock pulse whether during operating mode or test pattern
Numbers 106 drop edge samples input signal 101 to obtain data-signal 107.During operating mode, clock signal 106
Drop edge can close to 101 pulse of input signal middle position to obtain correct data.However, in the test pattern phase
Between, the drop edge of clock signal 106 can be close to the rising edge of input signal 101, this occur that acquired data can
Mistake.In general, when the phase of clock signal 106 has the offset of 0.5 unit gap (unit interval, UI), data
Signal 107 just might have mistake.In addition, the tracking speed of arteries and veins data recovery circuit 100 is (that is, change clock signal 106 at that time
The speed of phase) it is faster when, data-signal 107 can faster generation mistake during test pattern.Therefore, in this embodiment,
Counting circuit 160 can obtain the data-signal 107 during test pattern and the mistake required time occurs to calculate clock pulse data time
At least one tracking speed of compound circuit 100.Specifically, when test mode signal 103 indicates test pattern, counting circuit
160 can start timing.When judging that mistake occurs for data-signal 107, counting circuit 160 can stop timing to generate a counting
Value, and at least one tracking speed is calculated according to this count value and default unit gap.In some embodiments, it presets single
Interdigit is divided into 0.5UI, but the present invention and not subject to the limits.
It is noted that can then establish different models when filter circuit 130 has different circuit structures and be chased after to calculate
Track speed.For example, referring to figure 3., wherein horizontal axis is the time, and the longitudinal axis is the offset of clock signal phase, the phase of 0.5UI
Position offset indicates that mistake can occur for data-signal 107.If it is 0 limited arteries and veins that filter circuit 130, which has a series (order),
Punching response (finite impulse response) filter, then the offset of 106 phase of clock signal is represented by curve 301.
If the series of finite impulse response filter is 1, the offset of 106 phase of clock signal is represented by curve 302.When obtaining
Between 311,312 with default unit gap (0.5UI) after, the parameter of curve 301,302 can be calculated (for example, multinomial
Coefficient in equation), these parameters are above-mentioned tracking speed.It is appreciated that however, one skilled in the art works as
How to be calculated according to default unit gap with above-mentioned count value when using different filter configurations other kinds of
Speed is tracked, the present invention is not restricted to the embodiment being previously mentioned in this exposure.
[second embodiment]
Fig. 4 is the circuit diagram for being painted clock pulse data recovery circuit according to second embodiment.In the fig. 4 embodiment, it inverts
Circuit 120 include multiplexer 401 (also known as the first multiplexer), multiplexer 402 (also known as the second multiplexer) and multiplexer 403 (also
Claim third multiplexer).And filter circuit 130 then includes proportional gain amplifier 411, integral gain amplifier 412, deferred telegram
Road 413 and adder 414.Counting circuit 160 includes checking circuit 421 and door 422 and counter 423.
The first input end of multiplexer 401 is coupled to phase detector 110, and the second input terminal is oppositely to be coupled to phase
Position detector 110, control terminal then receive test mode signal 103.The first input end of multiplexer 402 receives a preset value (example
For example 0), the second input terminal is coupled to the output end of multiplexer 401, and control terminal then receives ratio control signal 404.Multiplexer
403 first input end is coupled to the output end of multiplexer 401, and the second input terminal then receives preset value, and control terminal then receives product
Dividing control signal 405.The input terminal of proportional gain amplifier 411 is coupled to the output end of multiplexer 402.Integral gain amplification
The input terminal of device 412 is coupled to the output end of multiplexer 403.The input terminal of delay circuit 413 is coupled to integral gain amplification
The output end of device 412.The input terminal of adder 414 is coupled to the output end and delay circuit 413 of proportional gain amplifier 411
Output end.Check circuit 421 is to judge whether data-signal 107 wrong and output error signal 431.It is defeated with door 422
Reset signal 432 out is to reset counter 423.
During operating mode, proportional gain amplifier 411 and integral gain amplifier 412 can all be enabled.However, surveying
Die trial formula can be divided into two time intervals, and one of above-mentioned two gain amplifier meeting in each time interval
It is disabled to estimate the two of clock pulse data recovery circuit 100 tracking speed.
Specifically, when test mode signal 103 indicates operating mode, test mode signal 103 is logical zero, because
This multiplexer 401 can select first input end (labeled as " 0 ").In addition, ratio control signal 404 and integral control signal 405
It also is all logical one, therefore multiplexer 402 selects the second input terminal (being labeled as " 1 "), and the selection first of multiplexer 403 is defeated
Enter end (being labeled as " 1 ").Next, clock signal 106 can gradually be locked to input signal 101.
After clock signal 106 is locked to input signal 101, test mode signal 103, which can be enabled, (enters test
Mode).When test mode signal 103 indicates test pattern, test mode signal 103 is logical one, therefore multiplexer 401
It can select the second input terminal (labeled as " 1 ").In the first time section of test pattern, ratio control signal 404 is logic
" 1 ", and integral control signal 405 is logical zero, therefore multiplexer 402 can select the second input terminal, and 403 meeting of multiplexer
The second input terminal is selected, forbidden energy integral gain amplifier 412 is equal to.Next, clock signal 106 and input signal 101 it
Between phase difference will be increasing.
Signal timing diagram referring to figure 5., when judging that mistake occurs for data-signal 107, error signal 431 is logic
" 1 ", reset signal 432 is logical zero, and counter 432 can be reset (i.e. stopping timing) to generate the first count value
510.Next, please referring to back Fig. 4, counter 423 can calculate one according to the first count value and default unit gap
Ratio tracks speed.For example, counter 423 can calculate ratio tracking speed according to following equation (1).
Wherein t1For the first count value, KPSpeed is tracked for ratio, constant 0.5 is default unit gap.
After calculating ratio tracking speed, test mode signal 103 can be disabled to return to operating mode.In clock pulse
After signal 106 is locked, test mode signal 103 can be enabled once again to enter the second time interval of test pattern.This
When, counter 423 can start timing, and ratio control signal 404 is logical zero, and integral control signal 405 is logical one, because
This multiplexer 402 can select first input end, and multiplexer 403 can select first input end, and this equates the increasings of forbidden energy ratio
Beneficial amplifier 411.When judging that mistake occurs for data-signal 107, counter 423 can stop timing to generate the second count value,
And an integral tracking speed is calculated according to the second count value and default unit gap.For example, counter 423 can according to
Lower equation (2) calculates integral tracking speed.
Wherein t2For the second count value, KISpeed is tracked for integral.
According to above-mentioned ratio tracking speed and integral tracking speed, clock pulse data recovery circuit 100 can be calculated
Tracking input signal 101 have how soon.Specifically, clock pulse data recovery circuit 100 can be calculated according to following equation (3)
When tracking input signal 101, the phase change amount of clock signal 106, wherein t indicates the time.
[3rd embodiment]
Clock pulse data recovery circuit in a second embodiment is digital circuit, and clock pulse data are returned in the third embodiment
Compound circuit is analogous circuit, illustrates 3rd embodiment and second embodiment difference below.Fig. 6 is please referred to, Fig. 6 is according to
Three embodiments are painted the circuit diagram of clock pulse data recovery circuit.Clock pulse reflex circuit 600 includes phase detector 610, anti-
Shifting circuit 620, charge pump 630, filter circuit 640, voltage-controlled oscillator 650, decision circuitry 660 and counting circuit 670.
For example, positive and negative (bang-bang) phase detector of phase detector 610, to detect input signal 601 and when
Phase difference between arteries and veins signal 606 is to export first phase signal 602.Circuit for reversing 620 is coupled to phase detector 610, uses
To export second phase signal 604 according to first phase signal 602 and test mode signal 603.Charge pump 630 is coupled to instead
Shifting circuit 620 simultaneously receives second phase signal 604.Filter circuit 640 is coupled to the output end of charge pump 630 to generate voltage
Control signal 605.Voltage-controlled oscillator 650 is coupled to filter circuit 640, to be generated according to voltage control signal 605
Clock signal 606.Decision circuitry 660 is to sample input signal 601 according to clock signal 606 to obtain data-signal 604.Meter
It calculates circuit 670 and is coupled to decision circuitry 660, to judge whether data-signal 607 occurs mistake.
Similarly with first embodiment and second embodiment, when test mode signal 603 indicates operating mode, reversion
Circuit 620 can set second phase signal 604 and be identical to first phase signal 602.When test mode signal 603 indicates test mould
When formula, counting circuit 670 starts timing, and the reversed first phase signal 602 of the meeting of circuit for reversing 620 is to generate second phase letter
Numbers 604.When judging that mistake occurs for data-signal 607 during test pattern, counting circuit 670 can stop timing with generate to
A few count value, and at least one tracking speed is calculated according to count value.
For example, circuit for reversing 620 includes multiplexer 621.The first input end of multiplexer 621 is coupled to detecting phase
Device 610, the second input terminal are anti-phase coupled to phase detector 610, and control terminal receives test mode signal 603.Filter circuit
640 include filter 641 and switch 642.The first end of filter 641 is coupled to charge pump 630 and voltage-controlled oscillator 650
Between, second end is coupled to ground terminal.Filter 641 includes resistance R and capacitor C, and the both ends of switch 642 are respectively coupled to electricity
Hinder the both ends of R.Counting circuit 670 includes checking circuit 671 and door 672 and counter 673.Check circuit 671 to judge number
It is believed that whether numbers 607 wrong with output error signal 608.With two input terminals of door 672 receive test mode signal 603 with
Error signal 608 is to export reset signal 609.
When test mode signal 603 indicates operating mode, multiplexer 621 select first input end (be labeled as " 0 ") with
Second phase signal 604 is exported to charge pump 630, switch 642 ends at this time, so that 641 normal operation of filter.When following
Arteries and veins signal 606 can gradually be locked to input signal 601.
When test mode signal 603 indicates test pattern, multiplexer 621 select the second input terminal (be labeled as " 1 ") with
Second phase signal 604 is exported to charge pump 630.Test pattern is divided into two time intervals also to estimate in this embodiment
Track speed.In the first time section of test pattern, switch 642 is connected, and is equal to and the resistance value of resistance R is allowed to be 0, this is
For the path of integration of filter 641 to be generated.Next, the phase difference between clock signal 606 and input signal 601 can be got over
Come bigger.When judging that mistake occurs for data-signal 607, error signal 608 is logical one, and counter 673 stops timing to produce
Raw first count value, and counter 673 calculates integral tracking speed according to this first count value and default unit gap.It lifts
For example, counter 673 can calculate integral tracking speed according to following equation (4).
Wherein KISpeed, t are tracked for integral1For the first count value.After calculating integral tracking speed, test pattern
Signal 603 can be disabled to return to operating mode.After clock signal 606 is locked to input signal 601, test pattern letter
Numbers 603 can be enabled again to enter the second time interval of test pattern.
In the second time interval of test pattern, timer 673 can start timing, and switch 642 can end and make to filter
641 normal operation of wave device.When judging that mistake occurs for data-signal 607, timer 673 stops timing to generate the second counting
Value, and ratio tracking speed is calculated according to the second count value, default unit gap and integral tracking speed.For example,
Timer 673 can calculate ratio tracking speed according to following equation (5).
Wherein KPSpeed, t are tracked for ratio2For the second count value.Calculating ratio tracking speed and integral tracking speed
After, when can calculate the tracking input data 601 of clock pulse data recovery circuit 600 according to aforesaid equation (3), clock pulse letter
Numbers 606 phase change amount.
[fourth embodiment]
A kind of shake tolerance estimating and measuring method for clock pulse data recovery circuit is proposed in fourth embodiment.Rapid pulse at this time
It can be the clock pulse reflex circuit of Fig. 1, Fig. 4 or Fig. 6 according to reflex circuit.Substantially, clock pulse in the fourth embodiment replys electricity
Road has included at least phase detector, filter circuit, control oscillator and decision circuitry.This control oscillator can be digital control
Oscillator or voltage-controlled oscillator processed.In addition, clock pulse data recovery circuit may also include if carrying out implementation in the form of analogy
Charge pump.Wherein, phase detector, filter circuit, control oscillator and decision circuitry function and operation all it is stated that as above,
Herein and repeat no more.
Fig. 7 is the flow chart that shake tolerance estimating and measuring method is painted according to fourth embodiment.In step s 701, judge to survey
Die trial formula signal designation operating mode or test pattern.If operating mode, in step S702, second phase signal is set
It is identical to first phase signal.If test pattern, in step S703, start timing and set second phase signal inversion in
First phase signal.In step S704, judge whether data-signal occurs mistake.If data-signal has generation mistake, in step
In rapid S705, stop timing to generate at least one count value, and at least one tracking speed is calculated according to count value.So
And each step can be implemented as various forms of circuits, for example, Fig. 1 or the circuit for reversing 120 in Fig. 4 and calculate electricity in Fig. 7
Circuit for reversing 620 and counting circuit 670 in road 160 or Fig. 6, but the present invention and not subject to the limits.
Here, the shake tolerance of clock pulse data recovery circuit indicates tolerable phase variation amount.For example, if
The phase of a certain frequency jitter signal is 0.8UI, but mistake does not occur for data-signal, then it represents that clock pulse data recovery circuit
This frequency shake tolerance at least more than be equal to 0.8UI.In this embodiment, due to having calculated clock pulse data recovery
The tracking speed of circuit, therefore the shake tolerance of clock pulse data recovery circuit can be calculated with the mode of simulation.
Fig. 8 is please referred to, Fig. 8 is the waveform diagram that dither signal and clock signal are painted according to fourth embodiment.Assuming that
Input signal has dither signal 810, and clock signal 820 can be exported by controlling oscillator then, as seen from Figure 8 clock signal
820 be in tracking dither signal 810.When the amplitude of dither signal 810 or bigger frequency, then clock signal 820 and shake are believed
Phase difference 830 between numbers 810 may be bigger.If the phase difference 830 between clock signal 820 and dither signal 810 is greater than
0.5UI is then likely to result in the mistake of data-signal.In this embodiment, since the tracking for having obtained clock pulse data circuit is fast
Degree, therefore clock signal 820 can be generated with the mode of calculating, the shake that can thus calculate under different frequency is held
Degree of bearing.
Fig. 9 is the flow chart that shake tolerance estimating and measuring method is painted according to fourth embodiment.In this embodiment, in Fig. 9
Each step can be implemented as multiple procedure codes, after clock pulse data recovery circuit calculates tracking speed, these tracking speed
It can transmit to another electronic device, thus electronic device executes each step in Fig. 9.Here, clock pulse data recovery circuit calculates
Tracking speed out includes ratio tracking speed and integral tracking speed.
In step S901, generate analog input signal, and set in analog input signal the amplitude of dither signal with
Frequency.It in this embodiment, is that the clock signal of fixed frequency is carried into (carry) data-signal plus dither signal to multiply, most
What modulation went out afterwards is analog input signal.Wherein the frequency of clock signal can according to the specification of clock pulse data recovery circuit and
It is fixed.
In step S902, simulation clock pulse is generated according to integral tracking speed, ratio tracking speed and analog input signal
Signal.For example, can be according to the phase change amount of equation (3) (following appended) calculating simulation clock signal.Here, t is simulation
Elapsed time after input signal is identical as the simulation phase of clock signal.For example, in fig. 8, at time point 840
Analog input signal is identical as the simulation phase of clock signal 820, then can be the time 841 to calculate the phase at time point 850
The t of equation (3) is brought into obtain phase change amount 842.
Go back to Fig. 9, in step S903, judge analog input signal and simulate clock signal between phase difference whether
Less than default unit gap.If the phase difference between analog input signal and simulation clock signal is less than default unit gap, table
Show that mistake can't occur for data-signal, therefore the amplitude of dither signal can be adjusted in step S904 with the weight in step S901
It is new to generate analog input signal.For example, the amplitude of dither signal can be progressively decreased.
If the phase difference between analog input signal and simulation clock signal is not less than default unit gap, in step S905
In, the amplitude for setting dither signal corresponds to the shake tolerance of dither signal frequency.
In step S906, the frequency of adjustment dither signal is determined whether to.For example, can determine whether the frequency of dither signal is
It is no to be more than or equal to a maximum frequency, if otherwise continuing the frequency of adjustment dither signal, if not adjusting dither signal
Frequency.
Frequency to adjust dither signal adjusts the frequency of dither signal in step S901 in step s 907
Regenerate analog input signal.For example, the frequency of dither signal can be incrementally increased.
Figure 10 is that the schematic diagram for calculating shake tolerance is painted according to fourth embodiment.It is first dither signal in Figure 10
Vibration good fortune be set as amplitude maximum UI_max, then adjust down, until analog input signal and simulation clock signal between
Phase difference be less than 0.5UI, find the shake tolerance of a certain frequency whereby.After finding the shake tolerance of all frequencies
Available curve 1010, this indicates the mistake that can be all tolerated in the shake below of curve 1010 without data occur.
In the clock pulse data recovery circuit and shake tolerance estimating and measuring method that above-described embodiment proposes, hold in estimation shake
Repeatedly input different frequency and amplitude jitter signal are not had to when degree of bearing.In this way, which shake tolerance can be estimated rapidly
Degree.
Although the present invention has been disclosed by way of example above, it is not intended to limit the present invention., any technical field
Middle tool usually intellectual, without departing from the spirit and scope of the present invention, when can make some changes and embellishment, thus it is of the invention
Protection scope when view the scope of which is defined in the appended claims subject to.
Claims (8)
1. a kind of clock pulse data recovery circuit of estimation shake tolerance characterized by comprising
One phase detector, to detect the phase difference between an input signal and a clock signal to export at least one first phase
Position signal；
One circuit for reversing is coupled to the phase detector, to according to an at least first phase signal and test pattern letter
Number to export an at least second phase signal；
One filter circuit is coupled to the circuit for reversing, and to filter this, at least a second phase signal is digital control to generate one
Signal；
One numerically-controlled oscillator is coupled to the filter circuit, to generate the clock signal according to the digital controlled signal；
One decision circuitry, to sample the input signal according to the clock signal to obtain a data-signal；And
One counting circuit is coupled to the decision circuitry, to judge whether the data-signal occurs mistake,
Wherein, when the test mode signal indicates an operating mode, which sets an at least second phase signal
It is identical to an at least first phase signal,
Wherein, when the test mode signal indicates a test pattern, which starts timing, and the circuit for reversing is anti-
To an at least first phase signal to generate an at least second phase signal,
Wherein when judge during the test pattern data-signal occur mistake when, the counting circuit stop timing with generate to
A few count value, and at least one tracking speed is calculated according to an at least count value and a default unit gap,
Wherein the filter circuit includes proportional gain amplifier and integral gain amplifier,
Wherein in a first time section of the test pattern, the circuit for reversing enable proportional gain amplifier and the forbidden energy product
Divide gain amplifier,
Wherein in one second time interval of the test pattern, the circuit for reversing forbidden energy proportional gain amplifier and the enable product
Divide gain amplifier.
2. the clock pulse data recovery circuit of estimation shake tolerance according to claim 1, which is characterized in that reversion electricity
Road includes:
One first multiplexer, one first input end are coupled to the phase detector, and one second input terminal is anti-phase coupled to this
Phase detector, a control terminal receive the test mode signal,
Wherein when the test mode signal indicates the operating mode, which selects the first input end,
Wherein when the test mode signal indicates the test pattern, which selects second input terminal.
3. the clock pulse data recovery circuit of estimation shake tolerance according to claim 2, which is characterized in that the phase is detectd
Survey device is a positive and negative phase detector, and the number of an at least first phase signal is 2.
4. the clock pulse data recovery circuit of estimation shake tolerance according to claim 2, which is characterized in that reversion electricity
Road further include:
One second multiplexer, first input end receive a preset value, and the second input terminal is coupled to the output of first multiplexer
End；And
One third multiplexer, first input end are coupled to the output end of first multiplexer, and it is pre- that the second input terminal receives this
If value.
5. the clock pulse data recovery circuit of estimation shake tolerance according to claim 4, which is characterized in that the filtered electrical
Road includes:
One proportional gain amplifier, input terminal are coupled to the output end of second multiplexer；
One integral gain amplifier, input terminal are coupled to the output end of the third multiplexer；
One delay circuit, input terminal are coupled to the output end of the integral gain amplifier；And
One adder, input terminal are coupled to the output end of the proportional gain amplifier and the output end of the delay circuit.
6. the clock pulse data recovery circuit of estimation shake tolerance according to claim 5, which is characterized in that
Wherein during the operating mode, which selects second input terminal of second multiplexer, and this
Three multiplexers select the first input end of the third multiplexer,
Wherein in a first time section of the test pattern, which selects second input of second multiplexer
End, and the third multiplexer selects second input terminal of the third multiplexer,
Wherein in one second time interval of the test pattern, which selects first input of second multiplexer
End, and the third multiplexer selects the first input end of the third multiplexer.
7. the clock pulse data recovery circuit of estimation shake tolerance according to claim 6, which is characterized in that this at least one
Count value includes one first count value and one second count value, which includes ratio tracking speed and a product
Divide tracking speed,
Wherein in the first time section of the test pattern, when judging that mistake occurs for the data-signal, which stops
Only timing is to generate first count value, and calculates ratio tracking according to first count value and the default unit gap
Speed,
In second time interval of the test pattern, when judging that mistake occurs for the data-signal, which stops meter
When to generate second count value, and integral tracking speed is calculated according to second count value and the default unit gap
Degree.
8. a kind of shake tolerance estimating and measuring method for clock pulse data recovery circuit, which is characterized in that the clock pulse data recovery
Circuit includes a phase detector, a filter circuit, a control oscillator and a decision circuitry, and wherein the phase detector is detected
To generate an at least first phase signal, which filters at least phase difference between one input signal and a clock signal
One second phase signal is to generate a control signal, which generates the clock signal according to the control signal, this is sentenced
Deenergizing samples the input signal according to the clock signal to obtain a data-signal, which includes:
During an operating mode, sets an at least second phase signal and be identical to an at least first phase signal；
During a test pattern, beginning timing and reversely an at least first phase signal are to generate an at least second phase
Signal；
Judge whether the data-signal occurs mistake；And
When judging that mistake occurs for the data-signal during the test pattern, stop timing to generate an at least count value, and
Speed is tracked according to calculating at least one during an at least count value and a default unit,
Wherein at least one tracking speed includes that an integral tracking speed and a ratio track speed, the shake tolerance estimation side
Method further include:
An analog input signal is generated, the amplitude and a frequency of a dither signal in the analog input signal are set；
Speed, ratio tracking speed and the analog input signal, which are tracked, according to the integral generates a simulation clock signal；
Judge the phase difference between the analog input signal and the simulation clock signal whether less than a default unit gap；
If the phase difference between the analog input signal and the simulation clock signal adjusts this and trembles not less than the default unit gap
The amplitude of dynamic signal is to regenerate the analog input signal；And
If the phase difference between the analog input signal and the simulation clock signal is less than the default unit gap, the shake is set
The amplitude of signal corresponds to a shake tolerance of the frequency, and adjusts the frequency of the dither signal to regenerate
The analog input signal.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201018229A (en) * | 2008-10-30 | 2010-05-01 | Himax Tech Ltd | Demodulator device and demodulation method for reducing PCR jitter |
| US8249207B1 (en) * | 2008-02-29 | 2012-08-21 | Pmc-Sierra, Inc. | Clock and data recovery sampler calibration |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009123372A1 (en) * | 2008-04-04 | 2009-10-08 | Snu Industry Foundation | Clock and data recovery circuit with eliminating data-dependent jitters |
| US8989329B2 (en) * | 2013-03-15 | 2015-03-24 | Intel Corporation | Eye width measurement and margining in communication systems |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8249207B1 (en) * | 2008-02-29 | 2012-08-21 | Pmc-Sierra, Inc. | Clock and data recovery sampler calibration |
| TW201018229A (en) * | 2008-10-30 | 2010-05-01 | Himax Tech Ltd | Demodulator device and demodulation method for reducing PCR jitter |
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