CN106409834A - 以纳米颗粒作为电荷俘获层的杂化电介质非易失性存储器 - Google Patents
以纳米颗粒作为电荷俘获层的杂化电介质非易失性存储器 Download PDFInfo
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Abstract
为了研究可印刷的纳米浮栅晶体管,提出了尺寸小于30nm的Si/SiO2核/壳纳米结构,其可作为UV固化的有机‑无机杂化栅电介质中的电荷俘获点。本发明的新颖性来自于通过溶胶‑凝胶法在低温下制备高质量的有机/无机杂化栅电介质层,和还在此电介质层中引入由高密度的硅纳米颗粒形成的单层结构。此纳米结构与电介质材料无明显界面缺陷,保持高品质的电介质层。通过对电介质层进行UV固化附加低温热固化的处理,从杂化电介质中成功移除了固定电荷俘获缺陷。仅与由Si/SiO2核/壳纳米结构形成的电荷俘获层相关的移动电荷清晰地展示了印制电子器件的电荷存储效应。每个硅纳米颗粒表面均匀的二氧化硅薄壳充当闪存器件的隧道层,简化了印制纳米浮栅存储器件的制备。
Description
技术领域
本发明涉及一种可印刷的非易失性存储器,特别是涉及一种在低温下通过溶液法制备用于闪存晶体管的有机/无机杂化电介质层的方法,尤其是涉及一种制备以纳米颗粒作为电荷俘获层的非易失性存储器的方法。
背景技术
在本说明书中引用了下列参考文献。通过引用的方式将这些参考文献的公开作为整体并入本文。
参考文献列表:
[1].Y.J.Park等人,IEEE Trans on Dielectrics and Electrical Insulation 17(4),1135-1163(2010)
[2].2003年4月,PROCEEDINGS OF IEEE 91(4),闪存的介绍
[3].Kim等人,Appl.Phys.Lett.,96,033302(2010)
[4].T.sekitani,Science326,1516-1519(2009)
[5].C.C.Leu、S.T.Chen、F.K.Liu和C.X.Wu,J.Matter Cham,22,2089-2098(2012)
[6].B.Chandar Shekar、Jiyeon Lee和Shi-Woo Rhee,J.Chem.Eng.,21(1),267-285(2004)
[7].C.Z.Zhao等人,IEEE TRANSACTIONS ON ELECTRON DEVICES55(7),1647-1656(2008)
[8].June Whan Choi、Ho Gyu Yoon、Jai Kyeong Kim,Organic Electronics11,1145-1148(2010)
[9].Jin-Yong Lee等人,Appl.Phys.Lett,104,093514(2014)
电子器件传统上采用刚性半导体和高温制造方法制备。相比之下,印刷装置可以在低温下并在大面积聚合物衬底上进行处理。在许多电子器件中,数据存储是一个关键的要求。为了实现大面积的、柔性的和低成本的电子器件,在印刷存储装置上花费了大量的努力。例如,铁电(Fe)聚合物P(VDF-TrFE)被开发用于电气开关[1]。该电气开关在铁电聚合物P(VDF-TrFE)的厚度100nm以下时需要相对较大的矫顽磁场~MV/cm,且反转宏观极化所需要的矫顽磁场随薄膜厚度的减小而增加。因此,难以获得读写电压在20V以下的足够大的存储窗口,这是对低功耗应用的印刷存储器的挑战。因此,这些基于铁电聚合物的存储器晶体管与在低功耗和低电压下工作的商用读写系统是不兼容的[2]。
为了使非易失性存储器晶体管在低电压下工作(<10V)并可印刷在柔性衬底上,具有足够薄的电介质栅层浮栅薄膜晶体管被开发出来[3、4]。通过用金纳米颗粒(Au NPs)旋涂在3-氨丙基三甲氧基硅烷(APTMS)-改良的SiO2上来改善NPs/电介质界面,能抑制电荷从Au NPs浮栅泄漏。此外,通过使用APTMS作为中介物,可使用简单而有效的自组装单层(SAM)方法构建Au-SiO2核-壳NC电容[5]。但是,该存储器件的工艺温度高于400℃,从而该器件不能通过印刷技术制备。
为了开发高性能的可印刷的浮栅存储器晶体管,电介质层的重要性正吸引着越来越多的关注。许多研究已经试图利用聚合物材料、无机/有机混合材料、无机/有机双层和通过溶胶-凝胶反应的有机/无机杂化材料找到更好的栅电介质。在聚合物电介质膜的情况下,与无机电介质(Al2O39和Ta2O526)相比,缺点之一是由其厚度和低介电常数(PMMA 2.5-4.5、聚酰亚胺2.6-3.3、聚四氟乙烯1.9)引起的器件的高工作电压[6]。为了解决这个问题,已使用高k无机材料诸如Al2O3和Ta2O5作为栅绝缘体,其介电常数大大高于聚合物的介电常数。但金属氧化物具有相对较高的漏电流,并且这些薄膜只能用真空技术生产,诸如化学气相沉积、溅射或火焰水解。真空装置不适合于印刷技术所需的低温和低成本工艺。另外,高k无机纳米颗粒可被分散在聚合物基质中。然而,嵌入在聚合物基质中的具有高k纳米颗粒的纳米复合电介质层,具有粗糙的表面和高的栅漏电流以具有低开/关电流比。另外,难以消除由电介质层中的高k纳米颗粒产生的固定电荷俘获缺陷。电介质中的与这些固定电荷相关的俘获缺陷将成为抑制存储器晶体管中的移动充电/放电过程的致命屏蔽。基于溶胶-凝胶法得到的硅氧烷有机/无机杂化材料(hybrimers)是纳米复合材料,其中无机和有机成分通过共价键以分子尺度紧密连接在一起且纳米大小的低聚物被很好地分散。因为它们结合了玻璃和聚合物两者的特性,所以其具有低的漏电流密度并具有移除有机/无机杂化电介质中的固定电荷俘获缺陷的潜在机会。
然而,常规技术的存储行为和生产成本仍然不能满足市场的需求。
因此,存在一种未满足的需求,以具有制备适用于所需的存储行为和低生产成本的印刷电子器件的非易失性存储器晶体管的方法。
发明内容
为了满足操作浮栅晶体管的俘获能级和俘获点的要求,考虑采用纳米晶体浮栅代替常规平面浮栅作为信息存储的可替代方法。本发明的重点是将Si NPs作为电荷存储元件引入到非易失性存储器件中。基于纳米颗粒的存储器受益于减少的横向放电路径,并保证更大的保留时间、更低功耗和更快的操作。与金属纳米颗粒(Au、Ag、Al等)相比,应用Si纳米晶体作为浮栅能移除栅电介质中的金属污染物,这是减少器件漏电的关键。
在本发明中,使用Si/SiO2核/壳纳米结构作为浮栅存储器中的俘获位置。包围每个Si NPs的厚度为3nm至5nm的均匀的SiO2壳由硅核在溶液中均匀氧化而形成。,它减小了横向放电从而改善了保留特性。更重要的是,用Si NPs的单层结构作为俘获层,这种超薄而均匀的SiO2壳充当为闪存器件的隧道层,从而可印刷NPs浮栅存储器件的工作电压相当低。与常规的存储器叠层(衬底/隧道层/电荷俘获层/控制层/栅电极)[2、3、4、5]相比,本发明不涉及单独的隧道层,由高品质的SiO2壳充当为隧道层。
同样通过溶胶-凝胶法制备有机/无机杂化电介质层。随着溶胶-凝胶配方的优化和在低温下固化条件的改善,具有这种新型杂化电介质的存储器件表现出了相对低的漏电流密度,更重要的是它成功地在电介质中移除了与固定电荷相关的俘获缺陷。
因此,本发明的第一方面是提供一种用于非易失性存储器的可印刷的浮栅晶体管。
根据本发明的实施例,一种浮栅存储器件包括:衬底;形成在该衬底上的电荷俘获层,其中电荷俘获层包括有机/无机杂化电介质材料和硅/二氧化硅(Si/SiO2)核/壳纳米结构,并且Si/SiO2核/壳纳米结构嵌入在有机/无机杂化电介质材料内;形成在该电荷俘获层上的有机/无机杂化电介质层;和形成在有机/无机杂化层上的栅电极;其中每个Si/SiO2核/壳纳米结构包括Si核以及包围Si核且充当浮栅存储器件隧道层的SiO2壳。
本发明的第二方面是提供一种用于制备浮栅晶体管的方法。
根据本发明的实施例,一种用于制造浮栅存储器件的方法包括:提供衬底;将硅颗粒与包括有机溶剂和过氧化氢的溶液混合以形成硅/二氧化硅(Si/SiO2)核/壳纳米结构溶液,其中硅颗粒包括10nm至50nm的大小尺寸;在衬底上涂布Si/SiO2核/壳纳米结构溶液;以60℃至150℃范围内的干燥温度干燥Si/SiO2核/壳纳米结构溶液,以形成电荷俘获层;混合3-(甲基丙烯酰氧)丙基三甲氧基硅烷(MEMO)、丙醇锆(ZrPO)、甲基丙烯酸(MAA)和光引发剂,以形成有机/无机杂化电介质溶液;在电荷俘获层上涂布有机/无机杂化电介质溶液;用UV光固化电荷俘获层上的有机-无机杂化电介质溶液;以130℃至180℃范围内的固化温度热固化有机/无机杂化电介质溶液,以形成有机/无机杂化层;和在有机/无机杂化层上形成栅电极。
溶胶-凝胶法得到的电介质层的有机-无机杂化材料是纳米复合材料,其中无机和有机成分通过共价键以分子尺度紧密连接在一起且纳米大小的低聚物被很好地分散。电荷俘获层的俘获位置直接涉及能够通过改变纳米颗粒的密度控制的存储窗口。本发明的存储晶体管展示了具有低工作电压(小于7V)的、长保留时间(100KS)的、4.2V的存储窗口。
附图说明
在下文中,将参考附图更加详细地描述本发明的实施例,其中:
图1A示出了根据本发明实施例的以Si/SiO2核/壳结构作为电荷俘获层的可印刷浮栅非易失性存储器件的示意图;
图1B示出了现有技术中的常规浮栅非易失性存储器件的示意结构;
图2示出了根据本发明实施例的用于制造非易失性存储器件的方法的流程图;
图3是示出根据本发明实施例的在不同偏置电场下的漏电流密度的图;
图4是示出根据本发明实施例的用于制备混合溶胶-凝胶溶液的工艺流程的流程图;
图5A是根据本发明实施例的、单层Si/SiO2核/壳结构涂层的原子力显微镜(AFM)图像;
图5B是根据本发明的实施例的壳厚度为~5nm的Si/SiO2核/壳结构的TEM图像;
图6是示出根据本发明的实施例的Si/SiO2核/壳结构的存储效果的图;
图7A是示出根据本发明的实施例的通过改变电压应力时间调整存储行为的图;
图7B是示出根据本发明的实施例的通过改变应力电压幅值调整存储行为的图;
图8是示出根据本发明的实施例的基于Si/SiO2核/壳NPs的存储器的保留属性的图;和
图9A-D是根据本发明的实施例的在不同电压应力时间下分别对样品1、2、3和4测量的CV循环图。
具体实施方式
在下面的描述中,将阐述作为优选实例的存储器件和制造方法的相应实施例。对本领域的技术人员来说,在不偏离本发明的范围和精神的情况下,可进行包括增加和/或替换的修改,这将是显而易见的。可省略具体细节以免使本发明模糊不清;然而,该公开内容写成使本领域的技术人员能实施本文中的教导,而不必过多的试验。
在本发明中,提出了尺寸小于30nm的、作为UV可固化的有机-无机杂化栅电介质的俘获点的Si/SiO2核/壳纳米结构。本发明的新颖性不仅来自于通过溶胶-凝胶法在低温下制备高质量的有机/无机杂化栅电介质叠层,而且还在此电介质层中引入由高密度的硅纳米颗粒(NPs)形成的单层结构。此纳米结构与电介质材料无明显界面缺陷,并保持高品质的电介质层。在低温下通过溶液工艺制造的本存储器件中,由合成引入的与固定电荷俘获点相关的缺陷被从电介质层中成功移除,从而仅与Si/SiO2核/壳纳米结构相关的俘获功能展示了清楚的存储器的效果。
如图1A所示,本发明的浮栅晶体管100包括Si衬底101、具有嵌入在有机/无机杂化电介质材料106中的多个Si/SiO2核/壳纳米结构105的电荷俘获层102、有机/无机杂化电介质层103和栅电极104。电荷俘获层102形成在Si衬底101上。充当用于存储器件的控制层的有机/无机杂化电介质层103形成在电荷俘获层102上,且栅电极104形成在有机/无机杂化电介质层103上。Si/SiO2核/壳纳米结构105位于衬底101的表面上。电荷俘获层102包括单层的Si/SiO2核/壳纳米结构105。有机/无机杂化电介质层103包括与有机/无机杂化电介质材料106相同的材料。用于常规浮栅晶体管的典型栅极叠层包括衬底/隧道层/电荷俘获层/控制层/栅电极,如图1B所示[2、3、4、5]。通常,作为用于闪存晶体管的隧道层的非常薄的氧化物必须通过高温和/或缓慢的真空工艺来制备[2、5]。本发明不涉及单独的隧道层的制备,这大大简化了闪存栅晶体管的制备。
优选地,Si/SiO2核/壳纳米结构的尺寸在10nm至50nm的范围内,并因为俘获点被形成在单层涂层中,所以电荷俘获层的厚度在10nm至50nm的范围内。电荷俘获层包括纳米结构的密度在1x1010cm-2至1x1012cm-2的范围内。在本发明中,厚度为3nm至5nm的SiO2壳充当闪存器件中的隧道层。优选地,SiO2壳的厚度为5nm。电介质层的厚度在300nm至800nm的范围内。
图2示出了根据本发明实施例的制备非易失性存储器件的方法的流程图。在步骤201中,提供衬底。在步骤202中,准备Si/SiO2核/壳纳米结构溶液。在步骤203中,在衬底上涂布Si/SiO2核/壳纳米结构溶液。在步骤204中,干燥Si/SiO2核/壳纳米结构溶液以形成电荷俘获层。在步骤205中,准备有机/无机杂化电介质溶液。在步骤206中,在电荷俘获层上涂布有机/无机杂化电介质溶液。在步骤207中,用UV固化和热固化使有机/无机杂化电介质溶液固化以形成有机/无机杂化电介质层。在步骤208中,在电介质层上制备栅电极。
通过用乙醇和过氧化氢混合硅纳米颗粒来准备Si/SiO2核/壳纳米结构溶液。该硅纳米颗粒的平均尺寸为30nm以下。与1nm至5nm的量子尺寸相比,这种尺寸大概30nm大小的纳米颗粒产率能够得到显著提高。也如本发明所证明的,30nm-纳米颗粒能形成用于非易失性存储器的有效电荷俘获层。较大的纳米颗粒(>50nm)将会影响随后的杂化电介质的膜质量。Si/SiO2核/壳纳米结构溶液通过浸渍法涂布在衬底上。纳米结构溶液还可通过其他方法诸如喷雾、刮刀、喷墨印刷或旋涂,涂布在衬底上。优选地,为了减少电荷泄漏,将这些纳米结构涂布在衬底上以形成单层。
优选地,根据所使用的涂布方法,纳米结构溶液中的硅颗粒的重量比可为1%至10%的范围内。硅纳米颗粒溶液的溶剂可包括但不限于异丙醇、正丙醇、乙醇、甲醇、丙酮等。H2O2与溶剂的体积比在5%至20%的范围内。
通过混合3-(甲基丙烯酰氧)丙基三甲氧基硅烷(MEMO)、丙醇锆(ZrPO)和甲基丙烯酸(MAA),来准备有机/无机杂化电介质溶液。MEMO:ZrPO的比例涉及有机物和无机物的混合成分,优选为7:3或6:4至5:5。添加用于UV固化的光引发剂,以将用于热固化的固化温度降低到180℃以下,从而得到高质量的混合电介质层。
有机-无机杂化电介质溶液通过浸涂涂布在电荷俘获层上,然后进行UV固化并在130℃至180℃的低温下热固化。溶胶-凝胶溶液也可通过其他方法诸如喷雾、刮刀、喷墨印刷或旋涂,涂布在电荷俘获层上。
UV固化是制备用于浮栅存储器的高质量的杂化电介质的关键。UV固化附加低温热固化将会有效地移除合成杂化电介质中的固定电荷缺陷。可在UV固化之前,用60℃至150℃的范围内的预干燥温度执行预干燥有机-无机杂化电介质溶液。
实例
实例1
制备具有Si/SiO2核/壳纳米结构作为电荷俘获层的非易失性存储器件的优选实施例示出如下。选择电阻率为15-25Ohm-cm的轻掺杂硅晶片作为衬底,然后涂布单层的Si/SiO2核/壳纳米结构作为电荷俘获层。再之后,通过浸涂形成厚度为0.5um-1.0um的杂化电介质层作为控制层。最终,通过印刷银浆形成顶部和底部电极。该器件面积被定义为2mmX2mm。
本发明中的有机-无机杂化栅电介质溶液,通过使用3-(甲基丙烯酰氧)丙基三甲氧基硅烷(MEMO)、丙醇锆(ZrPO)和甲基丙烯酸(MAA)之间的溶胶-凝胶反应来合成。利用这种有机/无机杂化前驱体溶液,通过浸涂法能得到高k电介质层以控制电介质的厚度。在UV固化和热固化后,通过杂化电介质层的电流密度相对较低,如图3所示,其中图3中的混合物1、2和3代表一个批次中的不同的样品。
在图4中,示出了有机/无机杂化电介质的溶胶-凝胶过程和浸涂的工艺流程。例如,首先以HCl为催化剂,部分水解3-(甲基丙烯酰氧)丙基三甲氧基硅烷(MEMO,19.5mmol)。用HCl控制pH值以提高水解。在5mL的1-丙醇中,混合各为10.5mmol的丙醇锆(ZrPO)和甲基丙烯酸(MAA)。在搅拌MEMO达30分钟之后,混合两种溶液。添加更多的DI水以促进反应。MEMO:ZrPO:MAA:水为6.5:3.5:3.5:18的摩尔比。将该溶液密封并搅拌一整夜,然后加入1wt%的光引发剂1-羟基环己基苯基甲酮(HCHPK)并用1-丙醇稀释以控制浓度。用0.22um微孔膜过滤该溶液。再之后,通过典型的浸渍涂布机将溶液沉积在衬底(PET、玻璃或Si晶片)上。然后,在110℃的热板上使涂层先预干达30分钟。然后,用戴马斯蓝波200以20mW/cm2执行UV固化达5分钟。最后,在170℃的热炉中实施热固化达3小时。
在乙醇(EtOH)/H2O2溶液中,硅纳米颗粒(Si NPs)能被容易地氧化以形成Si/SiO2核/壳结构。平均尺寸<30nm的这些纳米结构将被分散到乙醇溶液中,并通过浸渍涂布在衬底上。在图5A中,示出了原子力显微镜(AFM)下的典型的单层涂层。图5B中的高分辨率透射电子显微镜(TEM)图像示出SiO2壳具有~5nm的厚度。
清楚观察到由仅与电荷俘获层上的Si/SiO2核/壳纳米结构相关的移动充电/放电造成的图6所示的存储行为。关于无硅纳米结构的样品的电容与电压(CV)特性,其电荷俘获层没有示出表示无任何固定电荷缺陷的高品质杂化电介质的任何滞后效应。已经通过改变电压应力时间(图7A)和应力电压幅值(图7B)调整存储窗口(CV环的宽度),这种对存储窗口的控制能力可以提供对不同的柔性电子的应用。
虽然基于Si/SiO2核/壳纳米颗粒的纳米浮栅晶体管存储器的驱动电压不大于10V,但是,如图8所示在用75ms内的P/E速度104s编程/擦除(P/E)试验之后,存储窗口剩余75%。
实例2
为了优化高质量杂化电介质层的溶胶-凝胶过程,对不同杂化电介质的以下样品进行了研究,如表1所示。所有样品使用与实例1相同的器件结构。在栅极处施加不同时间的电压应力,来测量这些器件的电容与电压(CV)的循环。施加电压应力的脉冲宽度时间可在存储器充电/放电过程期间改变CV循环的宽度。然而,如果电介质中有显著的固定电荷缺陷,则将屏蔽存储器的充电/放电过程,从而CV循环的宽度将变得对电压应力时间不敏感[7]。
表1纳米浮栅存储器件的杂化电介质的研究
样品1类似于实例1中的样品,在以20mW/cm2的UV固化5分钟之后,通过170℃3小时热固化来完成其固化过程。样品2将更少的ZrPO混合到电介质中且同样通过20mW/cm25min和170℃3h来固化。从样品1(图9A)和样品2(图9B)两个样品的不同电压应力时间下的CV循环看出,随着应力时间延长,环宽度显著增加。这是存储器件中的俘获层的典型的充电/放电过程。在样品2中有较少的ZrPO的高k成分。所以样品2的平带电容为~114pF,略低于样品1的165pF。
然而,无UV固化的样品3指示在电介质中可能存在一些固定缺陷,其涉及一些具有-OH基团的混合材料[8]。其CV循环对电压应力时间保持不敏感,如图9C所示。UV光照射应该对在无机(高k)和有机成分之间的分子尺度形成良好交联键非常关键。比较样品1和样品3,高强度的UV光可有效抑制-OH基团的形成。受益于改进的溶胶-凝胶配方和更强大的UV光,样品1的杂化电介质显示出了比引用文献【8】的情况更好的性能[8]。因此,这种高品质的杂化电介质能满足非易失性存储器件的严格要求。
作为附加的参考,在样品4中,将二氧化钛纳米颗粒分散到PMMA中并制备到存储器中作为电介质层。样品4的电压应力时间下的CV循环的演变在图9D中示出。即使将500ms的脉冲施加在栅极上,循环宽度也不会变得对应力时间敏感。在样品4的电介质中有强烈的固定电荷缺陷,其中涉及关于二氧化钛纳米颗粒与PMMA之间的界面缺陷。在[8]中已经描述了混合于聚合物基质中的充当电荷中心的无机纳米颗粒,这些电介质中的固定电荷将破坏浮栅存储器结构的电荷俘获层。
本发明的杂化电介质也可在其他薄膜晶体管、或纳米浮栅晶体管、或平面浮栅晶体管中找到关键应用。
本发明的这些Si/SiO2核/壳纳米结构也可充当为引用文献[9]中的电阻开关存储器件(命名为memoristor)的超级电荷捕获点。
为了说明和描述目的已经提供了本发明的上述说明。其并非意图在于详尽的或限制本发明为公开的精确形式。对本领域的技术人员来说,许多修改和变化将是显而易见的。
为了最好地解释本发明的原则及其实际应用,选择并描述了实施例,从而使本领域的其他技术人员理解本发明的各种实施例,和适合于设想的特定用途的各种修改。其意图在于本发明的范围由下面的权利要求和它的等价物限定。
Claims (20)
1.一种用于制造浮栅存储器件的方法,包括:
提供衬底;
将硅颗粒与包括乙醇和过氧化氢H2O2的溶液混合以形成硅/二氧化硅Si/SiO2核/壳纳米结构溶液,其中硅颗粒包括10nm至50nm的尺寸,硅颗粒包括Si/SiO2核/壳纳米结构溶液的1%至10%的重量比,且乙醇与过氧化氢的体积比在5%至20%的范围内;
在衬底上涂布Si/SiO2核/壳纳米结构溶液;
以60℃至80℃范围内的干燥温度干燥Si/SiO2核/壳纳米结构溶液,以形成电荷俘获层;
混合3-(甲基丙烯酰氧)丙基三甲氧基硅烷MEMO、丙醇锆ZrPO、甲基丙烯酸MAA和光引发剂,以形成有机/无机杂化电介质溶液,其中MEMO与ZrPO的体积比在7:3至5:5范围内;
在电荷俘获层上涂布有机/无机杂化电介质溶液;
以60℃至150℃范围内的预干燥温度预干燥有机/无机杂化电介质溶液;
用UV光固化电荷俘获层上的有机/无机杂化电介质溶液;
以130℃至180℃范围内的固化温度热固化有机/无机杂化电介质溶液,以形成有机/无机杂化层;和
在有机/无机杂化层上形成栅电极。
2.一种制备浮栅存储器件的方法,包括:
提供衬底;
将硅颗粒与包括有机溶剂和过氧化氢的溶液混合以形成硅/二氧化硅Si/SiO2核/壳纳米结构溶液,其中硅颗粒包括10nm至50nm的尺寸;
在衬底上涂布Si/SiO2核/壳纳米结构溶液;
以60℃至150℃范围内的干燥温度干燥Si/SiO2核/壳纳米结构溶液,以形成电荷俘获层;
混合3-(甲基丙烯酰氧)丙基三甲氧基硅烷MEMO、丙醇锆ZrPO、甲基丙烯酸MAA和光引发剂,以形成有机/无机杂化电介质溶液;
在电荷俘获层上涂布有机/无机杂化电介质溶液;
用UV光固化电荷俘获层上的有机-无机杂化电介质溶液;
以130℃至180℃范围内的固化温度,热固化有机/无机杂化电介质溶液,以形成有机/无机杂化层;和
在有机/无机杂化层上形成栅电极。
3.根据权利要求2所述的方法,其中硅颗粒包括30nm的尺寸。
4.根据权利要求2所述的方法,其中硅颗粒包括Si/SiO2核/壳纳米结构溶液的1%至10%的重量比。
5.根据权利要求2所述的方法,其中有机溶剂是异丙醇、正丙醇、乙醇、甲醇或丙酮。
6.根据权利要求2所述的方法,其中有机溶剂与H2O2的体积比在5%至20%的范围内。
7.根据权利要求2所述的方法,其中MEMO与ZrPO的体积比在7:3至5:5的范围内。
8.根据权利要求2所述的方法,其中干燥温度在60℃至80℃的范围内。
9.根据权利要求2所述的方法,其中混合MEMO、ZrPO、MAA和光引发剂以形成有机/无机杂化电介质溶液的步骤进一步包括:
用盐酸HCL水解MEMO以形成第一溶液;
混合ZrPO、MAA和丙醇以形成第二溶液;
混合第一溶液、第二溶液和水以形成第三溶液;
将1-羟基环己基苯基甲酮HCHPK作为光引发剂添加到第三溶液中;和
用1-丙醇稀释具有HCHPK的第三溶液。
10.根据权利要求9所述的方法,其中第三溶液包括MEMO:ZrPO:MAA:水为6.5:3.5:3.5:18的摩尔比。
11.根据权利要求2所述的方法,其中用浸渍法将Si/SiO2核/壳纳米结构溶液涂布在衬底上,并用浸渍法将有机/无机杂化电介质溶液涂布在电荷俘获层上。
12.根据权利要求2所述的方法,进一步包括在用UV光固化的步骤之前,以60℃到150℃范围内的预干燥温度,预干燥有机-无机杂化电介质溶液。
13.一种浮栅存储器件,包括:
衬底;
形成在所述衬底上的电荷俘获层,其中所述电荷俘获层包括有机/无机杂化电介质材料和硅/二氧化硅Si/SiO2核/壳纳米结构,并且Si/SiO2核/壳纳米结构嵌入在有机/无机杂化电介质材料内;
形成在电荷俘获层上的有机/无机杂化电介质层;和
形成在有机/无机杂化层上的栅电极;和
其中每个Si/SiO2核/壳纳米结构包括被SiO2壳包围的Si核,该SiO2壳充当浮栅存储器件的隧道层。
14.根据权利要求13所述的器件,其中Si/SiO2核/壳纳米结构包括10nm至50nm的大小尺寸,其中SiO2壳包括3nm至5nm的厚度。
15.根据权利要求13所述的器件,其中Si/SiO2核/壳纳米结构包括30nm的尺寸。
16.根据权利要求13所述的器件,其中电荷俘获层包括颗粒密度在1x1010cm-2至1x1012cm-2范围内的Si/SiO2核/壳纳米结构。
17.根据权利要求13所述的器件,其中电荷俘获层包括在10nm至50nm范围内的厚度。
18.根据权利要求13所述的器件,其中电荷俘获层包括单层的Si/SiO2核/壳纳米结构。
19.根据权利要求13所述的器件,其中有机/无机杂化层由(甲基丙烯酰氧)丙基三甲氧基硅烷、锆和甲基丙烯酸形成。
20.根据权利要求13所述的器件,其中有机/无机杂化层包括在300nm至800nm范围内的厚度。
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