CN106409685B - A method of removal trench sidewall deposition object - Google Patents
A method of removal trench sidewall deposition object Download PDFInfo
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- CN106409685B CN106409685B CN201610822713.5A CN201610822713A CN106409685B CN 106409685 B CN106409685 B CN 106409685B CN 201610822713 A CN201610822713 A CN 201610822713A CN 106409685 B CN106409685 B CN 106409685B
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- 238000000034 method Methods 0.000 title claims abstract description 41
- 230000008021 deposition Effects 0.000 title claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 42
- 229910052751 metal Inorganic materials 0.000 claims abstract description 42
- 238000000151 deposition Methods 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims abstract description 23
- 230000010415 tropism Effects 0.000 claims abstract description 16
- 238000004544 sputter deposition Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 claims description 5
- 230000008020 evaporation Effects 0.000 claims description 5
- 238000001704 evaporation Methods 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000007788 liquid Substances 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 description 13
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 5
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000011982 device technology Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000013049 sediment Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention relates to a kind of methods for removing trench sidewall deposition object, comprising: S1, the depositing operation that user's tropism is strong in the flute surfaces for be formed with metal form medium；Medium on the weak etching technics removal trenched side-wall of S2, user's tropism, exposes the metal on side wall；The metal exposed on the weak etching technics removal trenched side-wall of S3, user's tropism；And S4, removal the top of the groove and the remaining medium in bottom, expose the metal of the top of the groove and bottom.
Description
Technical field
The present invention relates to technical field of semiconductors, specifically, being related to a kind of method for removing trench sidewall deposition object.
Background technique
In semiconductor device design, groove is a kind of common structure feature.As shown in Figure 1, appended drawing reference 10 indicates
Semiconductor material, appended drawing reference 12 and 14 respectively indicate the metal electrode for being formed in the top of the groove and bottom, 16 table of appended drawing reference
Show trenched side-wall.In order to achieve the purpose that function optimization and reduce cost, in these groove structures, the top and bottom of groove
Size a, c be all it is the smaller the better, often reach the limit of related photoetching or dry etch process.
In certain groove structures, top, side wall and the bottom of groove may need to connect different electrodes, answer in device
Different current potentials is endowed in.Therefore good electrical insulating property is needed to have between them.JFET device as shown in Figure 2
In, groove is formed in N-type semiconductor material 20, the metal electrode 22 on the top of groove can be source electrode, the gold on bottom
Belonging to electrode 24 may be grid, and appended drawing reference 26 and 28 respectively indicates the P-doped zone and N-doped zone of JFET device.Grid source
Between need at least bear 15V typical switching voltage it is poor, side wall attachment metal may result in grid source conducting or electric leakage,
Component failure.
Since the top of the groove and the size of bottom have all been the limit of technique, to become metal electrode is placed above just
Challenge.In order to reduce resistance, the two metal electrodes need to occupy the entire area of the top of the groove and bottom as far as possible, and cannot be mutual
It is in contact and destroys electrical isolation.In order to solve this problem, there has been proposed so-called " autoregistration " process, device is utilized
The geometrical characteristic on surface disposably, while depositing the metal of the top of the groove and bottom.
Above " autoregistration " process, defect are to be easy on side wall also deposited metal simultaneously, cause such as source grid
Between short circuit or electric leakage.In order to avoid this phenomenon, the general evaporation of metal deposition for selecting high directivity, and meanwhile it is most ideal
The case where be to allow trench profile that inverted trapezoidal, as shown in figure 3, wherein semiconductor is indicated with appended drawing reference 30, metal 30 and 32 is presented
It is respectively formed in the bottom and top of inverted trapezoidal groove.However in some cases, realize that inverted trapezoidal is not easy to, such as carbon
The hardness of silicon nitride material is very big, and etching is very difficult, and it is just highly difficult can to obtain subvertical side wall.In fact, source
Short circuit or electric leakage between grid, the often most important yield loss source of silicon carbide JFET device.
Therefore, it is still necessary to which finding one kind can be in " autoregistration " technique, and the method for avoiding trenched side-wall kish is
Improve the yield of a kind of groove structure device technology and the key of reliability.
Summary of the invention
The present invention utilizes the dielectric deposition and etching technics group of different directions common in the preceding road technique of semiconductor devices
It closes, to remove trenched side-wall relict sediment.
For this purpose, the present invention provides a kind of method for removing trench sidewall deposition object characterized by comprising
S1, the depositing operation that user's tropism is strong in the flute surfaces for be formed with metal form medium；
Medium on the weak etching technics removal trenched side-wall of S2, user's tropism, exposes the metal on side wall；
The metal exposed on the weak etching technics removal trenched side-wall of S3, user's tropism；And
S4, removal the top of the groove and the remaining medium in bottom, expose the metal of the top of the groove and bottom.
In a specific embodiment, the metal formed in S1 is the strong depositing operation formation of user's tropism.
In a specific embodiment, the depositing operation of the high directivity is collimated sputtering or evaporation.
In a specific embodiment, in S1, one in the PECVD and collimated sputtering for having significant lower electrode power is used
It is a to form the medium.
In a specific embodiment, in S2, the medium on the trenched side-wall is removed using wet-etching technology.
In a specific embodiment, in S3, the metal of inclination reactive ion etching removal exposing is used.
In a specific embodiment, in S4, the remaining medium is removed using buffered oxide etch liquid.
In a specific embodiment, the groove is formed by SiC material.
Detailed description of the invention
Fig. 1 shows typical groove structure according to prior art.
Fig. 2 shows groove structures in JFET device according to prior art.
Fig. 3 shows the cross-section structure of inverted trapezoidal groove according to prior art.
Fig. 4 a-e shows the device architecture sectional view of steps of a method in accordance with the invention.
Fig. 5 is shown according to method and step of the invention.
Specific embodiment
In order to illustrate more clearly of the present invention, the present invention is done below with reference to preferred embodiments and drawings further detailed
Explanation.Identical part is indicated in attached drawing with identical label.It will be appreciated by those skilled in the art that specifically described below
Content is illustrative and be not restrictive, and should not be limited the scope of the invention with this.
In the dielectric deposition stage of semiconductor device technology, it is often necessary to according to require selection process orientation it is strong
It is weak.Directionality is weak, refers to that each surface deposition medium of device geometries obtains thickness and tends to identical, also referred to as " conformality
(conformal) good " or " step coverage (step coverage) is good ".High directivity refers to device upper flat surface
Deposition thickness is greater than the deposition thickness of side wall.The directionality power of dielectric deposition can pass through selection deposition processing recipe or work
Skill parameter controls.For example " atomic layer deposition (ALD) ", " tetraethyl orthosilicate (TEOS) " or lower electrode power are very low
" plasma reinforced chemical vapour deposition (PECVD) " is all the work that good step spreadability is commonly realized in semiconductor technology
Skill.And there are " plasma reinforced chemical vapour deposition (PECVD) ", " collimated sputtering (collimated of significant lower electrode power
It) " etc. sputtering is then the dielectric deposition method of common high directivity.
The deposition method of metal can also directional power point, such as evaporation be high directivity metal deposit side
Method, these are well known to those skilled in the art.
Similarly, point of also directional power is etched in the preceding road technique of semiconductor devices.In the weak etching process of directionality
In, the etch rate on each surface of device is roughly the same.In the etching process of high directivity, the etching speed of device upper flat surface
Rate is greater than the etch rate of side wall.The directionality power of etching again may be by selective etching process or technological parameter
To control.The weak lithographic method of directionality has wet etching and chemically strong dry etching.The lithographic method of high directivity
There is the dry method of physical strong (emphasizing above device by the charged particle of electric field acceleration from top to bottom to the bombardment of exposed surface)
Etching.This physical strong dry etching often includes " reactive ion (RIE) " etching of inert gas or has significant
" inductively coupled plasma (ICP) " of lower electrode power is etched.
The present invention utilizes the medium/metal deposit and etching work of different directions common in the preceding road technique of semiconductor devices
Skill combination, to remove trenched side-wall kish.It is illustrated below in conjunction with Fig. 5 and Fig. 4 a-e.
As depicted in fig. 4-a, in flute surfaces deposited metal.Wherein, appended drawing reference 40 indicates semiconductor material, and 42 indicate institute
The metal of formation.The semiconductor material can be SiC.
In a preferred embodiment, the strong depositing operation of user's tropism forms metal, so that the gold formed on side wall
Belong to few as far as possible, to facilitate the later period to be easier to remove.
The technique of good directionality, such as collimated sputtering or evaporation.
As shown in Fig. 4-b, the depositing operation that user's tropism is strong in the flute surfaces for being formed with metal 42 forms medium
44, so that the medium on channel bottom and top is thicker than the medium on side wall.
In a preferred embodiment, using a formation in the PECVD and collimated sputtering for having significant lower electrode power
Medium 44.
Medium as shown in Fig. 4-c, on the weak etching technics removal trenched side-wall of user's tropism.
In one example, using the medium on wet-etching technology removal trenched side-wall, expose the metal on side wall.
In before the step of, much thicker than the medium on side wall of the medium of channel bottom and bottom, therefore make
When removing the medium on side wall with the weak etching technics of directionality, etch period is reasonably controlled, so that the medium quilt on side wall
Removal, and still there are certain thickness media for the top of the groove and bottom.
As shown in Fig. 4-d, the weak etching technics of user's tropism removes the metal exposed on trenched side-wall.
At this point, the metal of the top of the groove and bottom is due to there is media protection, and unaffected.
In a preferred embodiment, the metal exposed using inclination reactive ion etching removal.
As shown in Fig. 4-e, the top of the groove and the remaining medium in bottom are removed, exposes the metal of top and bottom.
Since the etching selection ratio of metal and medium is very high, the etching work of high directivity can be selected in this step
Skill is completed, and also be can choose the weak etching technics of directionality and is completed, does not do particular/special requirement.
In a preferred embodiment, it is made a return journey using buffered oxide etch liquid (BOE, Buffered Oxide Etch)
Except remaining medium.
In short, the thinking of this method is after autoregistration metal deposit, first with the process deposits of high directivity
One layer of medium, so that the dielectric thickness of the top of the groove and bottom is much larger than side wall medium thickness.Then utilization orientation weak quarter
Etching technique, the medium of removal devices trench sidewall surface, and on the top in flat surface and channel bottom plane, it leaves comparable
Dielectric thickness.Then the weak lithographic method of user's tropism, such as wet etching remove the metal exposed on side wall.In groove
Top and bottom, due to remaining the protection of medium, lower metal is retained.Then removed again with wet process or dry etching residual
Medium is stayed, the metal and clean trenched side-wall of the top of the groove and bottom are left.Any one has basic semiconductor technology knowledge
Operator/engineer can easily pass through the introduction and understand technical solution of the present invention, and phase is confirmed by experimental development
Answer process detail.
Present invention is particularly applicable in SiC device manufacture craft, it is not easy to realize ladder in SiC device manufacture craft to overcome
The deficiency of shape groove.
In the above-described embodiments, the deposit of side wall is metal.However, those skilled in the art, it is readily appreciated that, according to this
The method for inventing introduction, can remove other deposits on side wall.
Obviously, the above embodiment of the present invention be only to clearly illustrate example of the present invention, and not be pair
The restriction of embodiments of the present invention may be used also on the basis of the above description for those of ordinary skill in the art
To make other variations or changes in different ways, all embodiments can not be exhaustive here, it is all to belong to this hair
The obvious changes or variations that bright technical solution is extended out are still in the scope of protection of the present invention.
Claims (8)
1. a kind of method for removing trench sidewall deposition object, which is characterized in that including
S1, the depositing operation that user's tropism is strong in the flute surfaces for be formed with metal formed medium so that the top of the groove and
The dielectric thickness of bottom is greater than the dielectric thickness of trenched side-wall；
Medium on the weak etching technics removal trenched side-wall of S2, user's tropism, exposes the metal on side wall；
The metal exposed on the weak etching technics removal trenched side-wall of S3, user's tropism；And
S4, removal the top of the groove and the remaining medium in bottom, expose the metal of the top of the groove and bottom.
2. the method according to claim 1, wherein
The metal formed in S1 is the strong depositing operation formation of user's tropism.
3. according to the method described in claim 2, it is characterized in that,
The depositing operation of the high directivity is collimated sputtering or evaporation.
4. the method according to claim 1, wherein
In S1, the medium is formed using one in the PECVD and collimated sputtering for having significant lower electrode power.
5. the method according to claim 1, wherein
In S2, the medium on the trenched side-wall is removed using wet-etching technology.
6. the method according to claim 1, wherein
In S3, the metal of inclination reactive ion etching removal exposing is used.
7. the method according to claim 1, wherein
In S4, the remaining medium is removed using buffered oxide etch liquid.
8. such as method of any of claims 1-7, which is characterized in that
The groove is formed by SiC material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610822713.5A CN106409685B (en) | 2016-09-13 | 2016-09-13 | A method of removal trench sidewall deposition object |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610822713.5A CN106409685B (en) | 2016-09-13 | 2016-09-13 | A method of removal trench sidewall deposition object |
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| CN106409685A CN106409685A (en) | 2017-02-15 |
| CN106409685B true CN106409685B (en) | 2019-07-16 |
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| FR2579827B1 (en) * | 1985-04-01 | 1987-05-15 | Thomson Csf | METHOD FOR PRODUCING A SELF-ALIGNED GATE METALLIZATION FIELD-EFFECT TRANSISTOR |
| CN103839770B (en) * | 2012-11-21 | 2016-08-17 | 上海华虹宏力半导体制造有限公司 | Bottom deep trench, the process of figure is formed with top while of a kind of |
| CN105489755B (en) * | 2015-12-03 | 2017-11-03 | 中国科学院半导体研究所 | Vertical stratification limits the autoregistration preparation method of phase transition storage entirely |
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