CN106406974B - High-performance timer implementation method for virtual machine and virtual machine - Google Patents
High-performance timer implementation method for virtual machine and virtual machine Download PDFInfo
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Abstract
The invention provides a high-performance timer implementation method for a virtual machine and the virtual machine, wherein the method comprises the following steps: the partition GuestOS generates a timing requirement and writes a timing value into a high-precision timer register 0x 380; the partition CPU captures the operation of writing a 0x380 register privileged instruction, and generates VM _ Exit to Hypervisor processing; the embedded Hypervisor acquires the offset and the written value of the write register through the CPU, adds the offset and the written value to a timer configuration message, and sends the message to a high-speed communication queue; and the high-precision timer module acquires a timer configuration message from the high-speed communication queue and writes the timer configuration message into a hardware core register. Through the implementation of the invention, in the process of generating the timer configuration message and writing the timer configuration message into the timer, the hardware can decode the instruction and directly transmit the offset address and the written value of the register to the Hypervisor for processing, thereby essentially eliminating the time bottleneck generated by decoding the software instruction.
Description
Technical Field
The invention relates to the field of high-performance timing of virtual machines, in particular to a high-performance timer implementation method for a virtual machine and the virtual machine.
Background
In the application in the virtualization field, the performance of a virtual machine is a key index which is generally concerned, whether a virtual machine has the same performance as a physical machine or not is a difficult problem which is difficult to solve in the virtualization field for a long time, and the embedded virtualization has the characteristic of high real-time requirement due to the fact that the bearing service of the embedded virtualization has the high real-time requirement, so that the requirements on various performance indexes after virtualization are more strict, and the most critical one influencing the running indexes of the virtual machine is the precision problem of a virtual machine timer.
The existing embedded type virtualization high-precision timer processing flow is as follows: GuestOS configures the TimerInitial Count register timer value with an offset of 0x 380; writing a 0x380 register by hardware to generate VM _ Exit to Hypervisor, decoding the instruction and writing the instruction into a real hardware register; the system returns to GuestOS from Hypervisor to continue running; and the high-precision timer times until the hardware generates an interrupt, processes the interrupt from VM _ Exit to Hypervisor, converts the interrupt into a virtual interrupt and injects the virtual interrupt into an IDT interrupt processing flow of GuestOS.
The method has two aspects of key factors influencing the performance of the high-precision timer of the embedded virtual machine: the first is that writing a timing value to the 0x380 register at a time can generate one time of VM _ Exit to Hypervisor processing to generate instruction decoding operation to form a performance bottleneck; secondly, when the timing is up, the high-precision timer can send out an interrupt to generate VM _ Exit to Hypervisor processing, and then the interrupt is injected into the GuestOS IDT interrupt processing routine, so that the switching cost from VM _ Exit to Hypervisor and the hardware interrupt processing overhead are increased, and the high-precision timer has a large performance influence on the precision of the virtual machine timer.
Therefore, how to provide a high-performance timer implementation method with higher timer accuracy is a technical problem to be urgently solved by those skilled in the art.
Disclosure of Invention
The invention provides a high-performance timer implementation method for a virtual machine and the virtual machine, and aims to solve the problem of poor precision of a timer of the virtual machine.
The invention provides a high-performance timer implementation method for a virtual machine, which comprises the following steps: the partition GuestOS generates a timing requirement and writes a timing value into a high-precision timer register 0x 380; the partition CPU captures the operation of writing a 0x380 register privileged instruction, and generates VM _ Exit to Hypervisor processing; the embedded Hypervisor acquires the offset and the written value of the write register through the CPU, adds the offset and the written value to a timer configuration message, and sends the message to a high-speed communication queue; and the high-precision timer module acquires a timer configuration message from the high-speed communication queue and writes the timer configuration message into a hardware core register.
Further, when there are multiple partitions, the method further includes: the embedded Hypervisor integrates the core id where the partition VCPU initiating the register write operation is located and the address of the corresponding hardware post Interrupt descriptor, and adds the core id and the address to the timer configuration message.
Further, after sending the timer configuration message to the high-speed communication queue, notifying the high-precision timer module that the register writing operation is completed; and after receiving the notification, the high-precision timer module acquires a timer configuration message from the high-speed communication queue.
Further, the writing of the timer configuration message into the hardware core register by the high-precision timer module includes: and the high-precision timer module analyzes the timer configuration message, acquires the offset and the write value of the write register, determines the offset and the timing value of the timer and writes the offset and the timing value into the hardware Core timer.
Further, when there are multiple partitions, the method further includes: the high-precision timer module analyzes the timer configuration message, acquires the offset and the write value of a write register, the core id of a partition VCPU (virtual central processing unit) initiating the register write operation and the address of a corresponding hardware-position Interrupt descriptor, and stores the offset and the timing value of the timer into a virtual machine timer model by taking the core id of the VCPU and the address of the hardware-position Interrupt descriptor; the found minimum timer value is written into a hardware Core timer.
Further, the method also comprises the following steps: judging whether the hardware Core timer is in a non-timing state or not; if the hardware Core timer is in a non-timing state, the high-precision timer module searches a virtual machine timer data model and writes the found minimum timing value into the hardware Core timer; if the hardware Core timer is in a timed state, the write operation of the hardware Core timer is not performed.
Further, the method also comprises the following steps: and the core deploying the partition virtual machine closes the high-precision timer through the Hypervisor.
Further, the method also comprises the following steps: a core is selected where the embedded Hypervisor high precision timer module is running.
Further, the method also comprises the following steps: and constructing a high-speed communication channel between each partition virtual machine and the high-precision timer module on an embedded Hypervisor software layer.
Further, the method also comprises the following steps: and when the timing of the hardware Core timer reaches, sending an interrupt notification to a high-precision timer module, writing a high-precision timer interrupt mark into the partition PI descriptor by the high-precision timer module, and sending PI physical interrupt to the partition Core.
Further, when there are multiple partitions, the method further includes: the high-precision timer module acquires the core id and the virtual machine PI descriptor address information of the VCPU of the timed virtual machine from the virtual machine timer model, writes a high-precision timer interrupt mark into the corresponding PI descriptor according to the acquired virtual machine PI descriptor address, and sends PI physical interrupt to the corresponding core according to the acquired core id of the VCPU.
Further, the method also comprises the following steps: and the high-precision timer module deletes the partition timer data which completes the timed interrupt injection from the virtual machine timer model, reads the next minimum timer value from the virtual machine timer data model, and writes the read next minimum timer value of the virtual machine into the hardware Core timer.
The invention provides a virtual machine, which comprises: the partition GuestOS is used for generating timing requirements and writing timing values into the high-precision timer register 0x 380; the partition CPU is used for capturing the operation of writing the privileged instruction of the 0x380 register and generating VM _ Exit to Hypervisor processing; the embedded Hypervisor is used for acquiring the write register offset and the write value through the CPU, adding the write register offset and the write value to the timer configuration message, and sending the write register offset and the write value to the high-speed communication queue; and the high-precision timer module is used for acquiring the timer configuration message from the high-speed communication queue and writing the timer configuration message into the hardware core register.
Further, when there are multiple partitions, the embedded Hypervisor is further configured to integrate the core id where the partition VCPU initiating the register write operation is located and the address of the corresponding hardware post Interrupt descriptor, and add the core id and the address to the timer configuration packet.
Further, after sending the timer configuration message to the high-speed communication queue, the embedded Hypervisor is also used for notifying the high-precision timer module that the register writing operation is completed; the high-precision timer module is also used for acquiring a timer configuration message from the high-speed communication queue after receiving the notification.
Further, the high-precision timer module is used for analyzing the timer configuration message, acquiring the offset and the write value of the write register, determining the offset and the timing value of the timer, and writing the offset and the timing value into the hardware Core timer.
Further, when a plurality of partitions exist, the high-precision timer module is further configured to analyze a timer configuration message, obtain a write register offset and a write value, a core id of a partition VCPU initiating a register write operation, and a corresponding hardware posternturpett descriptor address, and store the timer offset and the timing value as the core id of the partition VCPU and the hardware posternturpett descriptor address in the virtual machine timer model; the found minimum timer value is written into a hardware Core timer.
Further, the high-precision timer module is also used for judging whether the hardware Core timer is in a non-timing state; if the hardware Core timer is in a non-timing state, searching a virtual machine timer data model, and writing the found minimum timing value into the hardware Core timer; if the hardware Core timer is in a timed state, the write operation of the hardware Core timer is not performed.
Further, the core deploying the partition virtual machine is also used for closing the high-precision timer through the Hypervisor.
Further, the embedded Hypervisor is also used for selecting a core, and the embedded Hypervisor high-precision timer module is operated in the core.
Furthermore, the embedded Hypervisor is also used for constructing a high-speed communication channel between each partition virtual machine and the high-precision timer module in a software layer.
Further, the hardware Core timer is also used for sending an interrupt notification to the high-precision timer module when the timing of the hardware Core timer reaches; the high-precision timer module is also used for writing a high-precision timer interrupt mark into the partition PI descriptor and sending PI physical interrupt to the partition core.
Further, when there are multiple partitions, the high-precision timer module is further configured to obtain, from the virtual machine timer model, the core id of the VCPU of the timed virtual machine and address information of the PI descriptor of the virtual machine, write a high-precision timer interrupt flag into the corresponding PI descriptor according to the obtained PI descriptor address of the virtual machine, and send a PI physical interrupt to the corresponding core according to the obtained core id of the VCPU.
Further, the high-precision timer module is further configured to delete the partition timer data that has completed the timed interrupt injection from the virtual machine timer model, read a next minimum timer value from the virtual machine timer data model, and write the read next minimum timer value of the virtual machine into the hardware Core timer.
The invention has the beneficial effects that:
the invention provides a new high-performance timer implementation method, in the process of generating a timer configuration message and writing the timer configuration message into a timer, a hardware does not need to write a 0x380 register to generate VM _ Exit to a Hypervisor to perform instruction decoding and then write the instruction into a real hardware register like the prior art, thus Guest OS writes the 0x380 register and does not need software to perform instruction decoding, the hardware can perform instruction decoding and directly transmit a register offset address and a write-in value to the Hypervisor in a VM _ Exit event for processing, and a time bottleneck generated by software instruction decoding is essentially eliminated; furthermore, after the timer arrives, the high-precision timer module writes a high-precision timer Interrupt mark into a post Interrupt descriptor, and then sends a post Interrupt inter-core Interrupt to a corresponding core id, and an Intel post Interrupt hardware virtualization mechanism can automatically complete Interrupt injection of the high-precision timers of the virtual machines in different partitions according to the configuration.
Drawings
Fig. 1 is a schematic structural diagram of a virtual machine according to a first embodiment of the present invention;
FIG. 2 is a flowchart of a high-performance timer implementation method according to a second embodiment of the present invention;
fig. 3 is a flowchart of a high-performance timer implementation method according to a third embodiment of the present invention.
Detailed Description
The invention will now be further explained by means of embodiments in conjunction with the accompanying drawings.
The first embodiment:
fig. 1 is a schematic structural diagram of a virtual machine according to a first embodiment of the present invention, and as can be seen from fig. 1, in this embodiment, the virtual machine 1 according to the present invention includes:
the GuestOS11 is used for generating timing requirements and writing timing values into the high-precision timer register 0x 380;
the partition CPU12 is used for capturing the operation of writing the privileged instruction of the 0x380 register and generating VM _ Exit to Hypervisor processing;
the embedded Hypervisor13 is used for acquiring the write register offset and the write value through the CPU, adding the write register offset and the write value to the timer configuration message, and sending the write register offset and the write value to the high-speed communication queue;
the high-precision timer module 14 is used for acquiring a timer configuration message from the high-speed communication queue and writing the timer configuration message into the hardware core timer 15;
the hardware core timer 15 is used to execute a timer.
In some embodiments, when there are multiple partitions, the embedded Hypervisor13 in the above embodiments is further configured to integrate and add a core id where the partition VCPU initiating the register write operation is located and an address of a corresponding hardware post Interrupt descriptor to the timer configuration packet.
In some embodiments, the embedded Hypervisor13 in the above embodiments is further configured to notify the high-precision timer module that the register writing operation is completed after sending the timer configuration message to the high-speed communication queue; the high-precision timer module is also used for acquiring a timer configuration message from the high-speed communication queue after receiving the notification.
In some embodiments, the high precision timer module 14 in the foregoing embodiments is configured to parse the timer configuration packet, obtain the write register offset and the write value, determine the timer offset and the timer value, and write the timer offset and the timer value into the hardware Core timer.
In some embodiments, when there are multiple partitions, the high-precision timer module 14 in the above embodiments is further configured to analyze a timer configuration packet, obtain a register write offset and a write value, a core id of a partition VCPU initiating a register write operation, and a corresponding hardware post Interrupt descriptor address, and store the timer offset and the timer value as the core id of the partition VCPU and the hardware post Interrupt descriptor address in the virtual machine timer model; the found minimum timer value is written to the hardware Core timer 15.
In some embodiments, the high precision timer module 14 in the above embodiments is further configured to determine whether the hardware Core timer 15 is in a non-timing state; if the hardware Core timer is in a non-timing state, searching a virtual machine timer data model, and writing the found minimum timing value into the hardware Core timer; if the hardware Core timer is in a timed state, the write operation of the hardware Core timer is not performed.
In some embodiments, the core deploying the partitioned virtual machine in the above embodiments is also used to turn off the high precision timer through Hypervisor 13.
In some embodiments, the embedded Hypervisor13 of the above embodiments is also used to select a core where the embedded Hypervisor high precision timer module 14 is running.
In some embodiments, the embedded Hypervisor13 in the above embodiments is also used to build a high-speed communication channel between each partition virtual machine and the high-precision timer module 14 at the software layer.
In some embodiments, the hardware Core timer 15 in the above embodiments is further configured to send an interrupt notification to the high-precision timer module 14 when the timing arrives; the high-precision timer module 14 is further configured to write a high-precision timer interrupt flag to the partition PI descriptor, and send a PI physical interrupt to the partition core.
In some embodiments, when there are multiple partitions, the high-precision timer module 14 in the foregoing embodiments is further configured to obtain, from the virtual machine timer model, a core id and virtual machine PI descriptor address information of a VCPU of a timed virtual machine, write a high-precision timer interrupt flag into a corresponding PI descriptor according to the obtained virtual machine PI descriptor address, and send a PI physical interrupt to the corresponding core according to the obtained core id of the VCPU.
In some embodiments, the high precision timer module 14 in the above embodiments is further configured to delete partition timer data that has completed timed interrupt injection from the virtual machine timer model, and read a next minimum timer value from the virtual machine timer data model, and write the read virtual machine next minimum timer value to the hardware Core timer.
Second embodiment:
fig. 2 is a flowchart of a high-performance timer implementation method according to a second embodiment of the present invention, and as can be seen from fig. 2, in this embodiment, the high-performance timer implementation method according to the present invention includes the following steps:
s201: the partition GuestOS generates a timing requirement and writes a timing value into a high-precision timer register 0x 380;
s202: the partition CPU captures the operation of writing a 0x380 register privileged instruction, and generates VM _ Exit to Hypervisor processing;
s203: the embedded Hypervisor acquires the offset and the written value of the write register through the CPU, adds the offset and the written value to a timer configuration message, and sends the message to a high-speed communication queue;
s204: and the high-precision timer module acquires a timer configuration message from the high-speed communication queue and writes the timer configuration message into a hardware core register.
In some embodiments, when there are multiple partitions, the method in the above embodiments further comprises: the embedded Hypervisor integrates the core id where the partition VCPU initiating the register write operation is located and the address of the corresponding hardware post Interrupt descriptor, and adds the core id and the address to the timer configuration message.
In some embodiments, after sending the timer configuration message to the high-speed communication queue, the method further includes notifying the high-precision timer module that the register writing operation is completed; and after receiving the notification, the high-precision timer module acquires a timer configuration message from the high-speed communication queue.
In some embodiments, the writing, by the high precision timer module in the above embodiments, the timer configuration message to the hardware core register includes: and the high-precision timer module analyzes the timer configuration message, acquires the offset and the write value of the write register, determines the offset and the timing value of the timer and writes the offset and the timing value into the hardware Core timer.
In some embodiments, when there are multiple partitions, the method in the above embodiments further comprises: the high-precision timer module analyzes the timer configuration message, acquires the offset and the write value of a write register, the core id of a partition VCPU (virtual central processing unit) initiating the register write operation and the address of a corresponding hardware-position Interrupt descriptor, and stores the offset and the timing value of the timer into a virtual machine timer model by taking the core id of the VCPU and the address of the hardware-position Interrupt descriptor; the found minimum timer value is written into a hardware Core timer.
In some embodiments, the method in the above embodiments further comprises: judging whether the hardware Core timer is in a non-timing state or not; if the hardware Core timer is in a non-timing state, the high-precision timer module searches a virtual machine timer data model and writes the found minimum timing value into the hardware Core timer; if the hardware Core timer is in a timed state, the write operation of the hardware Core timer is not performed.
In some embodiments, the method in the above embodiments further comprises: and the core deploying the partition virtual machine closes the high-precision timer through the Hypervisor.
In some embodiments, the method in the above embodiments further comprises: a core is selected where the embedded Hypervisor high precision timer module is running.
In some embodiments, the method in the above embodiments further comprises: and constructing a high-speed communication channel between each partition virtual machine and the high-precision timer module on an embedded Hypervisor software layer.
In some embodiments, the method in the above embodiments further comprises: and when the timing of the hardware Core timer reaches, sending an interrupt notification to a high-precision timer module, writing a high-precision timer interrupt mark into the partition PI descriptor by the high-precision timer module, and sending PI physical interrupt to the partition Core.
In some embodiments, when there are multiple partitions, the method in the above embodiments further comprises: the high-precision timer module acquires the core id and the virtual machine PI descriptor address information of the VCPU of the timed virtual machine from the virtual machine timer model, writes a high-precision timer interrupt mark into the corresponding PI descriptor according to the acquired virtual machine PI descriptor address, and sends PI physical interrupt to the corresponding core according to the acquired core id of the VCPU.
In some embodiments, the method in the above embodiments further comprises: and the high-precision timer module deletes the partition timer data which completes the timed interrupt injection from the virtual machine timer model, reads the next minimum timer value from the virtual machine timer data model, and writes the read next minimum timer value of the virtual machine into the hardware Core timer.
The present invention will now be further explained with reference to specific application scenarios.
The third embodiment:
fig. 3 is a flowchart of a high-performance timer implementation method according to a third embodiment of the present invention, and as can be seen from fig. 3, in this embodiment, the high-performance timer implementation method according to the present invention includes the following steps:
s301: and initializing the virtual machine.
The initialization comprises the following steps:
the core for deploying the partition virtual machine closes the high-precision timer through the Hypervisor to prevent unnecessary external interruption influence;
a core running embedded Hypervisor high-precision timer module is separated independently, the hardware function of the core high-precision timer is started, and the module provides clock sources for different partition high-precision timers;
constructing a high-speed communication channel between each partition virtual machine and the high-precision timer module on an embedded Hypervisor software layer, and providing a writing mechanism of 0x380 register timing values of different partitions to the high-precision timer module;
the embedded Hypervisor configures partition virtual machine hardware APIC Register Virtualization function, aims to enable GuestOS to write 0x380 Register without software to decode the instruction, enables hardware to decode the instruction and directly transmits the offset address and the written value of the Register to the Hypervisor to process in VM _ Exit event, and essentially eliminates the time bottleneck generated by software instruction decoding;
s302: and generating a timer configuration message by the partitions.
The embedded Hypervisor captures write processing operation of GuestOS on the 0x380 register, does not directly write in a hardware register of the current core, but writes a timing value, the current core id and a corresponding PostedInterruptdescriptor address into the high-precision timer module through a high-speed communication channel.
Specifically, the method comprises the following steps:
the high-precision GuestOS generates a timing requirement and writes a timing value into a high-precision timer register 0x 380;
CPU hardware captures the operation of writing a privileged instruction of a 0x380 register to generate VM _ Exit to Hypervisor processing;
the embedded Hypervisor acquires the offset and the write-in value of a write register through CPU hardware, integrates the core id of a partition VCPU initiating the register write operation with the corresponding hardware post Interrupt descriptor address, and configures a message through a timer to be packaged and sent to a high-speed communication queue;
the embedded Hypervisor sends an event to inform the high-precision timer module of completing the register writing operation;
and the high-precision timer module acquires the timer configuration message from the high-speed communication queue.
S303: the timing value is written to the hardware core timer.
And the high-precision timer module receives the high-precision timer messages configured by each partition virtual machine from the high-speed communication channel, updates the internal data model, calculates and analyzes the internal data model, and finally completes the configuration of the core hardware high-precision timer where the high-precision timer module is located.
Specifically, the method comprises the following steps:
the high-precision timer module receives the Hypervisor message event channel notification, proves that the high-precision timer timing message is written into the partition of the virtual machine at the moment, and prepares to read the timing message content from the communication queue;
the high-precision timer module analyzes the message event information to obtain a high-speed communication queue number, and reads a high-precision timer timing message written in the virtual machine partition from the queue;
the high-precision timer module analyzes the read virtual machine configuration timer message, and stores the core and hardware post Interrupt descriptor address of the VCPU operation in the message into a virtual machine timer data model by taking the timer offset and the timing value as indexes;
if the current hardware Core timer is in a non-timing state, the high-precision timer module searches a virtual machine timer data model, and writes the found minimum timing value into the hardware Core timer; and if the current hardware Core timer is in a timing state, not performing the write operation of the hardware Core timer.
S304: the hardware core timer is timed to arrive and generates an interrupt.
The method comprises the steps that a core hardware high-precision timer where a high-precision timer module is located is triggered to run after timing is reached, a partitioned virtual machine position Interrupt descriptor address and a core id which need timing processing are searched through an internal data model, after the data are found, a high-precision timer Interrupt mark is written into the partitioned virtual machine position Interrupt descriptor, then a partitioned Interrupt inter-core Interrupt is sent to the corresponding core id, an Intel partitioned Interrupt hardware virtualization mechanism can automatically complete Interrupt injection of the high-precision timers of different partitioned virtual machines according to the configuration, any VM _ Exit and Hypervisor intervention Interrupt processing cannot be generated in the process, and therefore performance can reach the level consistent with that of a physical machine
Specifically, the method comprises the following steps:
the hardware Core timer is timed to send an interrupt notification high-precision timer module;
the high-precision timer module acquires timed relevant virtual machine coreid and PI descriptor address information from a virtual machine timer data model;
writing a high-precision timer interrupt mark into a corresponding PI descriptor according to a virtual machine PI descriptor address obtained from a data model;
sending PI physical interruption to the core according to the core id of the VCPU obtained from the data model;
after the software Hypervisor completes the step, the hardware can automatically read the high-precision timer interrupt mark from the PI descriptor, automatically generate the high-precision timer interrupt and jump to GuestOS interrupt processing routine to execute, and the whole process cannot generate VM _ Exit, so that the performance is completely consistent with that of a physical machine.
S305: and writing next timing information in a hardware core timer.
The high-precision timer module deletes partition timer data which are injected by the timed interrupt from the virtual machine timer model, and reads the next minimum timing value from the virtual machine timer data model; and the high-precision timer module writes the read next minimum timing value of the virtual machine into the hardware Core high-precision timer.
In summary, the implementation of the present invention has at least the following advantages:
in the process of generating a timer configuration message and writing the timer configuration message into the timer, a hardware write 0x380 register to generate VM _ Exit to Hypervisor to perform instruction decoding and then write the instruction into a real hardware register is not needed like the prior art, so that Guest OS write 0x380 register does not need software to perform instruction decoding, the hardware can perform instruction decoding and directly transmit a register offset address and a write value to the Hypervisor for processing in a VM _ Exit event, and a time bottleneck generated by software instruction decoding is essentially eliminated;
furthermore, after the timer arrives, the high-precision timer module writes a high-precision timer Interrupt mark into a post Interrupt descriptor, and then sends a post Interrupt inter-core Interrupt to a corresponding core id, an Intel post Interrupt hardware virtualization mechanism can automatically complete Interrupt injection of the high-precision timers of the virtual machines of different partitions according to the configuration, and no VM _ Exit and Hypervisor intervention Interrupt processing are needed in the process, so that the performance can reach the level consistent with that of a physical machine;
furthermore, the core deploying the partition virtual machine closes the high-precision timer through the Hypervisor to prevent unnecessary external interruption influence;
further, a core running embedded Hypervisor high-precision timer module is separated independently, the hardware function of the core high-precision timer is started, and the module provides clock sources for the high-precision timers of different partitions;
furthermore, a high-speed communication channel between each partition virtual machine and the high-precision timer module is constructed in an embedded Hypervisor software layer, and a writing mechanism of 0x380 register timing values of different partitions into the high-precision timer module is provided.
The above embodiments are only examples of the present invention, and are not intended to limit the present invention in any way, and any simple modification, equivalent change, combination or modification made by the technical essence of the present invention to the above embodiments still fall within the protection scope of the technical solution of the present invention.
Claims (24)
1. A high-performance timer implementation method for a virtual machine is characterized by comprising the following steps:
the partition GuestOS generates a timing requirement and writes a timing value into a high-precision timer register 0x 380;
the partition CPU captures the operation of writing a 0x380 register privileged instruction, and generates VM _ Exit to Hypervisor processing;
the embedded Hypervisor acquires the offset and the written value of the write register through the CPU, adds the offset and the written value to a timer configuration message, and sends the message to a high-speed communication queue;
and the high-precision timer module acquires the timer configuration message from the high-speed communication queue and writes the timer configuration message into a hardware core timer.
2. The high performance timer implementing method of claim 1, when there are multiple partitions, further comprising: the embedded Hypervisor integrates the core id where the partition VCPU initiating the register write operation is located and the corresponding hardware PostedInterrupt descriptor address, and adds the core id and the corresponding hardware PostedInterrupt descriptor address to the timer configuration message.
3. The method for implementing high-performance timer according to claim 1, wherein after sending the timer configuration message to the high-speed communication queue, further comprising notifying the high-precision timer module that the register write operation is completed; and after receiving the notification, the high-precision timer module acquires the timer configuration message from the high-speed communication queue.
4. The method of claim 1, wherein the high-precision timer module writing the timer configuration packet to a hardware core timer comprises: and the high-precision timer module analyzes the timer configuration message, acquires the offset and the write value of the write register, determines the offset and the timing value of the timer, and writes the offset and the timing value into the hardware Core timer.
5. The high performance timer implementation method of claim 4, further comprising, when there are multiple partitions: the high-precision timer module analyzes the timer configuration message, acquires the write register offset and the write value, the core id of a partition VCPU initiating the register write operation and the corresponding hardware-position Interrupt descriptor address, and stores the core id and the hardware-position Interrupt descriptor address of the VCPU in a virtual machine timer model by using the timer offset and the timing value as the core id and the hardware-position Interrupt descriptor address of the VCPU; the found minimum timer value is written to the hardware Core timer.
6. The high performance timer implementing method of claim 5, further comprising: judging whether the hardware Core timer is in a non-timing state or not; if the hardware Core timer is in a non-timing state, the high-precision timer module searches a virtual machine timer data model and writes the found minimum timing value into the hardware Core timer; if the hardware Core timer is in a timed state, the write operation of the hardware Core timer is not performed.
7. The high performance timer implementing method of claim 1, further comprising: and the core deploying the partition virtual machine closes the high-precision timer through the Hypervisor.
8. The high performance timer implementing method of claim 1, further comprising: a core is selected, and the embedded Hypervisor high-precision timer module is operated on the core.
9. The high performance timer implementing method of claim 1, further comprising: and constructing a high-speed communication channel between each partition virtual machine and the high-precision timer module on an embedded Hypervisor software layer.
10. The high-performance timer implementing method of any one of claims 1 to 9, further comprising: and when the timing of the hardware Core timer is reached, sending an interrupt notification to the high-precision timer module, writing a high-precision timer interrupt mark into the partition PI descriptor by the high-precision timer module, and sending PI physical interrupt to the partition Core.
11. The high performance timer implementing method of claim 10, when there are a plurality of partitions, further comprising: the high-precision timer module acquires the core id of the VCPU of the timed virtual machine and the address information of the PI descriptor of the virtual machine from the virtual machine timer model, writes a high-precision timer interrupt mark into the corresponding PI descriptor according to the acquired PI descriptor address of the virtual machine, and sends PI physical interrupt to the corresponding core according to the acquired core id of the VCPU.
12. The high performance timer implementing method of claim 11, further comprising: and the high-precision timer module deletes the partition timer data which completes the timed interrupt injection from the virtual machine timer model, reads the next minimum timer value from the virtual machine timer data model, and writes the read next minimum timer value of the virtual machine into the hardware Core timer.
13. A virtual machine, comprising:
the partition GuestOS is used for generating timing requirements and writing timing values into the high-precision timer register 0x 380;
the partition CPU is used for capturing the operation of writing the privileged instruction of the 0x380 register and generating VM _ Exit to Hypervisor processing;
the embedded Hypervisor is used for acquiring the write register offset and the write value through the CPU, adding the write register offset and the write value to the timer configuration message, and sending the write register offset and the write value to the high-speed communication queue;
and the high-precision timer module is used for acquiring the timer configuration message from the high-speed communication queue and writing the timer configuration message into the hardware core timer.
14. The virtual machine according to claim 13, wherein when there are multiple partitions, the embedded Hypervisor is further configured to integrate and add a core id where a partition VCPU initiating a register write operation is located, and a corresponding hardware posternertupt descriptor address to the timer configuration packet.
15. The virtual machine according to claim 13, wherein the embedded Hypervisor is further configured to notify the high-precision timer module that the register writing operation is completed after sending the timer configuration packet to the high-speed communication queue; and the high-precision timer module is also used for acquiring the timer configuration message from the high-speed communication queue after receiving the notification.
16. The virtual machine according to claim 13, wherein the high-precision timer module is configured to parse the timer configuration packet, obtain the write register offset and the write value, determine a timer offset and a timer value, and write the timer offset and the timer value into the hardware Core timer.
17. The virtual machine according to claim 16, wherein when there are multiple partitions, the high precision timer module is further configured to parse the timer configuration packet, obtain the write register offset and the write value, a core id where a partition VCPU initiating a register write operation is located, and a corresponding hardware post Interrupt descriptor address, and store the core id and the hardware post Interrupt descriptor address where the VCPU is located in a virtual machine timer model with the timer offset and the timer value; the found minimum timer value is written to the hardware Core timer.
18. The virtual machine of claim 17, wherein the high-precision timer module is further to determine whether the hardware Core timer is in an untimed state; if the hardware Core timer is in a non-timing state, searching a virtual machine timer data model, and writing the found minimum timing value into the hardware Core timer; if the hardware Core timer is in a timed state, the write operation of the hardware Core timer is not performed.
19. The virtual machine of claim 13, wherein the core deploying the partitioned virtual machine is further configured to turn off a high precision timer via Hypervisor.
20. The virtual machine of claim 13 wherein the embedded Hypervisor is further configured to select a core at which to run the embedded Hypervisor high precision timer module.
21. The virtual machine according to claim 13, wherein the embedded Hypervisor is further configured to build a high-speed communication channel between each partitioned virtual machine and the high-precision timer module at a software layer.
22. The virtual machine according to any of the claims 13 to 21, wherein the hardware Core timer is further configured to send an interrupt notification to the high precision timer module when the timing arrives; and the high-precision timer module is also used for writing a high-precision timer interrupt mark into the partition PI descriptor and sending PI physical interrupt to the partition core.
23. The virtual machine according to claim 22, wherein when there are multiple partitions, the high-precision timer module is further configured to obtain, from the virtual machine timer model, the core id and the virtual machine PI descriptor address information of the VCPU of the timed virtual machine, write a high-precision timer interrupt flag into the corresponding PI descriptor according to the obtained virtual machine PI descriptor address, and send a PI physical interrupt to the corresponding core according to the obtained core id of the VCPU.
24. The virtual machine of claim 23, wherein the high precision timer module is further to delete partition timer data from the virtual machine timer model that has completed timed interrupt injection and read a next minimum timer value from the virtual machine timer data model and write the read virtual machine next minimum timer value to the hardware Core timer.
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| CN201510458635.0A CN106406974B (en) | 2015-07-30 | 2015-07-30 | High-performance timer implementation method for virtual machine and virtual machine |
| PCT/CN2015/089282 WO2016131247A1 (en) | 2015-07-30 | 2015-09-09 | Method for realizing high-performance timer using virtual machine and virtual machine |
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| CN108196934B (en) * | 2016-12-08 | 2022-04-26 | 阿里巴巴集团控股有限公司 | Timing setting method and device of timer and virtualization equipment |
| CN108241522B (en) * | 2016-12-27 | 2022-05-17 | 阿里巴巴集团控股有限公司 | Sleep state switching method and device in virtualization environment and electronic equipment |
| CN108512780B (en) * | 2017-02-28 | 2020-12-15 | 华为技术有限公司 | Timer implementation method and related device |
| CN112817701B (en) * | 2021-02-25 | 2024-03-12 | 北京火山引擎科技有限公司 | Timer processing method, device, electronic equipment and computer readable medium |
| CN114265775A (en) * | 2021-12-21 | 2022-04-01 | 中国科学院信息工程研究所 | Hardware-assisted virtualization environment core detection method and system |
| CN114489816A (en) * | 2021-12-22 | 2022-05-13 | 瑞芯微电子股份有限公司 | Timer device and method for providing timing |
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